Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 05/07

20070124561 - Active memory command engine and method: A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine,... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070124562 - Apparatus and method for generating packed sum of absolute differences: A microprocessor for generating a packed sum of absolute differences is disclosed. The microprocessor includes an instruction translator, for translating an MMX PSADBW macroinstruction into at least first and second microinstructions. The microprocessor includes an MMX unit, coupled to the instruction translator, for generating a result of the PSADBW macroinstruction... Agent: Huffman Law Group, P.C.

20070124563 - Processing device, method of determining internal configuration of processing device, and processing system: In order to execute desired operation on data to be processed of each data series to output processed data, a processing unit changes an arithmetic processing function by establishing a connection relation of internal components according to connection information. In each processing cycle, a control unit executes control processing to... Agent: Arent Fox PLLC

20070124564 - System and method for providing an extended platform for an operating system: A system and method of adding programming to a Symbian operating system. A binary component for use by the operating system, with the binary component including both a capability level and a trust level. The trust level is either equal to or higher than the capability level. If the trust... Agent: Foley & Lardner LLP

20070124565 - Reconfigurable processing array having hierarchical communication network: A processor includes multiple compute units and memory units arranged in groups of abutted tiles. Multiple tiles are arranged together along with input/output interfaces to form a processor system that can be configured to perform many different operations. A hierarchical communication network efficiently connects components within the tiles and between... Agent: Ambric, Inc. C/o Marger Johnson & Mccollom PC

20070124566 - Command decoder for microcontroller based flash memory digital controller system: A command decoder used for a microcontroller based Flash memory digital controller system includes multiple subsystems, including the command decoder, which serves as the main user interface for interpreting commands from a user and managing the priority of commands and command modes. The command decoder also stores crucial information including... Agent: Sawyer Law Group LLP

20070124567 - Processor system: A processor system capable of improving usability and performance of an on-chip heterogeneous multiprocessor is provided. The processor system has a processor and a memory, the processor including one control unit that reads a program, a plurality of arithmetic units that transmit a SIMD instruction of the program read by... Agent: Stanley P. Fisher Reed Smith LLP

20070124568 - Digital data processing apparatus having asymmetric hardware multithreading support for different threads: Asymmetric hardware support for a special class of threads is provided. Preferably, the special class threads are high-priority, I/O bound threads. In a first aspect, a multithreaded processor contains N sets of registers for supporting concurrent execution of N threads. At least one of the register sets is dedicated for... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070124569 - Method and apparatus for binding shadow registers to vectored interrupts: A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond to the interrupts. The exception vector considers the type of interrupt and the... Agent: Huffman Law Group, P.C.

20070118720 - Technique for setting a vector mask: A technique to generate a vector mask. In particular, at least one embodiment of the invention matches at least two instructions used in generating a vector mask and prevents at least one of the two instructions from executing if the correlation is found.... Agent: Blakely Sokoloff Taylor & Zafman

20070118721 - Apparatus for controlling access in a data processor: A data processor apparatus comprises a plurality of processor elements, a memory having a plurality of parts, and a first switching element associated with the first processor element for switchably coupling the first processor element to its associated memory part for at least one of read and write access. The... Agent: Blackwell Sanders Peper Martin LLP

20070118722 - Method for compressing instruction codes: The present invention discloses an apparatus for removing unnecessary instruction and method thereof. The apparatus and operating method thereof include: a comparing circuit for comparing a plurality of instructions and a predetermined pattern, so as to generate a plurality of comparing signals; a control logic for generating an instruction-selecting signal... Agent: Birch Stewart Kolasch & Birch

20070118723 - Computer system and method that eliminates the need for an operating system: A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The hardware/firmware layer eliminates the need for an operating system. Each of the Managers comprises a microcontroller associated with a firmware embedded in ROM... Agent: Mintz, Levin, Cohn, Ferris, Glovsky And Popeo, P.C.

20070118724 - Java hardware accelerator using microcode engine: A hardware Java accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java bytecode into multiple native instructions. A reissue buffer is... Agent: Hahn And Moodley LLP

20070118725 - Cpu life-extension apparatus and method: A CPU life-extension apparatus and method makes a processor appear to be an upgraded CPU to substantially all software applications accessed thereby, thereby reducing the need and expense of upgrading a selected processor. A CPU life-extension module translates new instructions, intended for a CPU upgrade, into instructions recognized by the... Agent: Pate Pierce & Baird

20070118727 - Processor for processing data of different data types: A processor architecture, for example, a SIMD processor architecture, includes at least two arithmetic/logic units to implement data processing, a data memory arrangement or a memory device interface to a memory arrangement to store data of different data types, an addressing unit to generate access addresses for the data to... Agent: Patrick J. O'shea O'shea, Getz & Kosakowski, P.C.

20070118726 - System and method for dynamically selecting storage instruction performance scheme: A system and method for dynamic switching between performance schemes is presented. The software program uses an instruction to indicate whether a pacing performance scheme or a flushing performance scheme is to be used. The selection by the software program is stored in a hardware register that the processor uses... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20070113046 - Data processing device and method: A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher... Agent: Kenyon & Kenyon LLP

20070113047 - Risc microprocessor architecture implementing multiple typed register sets: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24])... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070113048 - Low-power co-processor architecture: A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing units of the co-processor, and also a bus slave circuit coupled to a system bus of the system, to selected ones of the... Agent: Texas Instruments Incorporated

20070113049 - Electronic circuit with a fifo pipeline: An asynchronously operated FIFO pipe-line (10a-d) comprises a plurality of handshake chains functionally in parallel. Successive data items are each passed by selecting a chain dependent on a value of the data item. The FIFO pipelines (10a-d) comprise successive pipe-line stages, each pipe-line stage with respective handshake stages (12, 16)... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070113050 - Processor accessing a scratch pad on-demand to reduce power consumption: The present invention provides processing systems, apparatuses, and methods that access a scratch pad on-demand to reduce power consumption. In an embodiment, an instruction fetch unit initiates an instruction fetch. When a scratch pad is enabled, an instruction is retrieved from the scratch pad in parallel with a translation of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070113051 - Apparatus and method for live loading of control applications in a process control environment: A method includes identifying one or more data elements common to both a first version of a class and a second version of a class. The first version of the class is associated with at least one first function block. The method also includes automatically generating program code for transferring... Agent: Honeywell International Inc.

20070113052 - Method for compressing instruction codes: The present invention discloses a method for compressing instruction codes. This method comprises: compressing an instruction block including a plurality of instructions according to Huffman-Encoding technique; determining whether it's necessary to insert no-operation (nop) instructions among the plurality of compressed instructions according to a compression ratio, so as to generate... Agent: Birch Stewart Kolasch & Birch

20070113053 - Multithreading instruction scheduler employing thread group priorities: A concurrent instruction dispatch apparatus includes a group indicator for each of a plurality of threads that indicates which one of a plurality of groups of the threads the thread belongs to. A group priority indicator for each group indicates an instruction dispatch priority relative to the other groups. Selection... Agent: Huffman Law Group, P.C.

20070113054 - Component with a dynamically reconfigurable architecture: The invention relates to a component with a large grain dynamically reconfigurable architecture for processing of data by processing units organized in rows and connected to each other through interconnections so as to enable processing in pipeline or parallel mode or in dependent rows mode. All data types may be... Agent: Thelen Reid Brown Raysman & Steiner LLP

20070113055 - Apparatus and method for improving single thread performance through speculative processing: An apparatus, method and computer program product are provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070113056 - Apparatus and method for using multiple thread contexts to improve single thread performance: An apparatus, method and computer program product are provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070113059 - Loop detection and capture in the intstruction queue: A system and a method to identify a conditional branch instruction having a program counter and a target address, and increment a loop count each time the program counter and the target address equal a stored program counter and a target address. The system and method additionally includes assignment of... Agent: Texas Instruments Incorporated

20070113058 - Microprocessor with indepedent simd loop buffer: An apparatus comprising detection logic configured to detect a loop among a set of instructions, the loop comprising one or more instructions of a first type of instruction and a second type of instruction and a co-processor configured to execute the loop detected by the detection logic, the co-processor comprising... Agent: Texas Instruments Incorporated

20070113057 - Processor utilizing a loop buffer to reduce power consumption: The present invention provides processing systems, apparatuses, and methods that reduce power consumption with the use of a loop buffer. In an embodiment, an instruction fetch unit of a processor initially provides instructions from an instruction cache to an execution unit of the processor. While instructions are provided from the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070113060 - Floating point status/control register encodings for speculative register field: In one embodiment, a processor comprises a plurality of storage locations, a decode circuit, and a status/control register (SCR). Each storage location is addressable as a speculative register and is configured to store result data generated during execution of an instruction operation and a value representing an update for the... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070106877 - Single-chip multiple-microcontroller architecture and timing control method for the same: A single-chip multiple-microcontroller architecture and a timing control method for the same are proposed. The single-chip multiple-microcontroller architecture comprises multiple microcontrollers integrated into a single chip. Different microcontrollers are separately executed at mutually exclusive timings, equivalent to several microcontrollers that operate parallel and independently. Therefore, multiple microcontrollers can be realized... Agent: Rosenberg, Klein & Lee

20070106878 - High-performance, superscalar-based computer system with out-of-order instruction execution: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units,... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070106879 - Semiconductor device: A semiconductor device that comprises a dynamic reconfigurable processor that changes functions thereof by changing configuration data and executes a plurality of threads in a time-sharing mode, wherein the dynamic reconfigurable processor FE has a thread management table having a plurality of flag registers for each thread that indicate whether... Agent: Miles & Stockbridge PC

20070106880 - System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor: An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070106881 - Bit-wise operation followed by byte-wise permutation for implementing dsp data manipulation instructions: A digital signal processor having a generalized byte-wise data movement permute facility configurable at the microarchitectural level to execute a variety of ISA-level byte-wise data manipulation instructions. A bit-wise data manipulation facility is also provided. By combining the two, the bit-wise facility can be greatly simplified without sacrificing ISA-level functionality... Agent: Richard Calderwood Stexar Corp.

20070106882 - Byte-wise permutation facility configurable for implementing dsp data manipulation instructions: A digital signal processor having a generalized byte-wise data movement permute facility configurable at the microarchitectural level to execute a variety of ISA-level byte-wise data manipulation instructions. A bit-wise data manipulation facility is also provided. By combining the two, the bit-wise facility can be greatly simplified without sacrificing ISA-level functionality... Agent: Richard Calderwood Stexar Corp.

20070106883 - Efficient streaming of un-aligned load/store instructions that save unused non-aligned data in a scratch register for the next instruction: A memory block with any source alignment is streamed into general-purpose registers (GPRs) as aligned data using a streaming load instruction. A streaming store instruction reads the aligned data from the GPRs and writes the data into memory with any destination alignment. Data is streamed from any source alignment to... Agent: Stuart T Auvinen

20070106884 - Hybrid memory system for a microcontroller: A microcontroller, system and method are provided. In one implementation, a microcontroller is provided that includes a first memory operable to store instructions for normal operational use of the microcontroller, a second memory operable to store patch code instructions during debugging of the instructions within the first memory, and a... Agent: Sawyer Law Group LLP

20070106886 - Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch: Systems and methods that allow for performing a single transaction that both commands a device to perform an action and return the result to a processor without the processor having to send a separate request for the result. In addition, a processor may perform a context switch switching between threads... Agent: Huffman Law Group, P.C.

20070106885 - Expansion of a stacked register file using shadow registers: One or more Shadow Register Files (SRF) are interposed between a Physical Register File (PRF) and a Backing Store (BS) in a shadow register file system. The SRFs comprise dual-port registers connected serially in a chain of arbitrary depth from the PRF. A Register Save Engine has random access to... Agent: Qualcomm Incorporated

20070106887 - Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts: A multiprocessing system, including a multithreading microprocessor and a multiprocessor operating system (OS), is disclosed. The microprocessor includes a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a translation lookaside buffer (TLB), shared by... Agent: Huffman Law Group, P.C.

20070106889 - Configurable instruction sequence generation: A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070106888 - Return address stack recovery in a speculative execution computing apparatus: A technique recovers return address stack (RAS) content and restores alignment of a RAS top-of-stack (TOS) pointer for occurrences of mispredictions due to speculative operation, out-of-order instruction processing, and exception handling. In at least one embodiment of the invention, an apparatus includes a speculative execution processor pipeline, a first structure... Agent: Gunnison Mckay & Hodgson, LLP

20070101100 - System and method for decoupled precomputation prefetching: A program stream is executed at a first processing engine, the program stream including multiple iterations of a first load instruction. An instruction loop is executed at a second processing engine separate from the first processing engine substantially in parallel with an execution of the program stream at the first... Agent: Larson Newman Abel Polansky & White, LLP

20070101101 - Microprocessor: In a microprocessor that interprets instructions where a same instruction code can be interpreted as separate instructions with respectively different data lengths, a data length storage circuit that stores data length selection-use information is provided in a decoding unit. Instructions instructing storage to a general-purpose register, such storage of 8-bit... Agent: Mcdermott Will & Emery LLP

20070101102 - Selectively pausing a software thread: A method, system and computer-usable medium are presented for pausing a software thread in a process. An instruction from a first software thread in the process is sent to an Instruction Sequencing Unit (ISU) in a processing unit. The instruction from the first software thread is then sent to a... Agent: Dillon & Yudell LLP

20070101103 - High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution: The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070101104 - Microprocessor with improved data stream prefetching: A microprocessor has a data stream prefetch unit for processing a data stream prefetch instruction. The instruction specifies a data stream and a speculative stream hit policy indicator. If a load instruction hits in the data stream, then if the load is non-speculative the stream prefetch unit prefetches a portion... Agent: Huffman Law Group, P.C.

20070101105 - Microprocessor with improved data stream prefetching: A microprocessor has a plurality of stream prefetch engines for prefetching a respective data stream from the system memory into the microprocessor cache memory and an instruction decoder that decodes instructions of the microprocessor instruction set. The instruction set includes a stream prefetch instruction that returns an identifier uniquely associating... Agent: Huffman Law Group, P.C.

20070101106 - System and method for handling load and/or store operations in a superscalar microprocessor: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070101107 - Reconfigurable processor and apparatus: Provided is a reconfigurable processor or apparatus capable of changing a logic without any loss of input data and without any deterioration of data computing processing performance, which is impossible with a conventional reconfigurable processor or apparatus. The processor or apparatus is realized by a system for distributing only data... Agent: Stanley P. Fisher Reed Smith LLP

20070101108 - Method and apparatus for providing context switching of logic in an integrated circuit: A method and apparatus provides context switching of logic in an integrated circuit using one or more test scan circuits that use test data during a test mode of operation of the integrated circuit to store and/or restore non-test data during normal operation of the integrated circuit. The integrated circuit... Agent: Advanced Micro Devices, Inc. C/o Vedder Price Kaufman & Kammholz, P.C.

20070101109 - Processor and method for checking a condition for conditional execution of a program command: A processor comprises checking and control devices, first register, and register bank. The control device checks a condition or a subcondition of the condition within a first time unit based on a first subcondition checked within a second time unit preceding the first time unit, a second subcondition checked within... Agent: Maginot, Moore & Beck

20070101110 - Processor core and method for managing branch misprediction in an out-of-order processor pipeline: A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070101111 - Processor core and method for managing program counter redirection in an out-of-order processor pipeline: A processor core and method for managing program counter redirection in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.