Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 04/07

20070094481 - Neural modeling and brain-based devices using special purpose processor: A special purpose processor (SPP) can use a Field Programmable Gate Array (FPGA) or similar programmable device to model a large number of neural elements. The FPGAs can have multiple cores doing presynaptic, postsynaptic, and plasticity calculations in parallel. Each core can implement multiple neural elements of the neural model.... Agent: Fliesler Meyer LLP

20070094482 - Boundary address registers for selection of isa mode: An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070094483 - Pipelined digital signal processor: Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed... Agent: Iandiorio & Teska

20070094484 - Backing store buffer for the register save engine of a stacked register file: A Backing Store Buffer is interposed between a Physical Register File and the Backing Store in a stacked register file architecture. A Register Save Engine temporarily stores data from registers in the Physical Register File allocated to inactive procedures on-chip, freeing the registers to be re-allocated to new procedures. When... Agent: Qualcomm Incorporated

20070094485 - Data processing system and method: A data processing system and method. The data processing system includes a processor core that executes a program; a loop accelerator that has an array consisting of a plurality of data processing cells and executes a loop in a program by configuring the array according to a set of configuration... Agent: Sughrue Mion, PLLC

20070088933 - Interface between subsystems in a digital processing device: A subprocessor is used to interface between subsystems and to reduce the amount of dedicated hardware used to implement the subsystems in a hand-held computer. The subprocessor includes basic processing system resources such as random-access memory (RAM), read-only memory (ROM), a processor, input/output (I/O) facilities, etc. Selected functions in subsystems... Agent: Trellis Intellectual Property Law Group, PC

20070088934 - Multithread processor: To guarantee response time while strictly maintaining the priority specified by software, a processor (1) which is a multithread processor having a thread multiplexer (10), and an issue information buffer (ISINF). An instruction code, and issue information (isid) for instructions issued at and after the next operating cycle which is... Agent: Miles & Stockbridge PC

20070088935 - Method and apparatus for delaying a load miss flush until issuing the dependent instruction: A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070088936 - Using computation histories to make predictions: Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not limited to) registers, memory locations, static values, and instruction program counters. The computation history may be used to make a prediction... Agent: Marger Johnson & Mccollom, P.C.

20070088937 - Computer-implemented method and processing unit for predicting branch target addresses: Under the present invention, a branch target address corresponding to a target instruction to be pre-fetched is predicted based on two values. The first value is a “predictor value” that is known for the branch target address. The second value is the address of the branch instruction from which the... Agent: Hoffman, Warnick & D'alessandro LLC

20070088938 - Shared interrupt control method and system for a digital signal processor: Techniques for the design and use of a digital signal processor, including (but not limited to) processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system process interrupts arising in a multithreaded processor by receiving in an interrupt register a plurality of interrupts of a statistically indeterminate... Agent: Qualcomm Incorporated

20070088939 - Automatic and dynamic loading of instruction set architecture extensions: A portion of microcode for a processor is stored outside the processor. If needed for execution, the processor loads the microcode from outside the processor into a microcode storage inside the processor. The microcode is loaded in the form of a microcode patch which consists of the microcode as well... Agent: Blakely Sokoloff Taylor & Zafman

20070083730 - Data processing device and method: The present invention relates to a method of coupling at least one (conventional) unit processing data in a sequential manner, e.g. a CPU, von-Neumann-Processor and/or microcontroller, the (conventional) unit for data processing comprising an instruction pipeline, and an array for processing data comprising a plurality of data processing cells, e.g.... Agent: Kenyon & Kenyon LLP

20070083732 - Parallel processor and image processing apparatus: A parallel processor includes a global processor which interprets a program and control controls the entirety of the parallel processor. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processing a plurality of sets of data. The global processor outputs... Agent: Cooper & Dunham, LLP

20070083731 - Processor automatically performing processor id setting and path setting and method of configuring multiprocessor: An ID determining portion determines a self processor ID according to an input port name receiving a control instruction and a sender processor ID stored in the received control instruction. The control instruction storing the self processor ID is output from each output port via a diverging portion. Therefore, the... Agent: Birch Stewart Kolasch & Birch

20070083733 - Reconfigurable circuit and control method therefor: A reconfigurable circuit and control method therefor, capable of enhancing efficiency of implementation of a pipeline process in processing elements and improve processing performance. Processing elements are reconfigured to form a circuit based on configuration information and execute a prescribed process. Memory units store configuration information for the processing elements.... Agent: Arent Fox PLLC

20070083735 - Hierarchical processor: Various embodiments are described relating to hierarchical processors.... Agent: Brake Hughes PLC C/o Portfolioip

20070083734 - Queue design supporting dependency checking and issue for simd instructions within a general purpose processor: A method, an apparatus and a computer program product are provided for the managing of SIMD instructions and GP instructions within an instruction pipeline of a processor. The SIMD instructions and the GP instructions share the same “front-end” pipelines within an Instruction Unit. Within the shared pipelines the Instruction Unit... Agent: Ibm Corporation (cs) C/o Carr LLP

20070083736 - Instruction packer for digital signal processor: A digital signal processor which uses a RISC/CISC style front end and a VLIW style back end. Sequential ISA instructions are decoded into μops having a programmatic ordering. The μops are packed into a VLIW-like instruction packet according to a set of rules enforcing machine policy on e.g. data dependency,... Agent: Richard Calderwood Stexar Corp.

20070083737 - Processor with efficient shift/rotate instruction execution: A processor is disclosed that efficiently executes shift/rotate instructions. The processor determines if each shift/rotate instruction in an instruction stream is an immediate shift/rotate instruction or a register dependent shift/rotate instruction. If the processor determines that a particular shift/rotate instruction is an immediate shift/rotate instruction, then the processor sends the... Agent: Mark P. Kahler

20070083738 - Multi-threaded processor architecture: A multi-threaded processor that is capable of responding to, and processing, multiple low-latency-tolerant events concurrently and while using relatively slow, low-power memories is disclosed. The illustrative embodiment comprises a multi-threaded processor, which itself comprises a context controller and a plurality of hardware contexts. Each hardware context is capable of storing... Agent: Demont & Breyer, LLC

20070083739 - Processor with branch predictor: Various embodiments are described relating to processors, branch predictors, branch prediction systems, and computing systems.... Agent: Brake Hughes PLC C/o Portfolioip

20070083741 - Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence: A microprocessor for predicting return instruction target addresses is disclosed. A branch target address cache stores a plurality of target address predictions and a corresponding plurality of override indicators for a corresponding plurality of return instructions, and provides a prediction of the target address of the return instruction from the... Agent: Huffman Law Group, P.C.

20070083740 - Method, apparatus, and computer program product for implementing polymorphic branch history table reconfiguration: A method, apparatus and computer program product are provided for implementing polymorphic branch history table (BHT) reconfiguration. A BHT includes a plurality of predetermined configurations corresponding predetermined operational modes. A first BHT configuration is provided. Checking is provided to identify improved performance with another BHT configuration. The BHT is reconfigured... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070083742 - System and method for time-of-life counter design for handling instruction flushes from a queue: A system and method for tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20070079107 - Integrated circuit with a plurality of communicating digital signal processors: A plurality of digital signal processors (10), each contains a signal processing core (22), a memory (20) coupled to the processing core (22) and a multiplexed data input (16) coupled to the memory (20). Each digital signal processor has a plurality of outputs for outputting data from the signal processing... Agent: Philips Intellectual Property & Standards

20070079108 - Active element machine computation: An active element machine is a new kind of computing machine. When implemented in hardware, the Active element machine can execute multiple instructions simultaneously, because every one of its computing elements is active. This greatly enhances the computing speed. By executing a meta program whose instructions change the connections in... Agent: David Lewis

20070079109 - Simulation apparatus and simulation method: A simulation apparatus capable of performing processing at a higher speed. The simulation apparatus is for VLIW processors, and includes a storage section for storing a program file which has a VLIW instruction formed of a predetermined instruction group, an instruction reading section for reading the program file from the... Agent: Staas & Halsey LLP

20070079110 - Instruction stream control: An interface operable to request instructions from a data store storing instructions of an application to be processed by a data processor, and operable to receive and transmit said instructions to said data processor, said interface comprising: an input operable to receive said instructions from said data store via at... Agent: Nixon & Vanderhye, PC