Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 03/07

20070073997 - Modem with power manager: A programmable modem (20) for processing a waveform includes a general purpose processor (GPP) engine (34) and special purpose programmable signal processing engines (22) in communication with the GPP engine (34). Each of the special purpose engines (22) executes a special purpose software program (80) to process a portion of... Agent: Meschkow & Gresham, P.L.C

20070073998 - Data processing system, method and interconnect fabric supporting high bandwidth communication between nodes: A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. Each... Agent: Dillon & Yudell LLP

20070073999 - Hardware acceleration system for logic simulation using shift register as local cache with path for bypassing shift register: A simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic operation, and a shift register for storing intermediate values generating during the logic simulation.... Agent: Fenwick & West LLP

20070074000 - Vliw acceleration system using multi-state logic: A logic simulation processor uses multi-state logic (e.g., in 4-state, signals may take the values 0, 1, X or Z in the simulation of a semiconductor chip design). Typically a reduced number of basic multi-state logic functions are selected for the instruction set of the processor. Logic functions that are... Agent: Fenwick & West LLP

20070074001 - Reconfigurable integrated circuit device: A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in... Agent: Arent Fox PLLC

20070074002 - Data packet arithmetic logic devices and methods: New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device... Agent: Intel/blakely

20070074003 - Method for reducing code size of program in code memory: A method of reducing a code size of a program by controlling a control flow of the program using software in a computer system is disclosed. The method includes the steps of storing a first program count of a first instruction in a first buffer when an error occurs while... Agent: Staas & Halsey LLP

20070074004 - Systems and methods for selectively decoupling a parallel extended instruction pipeline: Systems and methods for selectively decoupling a parallel extended processor pipeline. A main processor pipeline and parallel extended pipeline are coupled via an instruction queue. The main pipeline can instruct the parallel pipeline to execute instructions directly or to begin fetching and executing its own instructions autonomously. During autonomous operation... Agent: Hunton & Williams LLP Intellectual Property Department

20070074005 - Method and apparatus for issuing instructions from an issue queue in an information handling system: An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns... Agent: Mark P. Kahler

20070074006 - Method and apparatus for early load retirement in a processor system: A technique known as checkpointed early load retirement, combines register checkpointing load-value prediction to manage long-latency loads. When a long-latency load reaches the retirement stage unresolved, the processor enters Clear mode by (1) taking a Checkpoint of the architectural registers, (2) supplying a load-value prediction to consumers, and (3) early-retiring... Agent: Jones, Tullar & Cooper, P.C.

20070074007 - Parameterizable clip instruction and method of performing a clip operation using the same: A parameterizable clip instruction for SIMD microprocessor architecture and method of performing a clip operating the same. A single instruction is provided with three input operands: a destination address, a source address and a controlling parameter. The controlling parameter includes a range type and a range specifier. The range type... Agent: Hunton & Williams LLP Intellectual Property Department

20070074008 - Mixed mode floating-point pipeline with extended functions: An embodiment of the present invention is a technique to perform mixed mode floating-point (FP) operations and extended FP functions. A sequencer controls issuing an instruction operating on an input vector. A mixed mode FP pipeline computes an extended FP function or an integer operation of the input vector using... Agent: Blakely Sokoloff Taylor & Zafman

20070074009 - Scalable parallel pipeline floating-point unit for vector processing: An embodiment of the present invention is a technique to perform floating-point operations for vector processing. An input queue captures a plurality of vector inputs. A scheduler dispatches the vector inputs. A plurality of floating-point (FP) pipelines generates FP results from operating on scalar components of the vector inputs dispatched... Agent: Blakely Sokoloff Taylor & Zafman

20070074010 - Processor for processing instruction set of plurality of instructions packed into single code: A conversion table converts a packed instruction (pre-conversion code) contained in the instruction code fetched from an instruction memory into a plurality of instruction codes (converted codes). An instruction decoder decodes the plurality of the instruction codes converted by a conversion table. A plurality of ALUs perform the operation in... Agent: Buchanan, Ingersoll & Rooney PC

20070074011 - Reliable computing with a many-core processor: According to embodiments of the disclosed subject matter, cores in a many-core processor may be periodically tested to obtain and/or refresh their dynamic profiles. The dynamic profile of a core may include information on its maximum operating frequency, power consumption, power leakage, functional correctness, and other parameters, as well as... Agent: Blakely Sokoloff Taylor & Zafman

20070074012 - Systems and methods for recording instruction sequences in a microprocessor having a dynamically decoupleable extended instruction pipeline: Systems and methods for recording instruction sequences in a microprocessor having a dynamically decoupleable extended instruction pipeline. A record instruction including a record start address is sent to the extended pipeline. The extended pipeline thus begins recording the subsequent instruction sequence at the specified address until an end record instruction... Agent: Hunton & Williams LLP Intellectual Property Department

20070074013 - Dynamic retention of hardware register content in a computer system: A hardware register content retention system (100) includes a hardware register (110) configured to store register content and a memory (120) capable of storing multiple entries per register coupled to the hardware register, configured to receive a dump of the register content from the hardware register in response to initiation... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070074014 - Extended instruction set for packet processing applications: A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of... Agent: Huffman Law Group, P.C.

20070067605 - Architecture of a parallel-processing multi-microcontroller system and timing control method thereof: The present invention discloses the architecture of a parallel-processing multi-microcontroller system and a timing control method thereof. The multi-microcontroller system of the present invention comprises multiple microcontroller program execution status modules, and under an identical clock, different microcontroller program execution status modules respectively operate at separate clock timings, which is... Agent: Rosenberg, Klein & Lee

20070067606 - Heterogeneous parallel processing based on processor performance: In at least some embodiments, a system, comprises a first computing unit having a first type of processors. The system further comprises a second computing unit having a second type of processors, the second computing unit being coupled to the first computing unit. The first and second computing units are... Agent: Hewlett Packard Company

20070067607 - Selecting multiple threads for substantially concurrent processing: The present disclosure provides for processing units, which are capable of concurrently executing instructions, and a source arbitrator. The source arbitrator determines whether instructions for the processing units are read from different sources. If the source arbitrator determines that each processing unit reads its respective instruction from a different source,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070067608 - Method and apparatus for removing a pipeline bubble: One embodiment of the present invention provides a system that removes a bubble from a pipeline. During operation, the system first detects a stall in the pipeline. The system next determines whether a first register contains invalid data, which is associated with a bubble. Next, the system determines whether a... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070067609 - Method and apparatus for generating a precursor for a semiconductor processing system: Embodiments of the present invention are directed to an apparatus for generating a precursor for a semiconductor processing system (320). The apparatus includes a canister (300) having a sidewall (402), a top portion and a bottom portion. The canister (300) defines an interior volume (438) having an upper region (418)... Agent: Patterson & Sheridan, LLP

20070067610 - Methods and apparatuses for processing data channels: A system and method for processing an extremely high data rate datastream. Embodiments of the invention provide methods for performing various operations on the datastream in order to map the datastream from one protocol to another as well as providing methods for processing multiple channels of a given protocol. For... Agent: Thomas Van Zandt

20070067611 - Processor resource management: Embodiments include a device and a method. In an embodiment, a device provides a resource manager operable to select a resource management policy likely to provide a substantially optimum execution of an instruction group by comparing an execution of the instruction group pursuant to a first resource management policy applied... Agent: Searete LLC Clarence T. Tegreene

20070067612 - Arithmetic operation apparatus, information processing apparatus, and register file control method: The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in... Agent: Staas & Halsey LLP

20070061550 - Instruction execution in a processor: A processor comprising: a scalar processing unit for executing scalar instructions each defining a single value pair; a vector processing unit for executing vector instructions each defining multiple value pairs, the vector processing unit comprising a plurality of value processing units each operable to process one of said multiple value... Agent: Mcandrews Held & Malloy, Ltd

20070061551 - Computer processor architecture comprising operand stack and addressable registers: A computer processor architecture is disclosed that exhibits both the speed of register-oriented architectures in the prior art and the code efficiency of stack-oriented machines in the prior art. The illustrative embodiment accomplishes this by providing an operand stack and a stack-oriented instruction set but also a set of general... Agent: Demont & Breyer, LLC

20070061552 - Architecture of program address generation capable of executing wait and delay instructions: An architecture of program address generation capable of executing a WAIT instruction and a DELAY instruction feeds the program address to the input terminal of a multiplexer to add a WAIT instruction to a program for performing a wait operation. This WAIT instruction can also be controlled by adding a... Agent: Rosenberg, Klein & Lee

20070061553 - Byte execution unit for carrying out byte instructions in a processor: A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070061554 - Branch predictor for a processor and method of predicting a conditional branch: A branch predictor, a method of predicting a conditional branch and a digital signal processor incorporating the conditional branch predictor or the method. In one embodiment, the branch predictor includes: (1) static branch correction logic configured to employ a static branch prediction and a correction indicator associated with a particular... Agent: Lsi Logic Corporation

20070061555 - Call return tracking technique: Method, apparatus, and system for tracking call returns. At least one embodiment maps the locations of a return instruction pointer within a speculative return stack buffer and a committed return stack buffer to determine a return stack buffers from which the return instruction pointer should be retrieved.... Agent: Blakely Sokoloff Taylor & Zafman

20070055845 - Self-reparable semiconductor and method thereof: A self-reparable semiconductor comprises first and second physical layer devices each including first and second subfunctional units that cooperate to provide first and second ports associated with a multi-bit Gigabit physical layer device. A first spare physical layer device includes first and second subfunctional units. The first sub-functional units are... Agent: Harness, Dickey & Pierce P.L.C

20070055847 - Operational processor with a status information register serving as a data register: The operational processor includes a general-purpose register that holds data associated with operation processing, and a program status register that holds information associated with the status of the operational processor. The data and information are saved during interrupt processing or task switching. The program status register holds in its bit... Agent: Nixon Peabody, LLP

20070055848 - Processor resource management: Embodiments include a device and a method. In an embodiment, a device provides a resource manager operable to select a resource management policy likely to provide a substantially optimum execution of an instruction group by comparing an execution of the instruction group pursuant to a first resource management policy applied... Agent: Searete Llc Clarence T. Tegreene

20070055846 - System and method for performing deterministic processing: A system and method is provided for performing deterministic processing on a non-deterministic computer system. In one example, the system forces execution of one or more computer instructions to execute within a constant execution time. A deterministic engine, if necessary, waits a variable amount of time to ensure that the... Agent: Lowrie, Lando & Anastasi

20070055850 - Generating instruction sets for compacting long instructions: A method of generating at least one instruction set from a plurality of program instructions, said plurality of program instructions comprising a plurality of instruction fields each of said instruction fields operable on decoding to generate control signals for transmission by individual command buses, said method comprising the steps of:... Agent: Nixon & Vanderhye, Pc

20070055849 - Method and system for processing an instruction set: The present invention provides a method and system for processing an instruction set, which can be applied to compress the operation part of a sequence of instructions in the instruction set and to perform the corresponding decompression. Upon the compression, the sequence of instructions is divided into a operation part... Agent: Schmeiser, Olsen & Watts

20070055852 - Processing operation management systems and methods: Methods and systems of managing processing operations are disclosed. Processing operations are not restricted to being executed by any particular processor of a multi-processor system. Information associated with a processing operation may be transferred to one processor for use by the processor in executing the processing operation. The processor may... Agent: Eckert Seamans Cherin & Mellott, Llc.

20070055851 - Zero overhead branching and looping in time stationary processors: Programmable processors are used to transform input data into output data based on program information encoded in instructions. The value of the resulting output data depends, amongst others, on the momentary state of the processor at any given moment in time. This state is composed of temporary data values stored... Agent: Philips Intellectual Property & Standards

20070050597 - Game controller and game system: A first control unit includes a first operation data generation section for generating first operation data in accordance with a motion of a first control unit body included in the first control unit. A second control unit includes a second operation data generation section for generating second operation data in... Agent: Nixon & Vanderhye, P.C.

20070050598 - Transferring data from integer to vector registers: A method for transferring data from a general purpose register to a vector register, the method including splatting a byte of data directly from a general purpose register (GPR) to a vector register (VR) by means of vector permute instructions, and splatting another byte of data from the GPR to... Agent: Ibm Corporation, T.j. Watson Research Center

20070050599 - Determining the placement of semiconductor components on an integrated circuit: Systems and methods are disclosed herein for determining the placement of a standard cell, representing a semiconductor component in a design stage, on an integrated circuit die. One embodiment of a method, among others, comprises analyzing regions of a semiconductor die with respect to the susceptibility of the region to... Agent: Avago Technologies, Ltd.

20070050601 - Avoiding live-lock in a processor that supports speculative execution: One embodiment of the present invention provides a system which avoids a live-lock state in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during the execution of an... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070050600 - Preventing loss of traced information in a data processing apparatus: Techniques for preventing the loss of trace information being transmitted via trace infrastructure are disclosed. A data processing apparatus for processing instructions is provided. The data processing apparatus comprises: decode/issue logic operable to receive and decode an instruction to be processed by the data processing apparatus and to determine when... Agent: Nixon & Vanderhye, PC

20070050602 - Partially decoded register renamer: In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource. Coupled to receive an input representing one... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070050603 - Data processing method and device: In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements,... Agent: Kenyon & Kenyon LLP

20070050604 - Fetch rerouting in response to an execution-based optimization profile: Embodiments include a device, and a method. In an embodiment, a device includes a processor operable to execute an instruction set, and an execution-optimization circuit. The execution circuit includes an execution circuit for receiving an identification of a first instruction to be fetched from the instruction set for execution by... Agent: Searete LLC Clarence T. Tegreene

20070050605 - Freeze-dried ghost pages: Embodiments include a device, apparatus, and a method. In an embodiment, an apparatus includes a first processor operable to execute a program. The apparatus also includes an information store configured by an execution-based optimization profile, the execution-based optimization profile usable in an execution of the program and that was created... Agent: Searete LLC Clarence T. Tegreene

20070050607 - Alteration of execution of a program in response to an execution-optimization information: Embodiments include a device, and a method. In an embodiment, a device includes an information store operable to save an execution-optimization information, a first processor, and a hardware circuit. The hardware circuit includes a hardware circuit for altering an execution of a program by the first processor in response to... Agent: Searete LLC

20070050609 - Cross-architecture execution optimization: Embodiments include a device, apparatus, and a method. A device includes an input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first architecture. The device also includes a generator circuit for creating an execution-based optimization profile useable in an... Agent: Searete LLC Clarence T. Tegreene

20070050608 - Hardware-generated and historically-based execution optimization: Embodiments include a device, and a method. In an embodiment, a device includes a processor operable to execute an instruction set, a communications link exposed to an execution-optimization synthesizer and to the processor, and the execution-optimization synthesizer. The execution-optimization optimization synthesizer includes an execution-optimization synthesizer operable to collect data from... Agent: Searete LLC Clarence T. Tegreene

20070050606 - Runtime-based optimization profile: Embodiments include a device, and a method. In an embodiment, a device includes a microengine operatively coupled with a processor having an instruction set. The microengine includes a microengine operable gather data in a manner transparent to software executing on the processor and corresponding to a runtime execution of at... Agent: Searete LLC Clarence T. Tegreene

20070050610 - Centralized resolution of conditional instructions: A processor that includes a memory comprising a condition code register (CCR) and a plurality of execution units coupled to the memory. Each execution unit comprises multiple stages and is provided with a different instruction predicated on a conditional statement. The conditional statement of each different instruction also is provided... Agent: Texas Instruments Incorporated