Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 02/07

20070043930 - Performance of a data processing apparatus: Techniques for improving the performance of a data processing apparatus are disclosed. A data processing apparatus operable to process instructions and operable to determine, prior to each instruction being issued for execution, when resources associated with that instruction are predicted to be available for use by succeeding instructions is provided.... Agent: Nixon & Vanderhye, PC

20070043931 - System and method for high frequency stall design: A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20070043932 - Wakeup mechanisms for schedulers: Methods and apparatus to provide wakeup mechanisms for schedulers are described. In one embodiment, a scheduler broadcasts a uop scheduler identifier of a scheduled uop (or micro-operation) to one or more uops awaiting scheduling. The scheduler may further update one or more corresponding entries in a uop dependency matrix or... Agent: Caven & Aghevli C/o Intellevate

20070043933 - Instruction set architecture employing conditional multistore synchronization: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the... Agent: Robert C. Kowert Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070043934 - Early misprediction recovery through periodic checkpoints: Methods and apparatus to provide misprediction recovery through periodic checkpoint are described. In one embodiment, a renamer unit (e.g., within a processor core) recovers a register alias table (RAT) to a state immediately preceding a misprediction.... Agent: Caven & Aghevli C/o Intellevate

20070043935 - Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts: A multiprocessing system is disclosed. The system includes a multithreading microprocessor including a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a shared privileged resource, shared by the plurality of TCs rather than being... Agent: Huffman Law Group, P.C.

20070043936 - System and method for communicating with a processor event facility: A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070038842 - Data recording processor and method for use in an active memory device: An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070038843 - System and method for application acceleration using heterogeneous processors: An accelerated processing system includes one or more conventional processors, one or more coprocessors, and high speed data links between the processors, coprocessors and memory. In an embodiment, an application program is compiled and linked to a library of macros, the macros are invoked at run time by the application... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070038845 - Data processor: A data processor having: an instruction fetch unit for acquiring an instruction; and an instruction execution unit for execution, by pipeline processing, the instruction acquired by the instruction fetch unit. In the data processor, the instruction execution unit includes an execution pipeline pipelined into two or more stages for execution... Agent: Miles & Stockbridge PC

20070038844 - Technique to combine instructions: A micro-operation (uop) fusion technique. More particularly, embodiments of the invention relate to a technique to fuse two or more uops originating from two or more instructions.... Agent: Blakely Sokoloff Taylor & Zafman

20070038848 - Implementing instruction set architectures with non-contiguous register file specifiers: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous... Agent: Keusey, Tutunjian & Bitetto, P.C.

20070038847 - Misalignment predictor: In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070038846 - Partial load/store forward prediction: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070038849 - Computing system and method: A computing system comprising: a first processor set for executing a first instance of software; a second processor set; and a delay unit that causes said second processor set to execute a second instance of said software at a predetermined delay to said first processor set, whereby a software error... Agent: Hewlett Packard Company

20070033379 - Active memory processing array topography and method: An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying instructions to the processing elements. The processing elements are logically arranged in a plurality of logical rows and logical columns. The array is logically folded to... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070033380 - Method and device for securing an integrated circuit, in particular a microprocessor card: A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the processing circuits. The method comprises, between the processing cycles, a step of modifying the rule for allocating electrical signals to the processing circuits,... Agent: Seed Intellectual Property Law Group PLLC

20070033381 - Conditional execution with multiple destination stores: A method for conditionally performing a SIMD operation causing a predetermined number of result objects to be held in a combination of different ones of a plurality of destination stores, the method comprising receiving and decoding instruction fields to determine at least one source store, a plurality of destination stores... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070033382 - Dynamic configuration of terminals for professional or customer usage: A method of dynamically configuring a terminal within a business establishment can include comparing context information relating to terminal usage within the business establishment with context definitions specifying at least one of time-based rules or terminal usage patterns and selecting a profile according to the comparing step. The profile can... Agent: Cuenot & Forsythe, L.L.C.

20070033383 - Multiple instruction set decoding: A method and a data processing apparatus operable to process instructions from a plurality of instruction sets, the plurality of instruction sets each sharing a sub-set of common instructions and each having a remaining set of instructions is disclosed. The data processing apparatus comprises: a plurality of decode units, each... Agent: Nixon & Vanderhye, PC

20070033384 - Real-time embedded simple monitor method and computer product: A processor context stored in a stack area at a time of an interrupt occurrence is saved in a context saving area of an ICB corresponding to an ISR that is interrupted. The ISR corresponding to the interrupt is set to an execution-waiting state. An ICB having a highest priority... Agent: Buchanan, Ingersoll & Rooney PC

20070033385 - Call return stack way prediction repair: A mechanism for repairing way mispredictions in a cache. An instruction cache in a processor is coupled to receive a fetch address and a corresponding way prediction. A return address stack is configured to store a return address corresponding to a fetched branch instruction, a return address way prediction, and... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20070028076 - Algebraic single instruction multiple data processing: A data processing apparatus comprises data processing logic operable to perform data processing operations specified by program instructions. The data processing logic (140) has a plurality of functional units (142, 144, 146) configured to execute in parallel on data received from a data source. A decoder (130) is responsive to... Agent: Nixon & Vanderhye, PC

20070028077 - Pipeline processor, and method for automatically designing a pipeline processor: A pipeline processor including an instruction decode unit configured to decode fetched instruction, and to selectively issue one of a user customizable instruction defined by a user and a core instruction. A core instruction execution unit is configured to execute the issued core instruction. A user customizable instruction unit is... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070028078 - Instruction queues in pipelined processors: A data processing apparatus comprising: a pipelined processor comprising an execution pipeline operable to execute instructions in a plurality of execution stages; a fetch unit for fetching instructions from a memory prior to sending those instructions to said execution pipeline; an instruction decoder operable to decode said fetched instructions; instruction... Agent: Nixon & Vanderhye, PC

20070028079 - Method for conditionally branching a validation: Conditionally branching a validation allows branch-specific child validations to execute based on the values of data in a specific record. This allows for example a conditional branch to call another validation to validate records having particular category field values, family values and/or audience level/name/values. Embodiments comprise an interface that assists... Agent: Dalina Law Group, P.C.