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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) January USPTO class patent listing 01/07

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
01/25/2007 > 10 patent applications in 10 patent subcategories. USPTO class patent listing

20070022271 - Processor with changeable correspondences between opcodes and instructions: A processor includes an instruction buffer operable to store an opcode, an instruction decoder configured to keep one-to-one correspondences between opcodes and instructions, to identify an instruction corresponding to the opcode received from the instruction buffer based on the correspondences, and to output a signal indicative of the identified instruction,... Agent: Arent Fox PLLC

20070022272 - Microprocessor: The present invention includes a pipeline having a plurality of stages, and a resource management unit configured to be connected to the pipeline and manage circuit resources for processing instructions. An instruction fetch unit is configured to issue processing commands to the pipeline, receive a busy signal BS from the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070022273 - Error recovery systems and methods for execution data paths: Systems and methods for error recovery in an integer execution unit of a multi-core processor are disclosed. In an exemplary embodiment a method may comprise checking parity for a transaction in an execution data path having parallel data registers. The method may also comprise copying one of the parallel data... Agent: Hewlett Packard Company

20070022274 - Apparatus, system, and method of predicting and correcting critical paths: Embodiments of the invention provide a method that includes partitioning a series of instructions of a trace into a plurality of dependency sets before executing the trace; and marking a first group of the dependency sets as critical and a second group of the dependency sets as non-critical Embodiments of... Agent: Pearl Cohen Zedek Latzer, LLP

20070022275 - Processor cluster implementing conditional instruction skip: A system and method include identifying a conditional skip instruction, determining when a conditional skip instruction is satisfied according to a result of an associated compare function, and skipping a fixed-number of the instructions defined by the conditional skip instruction when the conditional skip function is satisfied.... Agent: Marger Johnson & Mccollom, P.C.

20070022276 - Method and system for processing a work item in a pipelined sequence: The present invention relates to the processing of information in a computer with multiple stages wherein in each stage a particular, stage-specific work is done with or without stage-specific data. The present invention in particular adheres to the tracing of events which happen in each of these stages. In order... Agent: International Business Machines Corporation

20070022277 - Method and system for an enhanced microprocessor: Systems and methods for modes of operation for processing data are disclosed. While executing a program in one mode the hazard checking logic present in the microprocessor system may be utilized to check or ameliorate the hazards caused by the execution of this program. However, when a program does not... Agent: SprinkleIPLaw Group

20070022278 - Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines: A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20070022279 - Compressing and accessing a microcode rom: An arrangement is provided for compressing microcode ROM (“uROM”) in a processor and for efficiently accessing a compressed “uROM”. A clustering-based approach may be used to effectively compress a uROM. The approach groups similar columns of microcode into different clusters and identifies unique patterns within each cluster. Only unique patterns... Agent: Blakely Sokoloff Taylor & Zafman

20070022280 - Copying of unaligned data in a pipelined operation: Methods, computer readable media and computing devices including program instructions are provided for copying unaligned data. One method embodiment includes using 12 execution units to move 16 bytes of data from an unaligned data area to an aligned data area during each iteration of a loop in a pipelined operation,... Agent: Hewlett Packard Company

  
01/18/2007 > 4 patent applications in 4 patent subcategories. USPTO class patent listing

20070016757 - Control of priority and instruction rates on a multithreaded processor: A method and apparatus for controlling issue rate of instructions for an instruction thread to be executed by a processor is provided. The rate at which instructions are to be executed for an instruction thread are stored and requests are issued to cause instructions to execute in response to the... Agent: Flynn Thiel Boutell & Tanis, P.C.

20070016758 - Local and global register partitioning technique: A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the plurality of functional units. The register file segments are... Agent: Sun Microsystems, Inc. Attn: Timothy Schulte

20070016759 - System and method of controlling multiple program threads within a multithreaded processor: A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program... Agent: Qualcomm Incorporated

20070016760 - Central processing unit architecture with enhanced branch prediction: A central processing unit (CPU) architecture with enhanced branch prediction, being substantially a pipelined CPU with multiple pipelines, each pipeline having a plurality of stages, by which all instructions relating directly to a branch instruction of a code executed by the pipelined CPU are being fetched respectively by each corresponding... Agent: Bruce H. Troxell

  
01/11/2007 > 4 patent applications in 4 patent subcategories. USPTO class patent listing

20070011433 - Method and device for data processing: The invention relates to a data processing device with a data processing logic cell field and at least one sequential CPU, wherein a coupling of the sequential CPU to the data processing logic cell field, for data exchange, particularly in block form, by means of lines leading to a cache... Agent: Kenyon & Kenyon LLP

20070011434 - Multiple parallel pipeline processor having self-repairing capability: A multiple parallel pipeline digital processing apparatus has the capability to substitute a second pipeline for a first in the event that a failure is detected in the first pipeline. Preferably, a redundant pipeline is shared by multiple primary pipelines. Preferably, the pipelines are located physically adjacent one another in... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070011435 - Mesh node association method in a mesh network, and mesh network supporting the same: A mesh network has a plurality of mesh nodes, including a moving mesh node. A serving mesh node initially associates with the moving mesh node at the request of the moving mesh node, transmits context information due to the initial association to at least one neighbor mesh node, and transmits... Agent: Dilworth & Barrese, LLP

20070011436 - Content addressable memory architecture: A content addressable memory (CAM) architecture comprises two components, a small, fast on-chip cache memory that stores data that is likely needed in the immediate future, and an off-chip main memory in normal RAM. The CAM allows data to be stored with an associated tag that is of any size... Agent: Workman Nydegger/microsoft

20070011437 - System and method for pipelet processing of data sets: The present invention is directed towards systems and methods for decomposing a complex problem or task into one or more constituent components, operating in parallel over a plurality of computing devices in communication over a network. A system according to the present invention comprises one or more pipelets. A given... Agent: Brown, Raysman, Millstein, Felder & Steiner LLP

20070011439 - Data processing systems and methods of operating the same in which memory blocks are selectively activated in fetching program instructions: A processing unit includes an instruction fetch unit that is configured to process an instruction that includes a plurality of fields. The plurality of fields includes a flag field that identifies at least one of a plurality of memory blocks to be activated for fetching a next instruction.... Agent: Myers Bigel Sibley & Sajovec

20070011438 - Microprocessor: The microprocessor is simply structured, shortening the time for design and verification, and protecting tasks while executing multiple tasks The microprocessor includes an instruction fetch unit having a request queue configured to issue, to a bus interface unit, a bus request due to an instruction fetch and retain, of instruction... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070011440 - Processor and processing method: A processor for performing processing based on an instruction code stored in an instruction memory. In the instruction code, a plurality of operations corresponding to a common calculation pattern are represented by a common instruction set designating logical registers. A register-assignment control unit includes a plurality of register-map tables, and... Agent: Arent Fox PLLC

20070011441 - Method and system for data-driven runtime alignment operation: A method for processing instructions and data in a processor includes steps of: preparing an input stream of data for processing in a data path in response to a first set of instructions specifying a dynamic parameter; and processing the input stream of data in the same data path in... Agent: Michael J. Buchenhorner

20070011442 - Systems and methods of providing indexed load and store operations in a dual-mode computer processing environment: The methods, systems, and apparatus improve performance in a computer system by providing indexed load/store instructions for processor operations having indexed or indirect operations in a processing environment that supports both horizontal mode and vertical mode processing.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

  
01/04/2007 > 4 patent applications in 4 patent subcategories. USPTO class patent listing
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Next industry: Electrical computers and digital processing systems: support


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