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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) December patent applications/inventions, industry category 12/06

20060294342 - Method of renaming registers in register file and microprocessor thereof: A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions, multiple register sub-files each having multiple registers for storing data for executing the instructions, wherein each of the clusters is associated with corresponding one... Agent: F. Chau & Associates, LLC

20060294343 - Realtime compression of microprocessor execution history: A trace compression unit is included in a processor system that has a processor core and an external system memory. The trace compression unit encrypts the processor core execution history into compressed trace record that is stored in external memory using one or more control to define a storage location... Agent: Garlick Harrison & Markison

20060294344 - Computer processor pipeline with shadow registers for context switching, and method: A computer processor pipeline comprises a register file and a plurality of pipe stages connected to the register file. Each pipe stage comprises a working register and a shadow register. The working registers of the plurality of pipe stages are connected together to form a working pipe. The shadow registers... Agent: Elliot Furman

20060294345 - Methods and apparatus for implementing branching instructions within a processor: A processor is described that includes a plurality of registers configured as a status stack. The processor is configured to sequentially store results from status producing instruction executions in the status stack and implement a branching instruction based on at least one of the stored results.... Agent: Dean D. Small Armstrong Teasdale LLP

20060294346 - Method and apparatus for managing a link return stack: In one or more embodiments, a processor includes a link return stack circuit used for storing branch return addresses, wherein a link return stack controller is configured to determine that one or more entries in the link return stack are invalid as being dependent on a mispredicted branch, and to... Agent: Qualcomm Incorporated

20060294348 - Multi-processor system: In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP) provided with an operating system (OS), a slave processor (SP), an interrupt controller (INTC), and an interrupt among processors control register (IPCR) are connected... Agent: Miles & Stockbridge PC

20060294347 - Programmable event driven yield mechanism which may activate service threads: Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the... Agent: Blakely Sokoloff Taylor & Zafman

20060288190 - Apparatus and method for switching threads in multi-threading processors: A multi-threaded processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the first instruction fetch unit and the second instruction fetch unit. An execution unit, which executes a first active thread and a second... Agent: Intel Corporation

20060288191 - System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor... Agent: F. Chau & Associates, LLC

20060288192 - Fine grained multi-thread dispatch block mechanism: The present invention provides a method, a computer program product, and an apparatus for blocking a thread at dispatch in a multi-thread processor for fine-grained control of thread performance. Multiple threads share a pipeline within a processor. Therefore, a long latency condition for an instruction on one thread can stall... Agent: Ibm Corporation (cs) C/o Carr LLP

20060288193 - Register-collecting mechanism for multi-threaded processors and method using the same: A register-collecting mechanism and method using the same for multi-threaded processors are described. The register-collecting mechanism includes an instruction scanner, a register mapping table, an instruction modifier and an indication reporter. The instruction scanner scans one or more first programs having a plurality of first instructions and decode each of... Agent: Troxell Law Office PLLC

20060288194 - Real-time processor: A real-time processor for a data processing system includes a continuous clock counter, an instruction parser parsing instructions based upon whether they a clock command or no timing specific instruction, a clock comparator only operating upon instructions including a clock command and an execution mechanism for executing a series of... Agent: Welsh & Flaxman LLC

20060288195 - Apparatus and method for switchable conditional execution in a vliw processor: An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoders loads and decodes said instructions from a fetch unit for decoding and sending the decoded instructions to the ALU with... Agent: Lin & Associates Intellectual Property

20060288196 - System and method for exploiting timing variability in a processor pipeline: A processor including a pipeline for processing a plurality of instructions is disclosed. The pipeline comprises a plurality of stages. Each stage comprises a processing logic, and a control logic. The processing logic processes an input to produce an output. The control logic receives the output of the processing logic,... Agent: Blakely Sokoloff Taylor & Zafman

20060282646 - Software selectable adjustment of simd parallelism: Selective power control of one or more processing elements matches a degree of parallelism to requirements of a task performed in a highly parallel programmable data processor. For example, when program operations require less than the full width of the data path, a software instruction of the program sets a... Agent: Qualcomm Incorporated

20060282647 - Parallel processing system: The invention is based on the idea to provide a functional unit that is capable of performing not only a simple pass operation but also delayed pass operations, introducing a desired amount of latency. Therefore, a parallel processor is provided, wherein said processor comprises a control means CTR for controlling... Agent: Philips Intellectual Property & Standards

20060282648 - Network topology for a scalable multiprocessor system: A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060282649 - Device pairing via voice commands: A system comprising includes a first device, a second device, and logic to enable the first and second devices to pair as a result of at least one sound.... Agent: Fsp LLC

20060282650 - Efficient clip-testing: A method and apparatus for performing fast clip-testing operations in a general purpose processor are provided. This is accomplished by executing a single instruction for comparing a first value x to a second value y and, as a result of the comparison, determining whether x is less than y and... Agent: Zagorin O'brien Graham LLP (004)

20060277392 - Conditional execution via content addressable memory and parallel computing execution model: The use of a configuration-based execution model in conjunction with a content addressable memory (CAM) architecture provides a mechanism that enables performance of a number of computing concepts, including conditional execution, (e.g., If-Then statements and while loops), function calls and recursion. If-then and while loops are implemented by using a...

20060277391 - Execution model for parallel computing: A dataflow graph is split into sub-graphs referred to as configurations, each configuration comprising computational hardware containing elements that operate on operand sets. A configuration executes by consuming completed operand sets from a designated input tag space (e.g., in a content addressable memory) until the operand sets are exhausted. At...

20060277393 - Multi-image-source document camera: A document camera is used to show image picked up from an object and/or image received from an external apparatus such as a computer on an image display. In the document camera, an image sensing and processing device senses image of an object and processing the image into an image...

20060277394 - Computing system and method of enabling a digital signal processor to access parameter tables through a central processing unit: A computing system includes a digital signal processor, a storage medium for storing parameter tables, a central processing unit coupled to the digital signal processor and the storage medium, and a shared memory coupled to the digital signal processor and the central processing unit. The digital signal processor stores a...

20060277395 - Processor performance monitoring: Systems, methods, and device are provided for monitoring a processor. One method embodiment includes selectively combining micro-architectural events into various groups of micro-architectural events. The method includes multiplexing the various groups of micro-architectural events to a performance monitoring unit (PMU) associated with the processor....

20060277396 - Memory operations in microprocessors with multiple execution modes and register files: An apparatus and method for saving and operating on a register set, shadow register file, and memory is presented. A register within a register set that is associated with an active execution state in a computing system is used as an address pointer to a memory location. The content of...

20060277397 - Method and apparatus for predicting branch instructions: A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses...

20060277398 - Method and apparatus for instruction latency tolerant execution in an out-of-order pipeline: A method and apparatus for setting aside a long-latency micro-operation from a reorder buffer is disclosed. In one embodiment, a long-latency micro-operation would conventionally stall a reorder buffer. Therefore a secondary buffer may be used to temporarily store that long-latency micro-operation, and other micro-operations depending from it, until that long-latency...

20060277399 - Semiconductor device and data processing system: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel...