Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 10/06

20060242384 - Register files for a digital signal processor operating in an interleaved multi-threaded environment: A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of...

20060242385 - Dynamically reconfigurable processor: Disclosed is a technology of generating an instruction set architecture (hereinafter, referred to as ‘ISA’) and a series of logic circuit configuration information of a processor for executing an application program from an application program described in a high-level language. The present invention also relates to a custom LSI development...

20060242386 - Asynchronous processor: Systems and methods for executing program instructions in a data processor at a variable rate. In one embodiment, a processor is configured to examine received instructions, identify an execution time associated with each instruction, and generate clock pulses at necessary intervals to obtain the appropriate execution time for each instruction....

20060242387 - Processor, compiler and compilation method: In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing...

20060242388 - Processor with register dirty bit tracking for efficient context switch: A processor including a large register file utilizes a dirty bit storage coupled to the register file and a dirty bit logic that controls resetting of the dirty bit storage. The dirty bit logic determines whether a register or group of registers in the register file has been written since...

20060242389 - Job level control of simultaneous multi-threading functionality in a processor: Using resource sets for job-level control of the simultaneous multi-threading capability (SMT) of a processor in a data processing system. A resource set defined with respect to the processor is adapted to control whether the simultaneous multi-threading capability is enabled....

20060242390 - Advanced load address table buffer: Methods and apparatus to store information corresponding to a data speculative instruction are described. In one embodiment, an apparatus includes an advanced load address table (ALAT) buffer to store the information corresponding to the data speculative instruction....

20060242391 - Context switching within a data processing system having a branch prediction mechanism: A branch target buffer 10 is provided which maintains its entries across context switches within a virtually addressed system. Branch mispredictions are detected for individual entries 12 within the branch target buffer 10 and those individual entries are invalidated....

20060242393 - Branch target prediction for multi-target branches: An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of target addresses representing a history of target addresses for a multi-target branch and logic for reading the memory and identifying a repeated pattern...

20060242392 - Reading prediction outcomes within a branch prediction mechanism: A branch prediction mechanism 2 includes a history value register 4 storing a history value which is used to address into a history buffer 6 from which a plurality of prediction values are read and stored into a prediction value store 8. The one or more prediction values to be...

20060242394 - Processor and processor instruction buffer operating method: A processor includes an instruction fetch unit providing a fetch address to the memory system; a branch buffer, a normal buffer, and a general buffer, which receive fetch instructions, respectively; a to-be-issued instruction selecting unit, which selects an instruction from the normal buffer, the branch buffer, and the general buffer...

20060236075 - Simd microprocessor and data processing method: A SIMD microprocessor including m processor elements, m being a natural number that is no less than 2 is disclosed. The SIMD microprocessor includes an arithmetic part included in each processor element for processing a maximum of n data items in a single time by using n arithmetic circuits, n...

20060236076 - Method and apparatus for packing data: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed...

20060236077 - Microprocessor access of operand stack as a register file using native instructions: A combined native (RISC or CISC) microprocessor and stack (Java) machine are constructed so that Java VM instructions can be executed in hardware. Most Java instructions are executed directly, while more complex Java instructions, such as those manipulating Java objects, are executed as native microcode. In order for native microcode...

20060236078 - System and method wherein conditional instructions unconditionally provide output: A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides...

20060236079 - Unified single-core and multi-mode processor and its program execution method: A unified single-core and multi-mode processor and its program execution method are provided. In an embodiment of this processor, a single instruction stream is different types of instructions randomly arranged in thereof. The processor switches its modes based on the type of a fetched instruction to execute the program corresponding...

20060236080 - Reducing the fetch time of target instructions of a predicted taken branch instruction: A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of...

20060230253 - Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment: A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit...

20060230254 - Systems and methods for cpu repair: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty...

20060230255 - Systems and methods for cpu repair: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty...

20060230256 - Credit-based activity regulation within a microprocessor: A technique to control power consumption within a microprocessor. More particularly, embodiments of the invention relate to a technique to control power and performance within one or more microprocessors by enforcing a credit-based instruction execution rate algorithm....

20060230257 - System and method of using a predicate value to access a register file: A processor device is disclosed and includes a memory unit and at least one interleaved multi-threading instruction pipeline. The interleaved multi-threading instruction pipeline utilizes a number of clock cycles that is less than an instruction issue rate for each of a plurality of program threads that are stored within the...

20060230258 - Multi-thread processor and method for operating such a processor: A multithread processor with synchronization of a command flow, with an associated data flow and with generation of a memory-triggered context switch signal comprises a synchronization device configured, when receiving a load cycle indicator flag with a positive logic signal level from a memory read access unit, to load and...

20060230259 - Instruction memory unit and method of operation: An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of...

20060224859 - Microcomputer: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values...

20060224860 - Apparatus and method for supporting execution of prefetch threads: A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use in the immediate future. Data is...

20060224861 - Condition branch instruction encoding within a multiple instruction set data processing system: A data processing system is operable in a first state to use a first instruction set having a first instruction set encoding. The data processing system is also operable in a second state to use a second instruction set having a second instruction encoding. Conditional branch instructions provided within the...

20060224862 - Mixed superscalar and vliw instruction issuing and processing method and system: Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality...

20060224863 - Preparing instruction groups for a processor having multiple issue ports: Disclosed is a mechanism of preparing an instruction group 606 using a plurality of pools 700 having a hierarchical structure 711-715. Each pool represents a different overlapping subset of the issue ports 610. Placing an instruction 600 into a particular pool 700 also reduces vacancies in any one or more...

20060224864 - System and method for handling multi-cycle non-pipelined instruction sequencing: A system and method for handling multi-cycle non-pipelined instruction sequencing. With the system and method, when a non-pipelined instruction is detected at an issue point, the issue logic initiates a stall that is for a minimum number of cycles that the fastest non-pipelined instruction could complete. The execution unit then...

20060224865 - Vector processing system: A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation...

20060224867 - Avoiding unnecessary processing of predicated instructions: A processor comprising an instruction cache module adapted to store a plurality of instructions, the plurality of instructions comprising a group of instructions predicated on a conditional statement. The processor also comprises a branch prediction module coupled to the instruction cache module and adapted to predict an outcome of the...

20060224866 - Selecting subroutine return mechanisms: Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect a match and the return instruction response is selected in dependence upon whether or not a match is detected....

20060224868 - Branch tracing generator device for a microprocessor and microprocessor equipped with such a device: A device for generating an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of the expanded type, said device including: means for receiving a first signal representative of...

20060224869 - Combination of forwarding/bypass network with history file: An apparatus, a method, and a processor are provided for recovering the correct state of processor instructions in a processor. This apparatus contains a pipeline of latches, a register file, and a replay loop. The replay loop repairs incorrect results and inserts the repaired results back into the pipeline. A...

20060224870 - Information processing device: The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of...

20060224872 - System for speculative branch prediction optimization and method thereof: A value representative of a processor's speculative branch prediction efficiency is determined and the speculative branch prediction depth is adjusted accordingly. The processor's speculative branch prediction efficiency may be represented by the average number of clocks per instruction (CPI), whereby an increase in the average CPI indicates that the processor...

20060224871 - Wide branch target buffer: A system comprising a pipeline in which a first plurality of instructions are processed, and a branch prediction module coupled to the pipeline, where the branch prediction module is adapted to predict the outcomes of at least some branch instructions in the first plurality of instructions and in a second...

20060224873 - Acquiring instruction addresses associated with performance monitoring events: Systems, methodologies, media, and other embodiments associated with acquiring instruction addresses associated with performance monitoring events are described. One exemplary system embodiment includes logic for recording instruction and state data associated with events countable by performance monitoring logic associated with a pipelined processor. The exemplary system embodiment may also include...