Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 09/06

20060212677 - Multicore processor having active and inactive execution cores: Embodiments of a multicore processor having active and inactive execution cores are disclosed. In one embodiment, an apparatus includes a processor having a plurality of execution cores on a single integrated circuit, and a plurality of core identification registers. Each of the plurality of core identification registers corresponds to one...

20060212678 - Reconfigurable processor array exploiting ilp and tlp: A processing system according to the invention comprises a plurality of processing elements, and the plurality of processing elements comprises a first set of processing elements and at least a second set of processing elements. Each processing element of the first set comprises a register file and at least one...

20060212679 - Field programmable mixed-signal integrated circuit: Field programmable mixed-signal integrated circuit. A reconfigurable processor system includes a processor core is provided that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output...

20060212680 - Methods and apparatus for dynamic prediction by software: A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine...

20060212681 - Processor and method of grouping and executing dependent instructions in a packet: An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for...

20060212682 - Processor utilizing novel architectural ordering scheme: Various methods, apparatuses, and systems in which a processor includes an issue engine and an in-order execution pipeline. The issue engine categorizes operations as at least one of either a speculative operation which perform computations or an architectural operation which has potential to fault or cause an exception. Each architectural...

20060212683 - Information processing system, pipeline processor, and computer readable recording medium in which busy judgment program is stored: In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register provided at the final stage of a pipeline register in a stage in which the request is...

20060212684 - Circuit for monitoring a microprocessor and analysis tool and inputs/outputs thereof: The invention relates to a method for the transmission of digital messages by means of the output terminals (22) of a monitoring circuit (18) which is integrated into a microprocessor (12), said digital messages being representative of first specific events which are dependent on the execution of a series of...

20060212685 - Ultra low power asip architecture: A microcomputer architecture comprises a microprocessor unit and a first memory unit, the microprocessor unit comprising a functional unit and at least one data register, the functional unit and the at least one data register being linked to a data bus internal to the microprocessor unit. The data register is...

20060212686 - Pipelined instruction processor with data bypassing: An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline...

20060212687 - Dual thread processor: A pipeline processor architecture, processor, and methods are provided. In one implementation, a processor is provided that includes an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, a decoder responsive to the instruction fetch unit, issue logic responsive to the decoder, and a register...

20060212688 - Generation of multiple checkpoints in a processor that supports speculative execution: One embodiment of the present invention provides a system which creates multiple checkpoints in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during an instruction which causes a...

20060212689 - Method and apparatus for simultaneous speculative threading: One embodiment of the present invention provides a system which performs simultaneous speculative threading. The system starts by executing instructions in normal execution mode using a first thread. Upon encountering a data-dependent stall condition, the first thread generates an architectural checkpoint and commences execution of instructions in execute-ahead mode. During...

20060212690 - System and method for processing complex computer instructions: A system and method for handling complex instructions are provided. The process includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting the original instruction if it was not complex or the jump instruction if it was....

20060206688 - Power saving methods and apparatus to selectively enable comparators in a cam renaming register file based on known processor state: A renaming register file complex for saving power is described. A mapping unit transforms an instruction register number (IRN) to a logical register number (LRN). The renaming register file maps an LRN to a physical register number (PRN), there being a greater number of physical registers than addressable by direct...

20060206690 - Maxq microcontroller: A microcontroller includes a program memory, data memory, central processing unit, at least one register module, a memory management unit, and a transport network. Instructions are executed in one clock cycle via an instruction word. The instruction word indicates the source module from which data is to be retrieved and...

20060206689 - Processor integrated circuit and product development method using the processor integrated circuit: A processor integrated circuit according to the present invention comprises low-speed and high-speed computing units (110), (120) as two or more kinds of computing units, a program memory (131) as a first storage unit in which programs for operation the computing units are stored, a data memory (second storage unit)...

20060206691 - Memory organization allowing single cycle pointer addressing where the address of the pointer is also contained in one of the memory locations: All Pointer-based accesses require first that the value contained in a pointer register (200a, 200b, 200c, 200d) to be read and then that value be used as an address to the appropriate region in random access memory (RAM) (104). As implemented today, this requires two memory read access cycles, each...

20060206692 - Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor: A dispatch scheduler in a multithreading microprocessor is disclosed. Each of N concurrently executing threads has one of P priorities. P N-bit round-robin vectors are generated, each being a 1-bit left-rotated and subsequently sign-extended version of an N-bit 1-hot input vector indicating the last thread selected for dispatching at the...

20060206693 - Method and apparatus to execute an instruction with a semi-fast operation in a staggered alu: A method for executing an instruction with a semi-fast operation in a staggered ALU. The method of one embodiment comprises generating a first operation and a second operation from a micro-instruction. The first and second operations are scheduled for execution in a staggered arithmetic logic unit (ALU). The first and...

20060206695 - Data movement within a processor: A processor, e.g., a VLIW processor, may include two separate execution units, a first execution unit may have a general-purpose register file and an arithmetic logic unit. The register file may source operands to the ALU, and the result of the ALU operation may be stored in the register file...

20060206694 - Parsing-enhancement facility: An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an...

20060206696 - Reconfigurable processor: The present invention provides a reconfigurable processing apparatus enabling clusters to utilize a shared functional unit by using data and a validity signal received from the clusters by way of a network therebetween. In the reconfigurable processing apparatus comprising one or more clusters which are reconfigured based on configuration information,...

20060206697 - System and method for trellis-based decoding: A decoder comprising a demodulator operable to receive a plurality of encoded data bits and generate a demodulated output, a channel decoder coupled to the demodulator operable to receive the demodulated output and generate decoded data bits, an encoder coupled to the channel decoder operable to receive the decoded data...

20060200645 - Apparatus and method for employing cloning for software development: The present invention provides a method and apparatus for employing cloning for creating hierarchies of artifacts needed for development of software. The present invention also applies to managing cloning for the maintenance and modification of software artifacts including tracking and propagating the changes to the artifacts. In accordance with the...

20060200646 - Data processing system with clustered ilp processor: The invention is based on the idea to specify operations from different cycles in one instruction and, consequently, to pipeline control connections to remote clusters. Therefore a data processing system is provided. Said system comprises a clustered ILP processor having a plurality of clusters each comprising at least one register...

20060200647 - Packet processor with wide register set architecture: A Wide Register Set (WRS) is used in a packet processor to increase performance for certain packet processing operations. The registers in the WRS have wider bit lengths than the main registers used for primary packet processing operations. A wide logic unit is configured to conduct logic operations on the...

20060200648 - High-level language processor apparatus and method: A digital computing component and method for computing configured to execute the constructs of a high-level software programming language via optimizing hardware targeted at the particular high-level software programming language. The architecture employed allows for parallel execution of processing components utilizing instructions that execute in an unknown number of cycles...

20060200649 - Data alignment and sign extension in a processor: A method comprising loading a plurality of data bytes from a data cache in response to a load instruction, determining the most significant bit of at least one of the data bytes using a first logic, arranging at least some of the data bytes onto a data bus using a...

20060200651 - Method and apparatus for power reduction utilizing heterogeneously-multi-pipelined processor: A processor includes a common instruction decode front end, e.g. fetch and decode stages, and a heterogeneous set of processing pipelines. A lower performance pipeline has fewer stages and may utilize lower speed/power circuitry. A higher performance pipeline has more stages and utilizes faster circuitry. The pipelines share other processor...

20060200652 - Method for signaling of a state or of an event: A first component is signaled from a second component by a status signal that a state or an event which requires a reaction has occurred. First data items are stored in the second component which can be set to a specific value by the second component and can be reset...

20060200650 - Single-cycle low-power cpu architecture: An n architecture for implementing an instruction pipeline within a CPU comprises an arithmetic logic unit (ALU), an address arithmetic unit (AAU), a program counter (PC), a read-only memory (ROM) coupled to the program counter, to an instruction register, and to an instruction decoder coupled to the arithmetic logic unit....

20060200653 - Decoding predication instructions within a superscalar data processing system: Within a multiple instruction pipeline data processing system which supports predication instructions, program instructions are initially decoded upon the assumption that they are predicated. A predication signal is generated within the instruction decoder stages when a predication instruction is detected. The presence or absence of this predication signal can then...

20060200654 - Stop waiting for source operand when conditional instruction will not execute: The delay of non-executing conditional instructions, that would otherwise be imposed while waiting for late operand data, is alleviated based on an early recognition that such instructions will not execute on the current pass through a pipeline processor. At an appropriate point prior to execution, a determination regarding the condition...

20060200655 - Forward looking branch target address caching: A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC...

20060200645 - Apparatus and method for employing cloning for software development: The present invention provides a method and apparatus for employing cloning for creating hierarchies of artifacts needed for development of software. The present invention also applies to managing cloning for the maintenance and modification of software artifacts including tracking and propagating the changes to the artifacts. In accordance with the...

20060200646 - Data processing system with clustered ilp processor: The invention is based on the idea to specify operations from different cycles in one instruction and, consequently, to pipeline control connections to remote clusters. Therefore a data processing system is provided. Said system comprises a clustered ILP processor having a plurality of clusters each comprising at least one register...

20060200647 - Packet processor with wide register set architecture: A Wide Register Set (WRS) is used in a packet processor to increase performance for certain packet processing operations. The registers in the WRS have wider bit lengths than the main registers used for primary packet processing operations. A wide logic unit is configured to conduct logic operations on the...

20060200648 - High-level language processor apparatus and method: A digital computing component and method for computing configured to execute the constructs of a high-level software programming language via optimizing hardware targeted at the particular high-level software programming language. The architecture employed allows for parallel execution of processing components utilizing instructions that execute in an unknown number of cycles...

20060200649 - Data alignment and sign extension in a processor: A method comprising loading a plurality of data bytes from a data cache in response to a load instruction, determining the most significant bit of at least one of the data bytes using a first logic, arranging at least some of the data bytes onto a data bus using a...

20060200651 - Method and apparatus for power reduction utilizing heterogeneously-multi-pipelined processor: A processor includes a common instruction decode front end, e.g. fetch and decode stages, and a heterogeneous set of processing pipelines. A lower performance pipeline has fewer stages and may utilize lower speed/power circuitry. A higher performance pipeline has more stages and utilizes faster circuitry. The pipelines share other processor...

20060200652 - Method for signaling of a state or of an event: A first component is signaled from a second component by a status signal that a state or an event which requires a reaction has occurred. First data items are stored in the second component which can be set to a specific value by the second component and can be reset...

20060200650 - Single-cycle low-power cpu architecture: An n architecture for implementing an instruction pipeline within a CPU comprises an arithmetic logic unit (ALU), an address arithmetic unit (AAU), a program counter (PC), a read-only memory (ROM) coupled to the program counter, to an instruction register, and to an instruction decoder coupled to the arithmetic logic unit....

20060200653 - Decoding predication instructions within a superscalar data processing system: Within a multiple instruction pipeline data processing system which supports predication instructions, program instructions are initially decoded upon the assumption that they are predicated. A predication signal is generated within the instruction decoder stages when a predication instruction is detected. The presence or absence of this predication signal can then...

20060200654 - Stop waiting for source operand when conditional instruction will not execute: The delay of non-executing conditional instructions, that would otherwise be imposed while waiting for late operand data, is alleviated based on an early recognition that such instructions will not execute on the current pass through a pipeline processor. At an appropriate point prior to execution, a determination regarding the condition...

20060200655 - Forward looking branch target address caching: A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC...