Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 08/06

20060195678 - Task sequence integration and execution mechanism with automated global condition checking and compensation: A method for verifying that a sequence of tasks is more likely to be successful prior to executing the sequence of tasks. First, a projection algorithm is performed to generate a precondition and postconditions list for the entire sequence. In order to execute the sequence of tasks, it is determined...

20060195679 - Processing apparatus: A processing apparatus includes an execution stage which executes each of instruction streams, a first resource counter which counts the number of operating resources used when the execution stage executes a first one of the instruction streams, a second resource counter which holds data of the number of unused ones...

20060195680 - Computer instruction value field having an embedded sign: A computer machine instruction is fetched and executed, the machine instruction having a signed field value wherein the signed field value comprises contiguous bit positions 1-N consisting of a contiguous most significant value contiguous with a contiguous embedded sign field, the embedded sign field contiguous with a contiguous least significant...

20060195681 - Test program instruction generation: An architectural definition of an instruction set is parsed to identify distinct program instructions therein. These distinct program instructions are associated with operand defining data specifying the variables they require. A complete set of such distinct program instructions and their associated operand defining data is generated for the instruction set...

20060195682 - Monitoring device with optimized buffer: The invention concerns a monitoring device (18) integrated to a microprocessor chip (12) executing a series of instructions comprising: means (26) for producing simultaneously several types of monitoring messages of the microprocessor, a buffer (28) divided into several blocks (A, B, C, D, E) each of which is designed to...

20060195684 - Reconfigurable data processing device and method: A reconfigurable data processing device equipped with a plurality of data processing units controls timing of switching contents of data processing executed by each of the plurality of data processing units for each of a plurality of data processing operations....

20060195683 - Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts: A multiprocessing system is disclosed. The system includes a multithreading microprocessor including a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a shared privileged resource, shared by the plurality of TCs rather than being...

20060190700 - Handling permanent and transient errors using a simd unit: A method for handling permanent and transient errors in a microprocessor is disclosed. The method includes reading a scalar value and a scalar operation from an execution unit of the microprocessor. The method further includes writing a copy of the scalar value into each of a plurality of elements of...

20060190701 - Data processor: There is provided at least one processor block including a plurality of load store interfaces (801, 804), a plurality of memory banks (821), an input/output port having at least one of an input port (850) and an output port (860), and a crossbar switch (810), and the crossbar switch connects...

20060190702 - Device and method for correcting errors in a processor having two execution units: A method and a device for correcting errors in a processor having two execution units as well as a corresponding processor, in which registers are provided in which instructions and/or associated information can be stored, the instructions being processed redundantly in both execution units and comparison means being included, and...

20060190703 - Programmable delayed dispatch in a multi-threaded pipeline: Detecting a stall condition associated with processor instructions within one or more threads and generating a no-dispatch condition. The stall condition can be detected by hardware and/or software before and/or during processor instruction execution. The no-dispatch condition can be associated with a number of processing cycles and an instruction from...

20060190704 - Apparatus for increasing addressability of registers within a processor: An apparatus for increasing addressability of registers within a processor is disclosed. The apparatus includes a set of apparent registers and a set of real registers. The total number of real registers is substantially higher than the total number of apparent registers such that only a subset of the real...

20060190705 - Processor utilizing novel architectural ordering scheme: Various methods, apparatuses, and systems in which a processor includes an issue engine and an in-order execution pipeline. The issue engine categorizes operations as at least one of either a speculative operation which perform computations or an architectural operation which has potential to fault or cause an exception. Each architectural...

20060190706 - Processor utilizing novel architectural ordering scheme: Various methods, apparatuses, and systems in which a processor includes an issue engine and an in-order execution pipeline. The issue engine categorizes operations as at least one of either a speculative operation which perform computations or an architectural operation which has potential to fault or cause an exception. Each architectural...

20060190707 - System and method of correcting a branch misprediction: When a branch misprediction in a pipelined processor is discovered, if the mispredicted branch instruction is not the last uncommitted instruction in the pipelines, older uncommitted instructions are checked for dependency on a long latency operation. If one is discovered, all uncommitted instructions are flushed from the pipelines without waiting...

20060190708 - Multifunction hexadecimal instruction form: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point...

20060190709 - Method and system for branch prediction: A system and method for predicting the outcome of a conditional branch within a computer system, the method comprising the steps of identifying (105) the occurrence of a conditional branch, obtaining (106) data relating to system activity since a previous branch, comparing (110) said data with data relating to previous...

20060190710 - Suppressing update of a branch history register by loop-ending branches: Conditional branch instructions that terminate code loops are detected, and a Branch History Register (BHR) is prevented from updating to store the loop-ending branch evaluations. This prevents the branch that implements loop iterations from displacing other branch evaluation histories from the BHR. The loop-ending branch may be detected statically, by...

20060190711 - Method and apparatus for managing a return stack: A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of return addresses from the return stack. Popping multiple return addresses from the...

20060184765 - Method and apparatus for producing an index vector for use in performing a vector permute operation: A method for generating a permutation index vector includes receiving a condition vector and performing an index generation function using the condition vector in order to generate the permutation index vector. An index vector generation circuit is also disclosed....

20060184766 - Processing system: A processing system according to the invention comprises a plurality of processing elements (PE1, . . . ,PE7). The processing elements comprise a controller and computation means. The plurality of processing elements is dynamically reconfigurable as mutually independently operating task units (TU1, TU2, TU3), which task units comprise one processing...

20060184767 - Dynamic recalculation of resource vector at issue queue for steering of dependent instructions: A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared...

20060184768 - Method and apparatus for dynamic modification of microprocessor instruction group at dispatch: Dynamic reformatting of a dispatch group by selective activation of inactive Start bits of instructions within the dispatch group at the time the instructions are read from the IBUF. The number of instructions in the reformatted dispatch groups can vary from as few as one instruction per group to a...

20060184769 - Localized generation of global flush requests while guaranteeing forward progress of a processor: Localized generation of global flush requests while providing a means for increasing the likelihood of forward progress in a controlled fashion. Local hazard (error) detection is accomplished with a trigger network situated between execution units and configurable state machines that track trigger events. Once a hazardous state is detected, a...

20060184770 - Method of implementing precise, localized hardware-error workarounds under centralized control: In a processor, a localized workaround is activated upon the sensing of a problematic condition occurring on said processor, and then control of the deactivation of the localized workaround is superseded by a centralized controller. In a preferred embodiment, the centralized controller monitors forward progress of the processor and maintains...

20060184772 - Lookahead mode sequencer: A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the...

20060184771 - Mini-refresh processor recovery as bug workaround method using existing recovery hardware: A method in a data processing system for avoiding a microprocessor's design defects and recovering a microprocessor from failing due to design defects, the method comprised of the following steps: The method detects and reports of events which warn of an error. Then the method locks a current checkpointed state...

20060184773 - Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units: A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted...

20060184775 - Computer system with debug facility for debugging a processor capable of predicated execution: A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in...

20060184774 - Context-based operation reconfigurable instruction set processor and method of operation: A reconfigurable context-based operation instruction set processor for use in a processing system capable of executing a first instruction set. The reconfigurable context-based operation instruction set processor comprises: 1) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and 2) a programmable finite state machine capable of controlling...

20060184777 - Method, apparatus and computer program product for identifying sources of performance events: Event vectors are included in an instruction tracking structure of a processor to collect history for every instruction flowing through the processor. Such an event vector, by its nature, cannot be whole until the vector's corresponding instruction completes. However, some information for the event vector is collected earlier, i.e., as...

20060184776 - Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor: A method for pseudo-randomly, without bias, selecting instructions for marking in a microprocessor. Responsive to reading an instruction from an instruction cache, an instruction tag associated with the instruction is compared against a pseudo-randomly generated value in a linear feedback shift register (LFSR). If the instruction tag matches the value...

20060184778 - Systems and methods for branch target fencing: Systems and methods for handling the event of a wrong branch prediction and an instruction rejection in a digital processor are disclosed. More particularly, hardware and software are disclosed for detecting a condition where a branch instruction was mispredicted and an instruction that preceded the branch instruction is rejected after...

20060184779 - Pipeline controller for context-based operation reconfigurable instruction set processor: An instruction execution pipeline for use in a data processor. The instruction execution pipeline comprises: 1) an instruction fetch stage; 2) a decode stage; 3) an execution stage; and 4) a write-back stage. The instruction pipeline repetitively executes a loop of instructions by fetching and decoding a first instruction associated...

20060174089 - Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture: A method, system, and computer program product for mixing of conventional and augmented instructions within an instruction stream, wherein control may be directly transferred, without operating system intervention, between one type of instruction to another. Extra instruction word bits are added in a manner that is designed to minimally interfere...

20060174090 - Power efficient instruction prefetch mechanism: A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when...

20060174091 - Instruction grouping history on fetch-side dispatch group formation: An improved method, apparatus, and computer instructions for grouping instructions processed in equal sized sets. A current set of instructions is received in an instruction cache for dispatching. A determination is made as to whether any instructions in the current set of instructions are part of a group including a...

20060174092 - Fetch-side instruction dispatch group formation: An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system. Instructions in the set of instructions are grouped into a dispatch grouping of instructions prior to the set of instructions being placed in...

20060174093 - System and method for event based interportlet communications: In accordance with embodiments, there are provided mechanisms and methods for configuring and executing portlet responses to events within a web portal framework. These mechanisms and methods can enable event descriptions to be organized within a portlet configuration file with event handlers designated for responding to the event. As used...

20060174094 - Systems and methods for providing complementary operands to an alu: Systems, methods and media for providing complementary operands to the arithmetic/logic unit of a processor are disclosed. A determination is made whether both a result of an instruction and a complement of that result are called for by a next instruction. If so, a value is input to a first...

20060174095 - Branch encoding before instruction cache write: Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the target of the branch prior to Writing the branch...

20060174096 - Methods and systems for storing branch information in an address table of a processor: Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and...

20060174097 - Generation of a computer program to test for correct operation of a data processing apparatus: Software built in self test computer programs 12 are generated using a genetic algorithm 14 technique. A fault simulator 20 is used to simulate candidate software built in self test computer programs and compare the simulated execution, such to deliberately introduced test faults, with expected execution outcomes previously derived for...