Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 07/06

20060168423 - Array synchronisation: A method is disclosed for achieving synchronization in an array of semi-synchronous devices. A processor array has an array of processor elements, wherein each of said processor elements comprises a cycle counter, and a master processor element is able to transmit control command signals to each of the other processor...

20060168424 - Processing apparatus, processing method and compiler: Differences in encoding efficiency of instructions may arise if certain operations require very large immediate values as operands, as opposed to others requiring no immediate values or small immediate values. The present invention describes a processing apparatus, a compiler as well as a method for processing data, allowing the use...

20060168425 - Method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed: A method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed. At least some of the exemplary embodiments may be a method comprising operating duplicate copies of a user program in a first and second processor, allowing at least one...

20060168426 - System and method for selectively controlling operations in lanes: A computer system is disclosed capable of conditionally carrying out an operation defined in a computer instruction. The computer instruction is implemented on so-called packed operands, that is operands containing a plurality of packed objects in respective lanes. An operation defined in the computer instruction is conditionally carried out in...

20060168430 - Apparatus and method for concealing switch latency: An multi-threading processor is provided. The multi-threading processor includes a front end module, an execution module coupled to the front end module, and a state module coupled to both the front end module and the execution module. The processor also includes a switch logic module, which is coupled to the...

20060168429 - Deterministic microcontroller with configurable input/output interface: A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers...

20060168427 - Deterministic microcontroller with context manager: A deterministic microprocessor is disclosed in which a plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed...

20060168428 - Method of providing microcontroller context management: A method of operating a deterministic microcontroller is disclosed in which the microcontroller is switchable to various contexts. A plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls...

20060168431 - Method and apparatus for jump delay slot control in a pipelined processor: An improved method and apparatus for implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of controlling branching and the execution of instructions within the pipeline is disclosed. In one embodiment, the method comprises defining three discrete...

20060168432 - Branch prediction accuracy in a processor that supports speculative execution: One embodiment of the present invention provides a system which improves branch prediction accuracy in a processor that supports speculative-execution. During normal-execution mode, the system issues instructions in program order. Upon encountering a launch condition which causes a processor to enter a speculative-execution mode, the system performs a checkpoint and...

20060168433 - Method and apparatus for efficient and flexible sequencing of data processing units extending vliw architecture: A very long instruction word processor with sequence control. During each cycle the processor generates control signals to functional units based on the values in fields of an instruction. Each instruction may include an iteration count specifying the number of cycles for which the control signals should be generated based...

20060168434 - Method and system of aligning execution point of duplicate copies of a user program by copying memory stores: A method and system of aligning execution point of duplicate copies of a user program by copying memory stores. Some of the exemplary embodiments may be a method comprising aligning the execution point of duplicate copies of a user program executed in a first and second processor by copying only...

20060161762 - Method and logical apparatus for managing processing system resource use for speculative execution: A method and logical apparatus for managing processing system resource use for speculative execution reduces the power and performance burden associated with inefficient speculative execution of program instructions. A measure of the efficiency of speculative execution is used to reduce resources allocated to a thread while the speculation efficiency is...

20060161763 - Microcomputer and encoding system for instruction code and cpu: A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral...

20060155954 - Selective macro event recording: A method, system and apparatus for selective macro event recording. In accordance with the present invention, events can be selectively included in a macro recording process, even where the events occur across different contexts such as different application windows in different applications. Specifically, once a macro recording session has been...

20060155955 - Simd-risc processor module: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which...

20060155956 - Processor array: There is disclosed a processor array, which achieves an approximately constant latency. Communications to and from the farthest array elements are suitably pipelined for the distance, while communications to and from closer array elements are deliberately “over-pipelined” such that the latency to all end-point elements is the same number of...

20060155957 - Encoding method for very long instruction word (vliw) dsp processor and decoding method thereof: An encoding method for a very long instruction word (VLIW) DSP processor and decoding method thereof. The encoding method involves a plurality of first encoding portions and a plurality of second encoding portions. The first encoding portions and second encoding portions are complied from an instruction. The first encoding portions...

20060155958 - Processor architecture: A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimised for use in signal processing operations, in that the multiple execution...

20060155959 - Method and apparatus to provide efficient communication between processing elements in a processor unit: A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is transferred over a first bus from processing element to processing element....

20060155960 - Programmable controller: A programmable controller has a multi-purpose processor such as an MPU and an application specific control device such as an ASIC (application specific integrated circuit). When the MPU requests the ASIC to execute a user program and the ASIC is activated, the MPU executes an event process while the ASIC...

20060155961 - Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor: Method and apparatus for reformatting instructions in a pipelined processor. An instruction register holds a plurality of instructions received from a cache memory external to the processor. A predecoder predecodes each of the instructions and determines from an instruction operation field where the instruction fields should be placed. A multiplexer...

20060155963 - Assist thread for injecting cache memory in a microprocessor: A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference...

20060155964 - Method and apparatus for enable/disable control of simd processor slices: Methods and apparatus provide for disabling at least some data path processing circuits of a SIMD processing pipeline, in which the processing circuits are organized into a matrix of slices and stages, in response to one or more enable flags during a given cycle....

20060155962 - Processing activity masking in a data processing system: Apparatus for processing data under control of data processing instructions specifying data processing operations, said apparatus comprising: a first execution mechanism operable to execute a first set of data processing instructions; a second execution mechanism operable to execute a second set of data processing instructions, said first set of data...

20060155965 - Method and apparatus for control signals memoization in a multiple instruction issue microprocessor: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register...

20060155966 - Processor including a register file and method for computing flush masks in a multi-threaded processing system: A processor including a register file and method for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent...

20060155967 - Processing essential and non-essential code separately: A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the...

20060155968 - Electronic computer, semiconductor integrated circuit, control method, program generation method, and program: An application program is executed and is easily made reusable by dividing the application program into processing units, and by creating a logical circuit in the reconfigurable hardware by switching so as to improve the processing speed at low cost. The electronic computer comprises a processing device 70. The processing...

20060155969 - Reconfigurable, expandable semiconductor integrated circuit: A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter...

20060155970 - Monitoring a microprocessor programme by sending time-trackable messages: The invention concerns a monitoring device (18′, 18″) integrated to the chip of a microprocessor (12) executing a series of instructions comprising message calculating means (36) for upon each execution of an instruction, producing a corresponding digital message; a buffer memory (34) for storing each message produced; and a plurality...

20060155971 - Transmission of a digital message between a microprocessor monitoring circuit and an analysis tool: The invention relates to a method for the transmission of digital messages by a monitoring circuit (18) which is integrated into a microprocessor (12), said method being performed during the execution of a series of instructions by the microprocessor. Moreover, at least one of said digital messages represents the detection...

20060155972 - Method in pipelined data processing: A method in a processor is presented, in which data is processed in a pipelined manner, the data being included in a plurality of contexts, comprising a first (3), in addition to which a plurality of operations is adapted to be executed on the contexts. The method comprises executing an...

20060155973 - Multithreaded hardware systems and methods: Multithreaded hardware systems and methods are disclosed. One embodiment of a system may comprise a multithreaded processor comprising a register file having N hardware threads, where N is an integer greater than or equal to one, and an offline storage structure having M hardware threads, where M is an integer...

20060155974 - Data processing system having flexible instruction capability and selection mechanism: If a data processing system (10) implements more than one instruction set within a single processor (12), then program portions encoded using a first instruction set will need to be able to call program portions encoded using a second instruction set. This switching between instruction sets requires that the processor...

20060155975 - Method and apparatus for processing conditonal branch instructions: In the programming of a microcontroller (100) carried out in at least one machine-dependent assembly language in which the assembler commands, with the exception of conditional program branches, are executable essentially independently of data,—in case of a fulfilled branch condition, for example, at least one fulfilled status flag, at least...

20060155976 - Processor, microcomputer and method for controlling program of microcomputer: A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgement instruction in the special task,...

20060149920 - Object oriented mission framework and system and method: A mission system includes a peer vector machine having a host processor and pipeline accelerator and including bridge objects that provide communication via signal objects, message objects, and mission objects....

20060149921 - Method and apparatus for sharing control components across multiple processing elements: Method and apparatus for sharing control components across multiple processing elements. In one embodiment, common control components, including a control store and instruction control unit, are shared across multiple processing cores on a combined microengine. Each processing core includes a respective datapath and register file. Instruction gating logic is employed...

20060149922 - Multiple computational clusters in processors and methods thereof: A processor may have more than one computational cluster. An instruction packet may include an instruction replication control word to indicate that a particular machine language instruction in the instruction packet is to be executed in parallel by two or more of the computational clusters. An instruction packet may include...

20060149923 - Microprocessor optimized for algorithmic processing: Provided is a microprocessor optimized for algorithmic processing for accelerating algorithm processing through a closely coupled set of parallel sub-processing elements. The device includes a primary processor, one or more subprocessors and an interconnecting buss. The buss is preferably a crossbar buss. The primary processor is preferably a pipelined CPU...

20060149924 - Evaluation unit for single instruction, multiple data execution engine flag registers: According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might perform evaluation operations across multiple vectors being processed by the SIMD execution engine. According to some embodiments, a vertical evaluation unit might perform...

20060149925 - High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution: The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of...

20060149926 - Control words for instruction packets of processors and methods thereof: Control words are included in instruction packets to influence how one or more instructions in the packet are executed. Whether the control word is short or long will depend upon the situation. A short control word will be included in the packet in the event that the short control word...

20060149927 - Processor capable of multi-threaded execution of a plurality of instruction-sets: A processor (100) capable of receiving a plurality of instructions sets from at least one memory (50), and capable of multi-threaded execution of the plurality of instruction sets. The processor includes at least one decoder (130) capable of decoding and interpreting instructions from the plurality of instruction sets. The processor...

20060149928 - Aligning instructions using a variable width instruction alignment engine: In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based...

20060149929 - Processor with automatic scheduling of operations: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand...

20060149932 - Data processing circuit, multiplier unit with pipeline, alu and shift register unit for use in a data processing circuit: The present invention provides a circuit of processing integer data, especially for graphic applications having a multiplier unit which includes a pipeline in which the word length is adjustable for multiplying integer data s words of 8 bits or multiples thereof an arithmetic logic unit (ALU) for performing arithmetic operations...

20060149931 - Runahead execution in a central processing unit: According to one embodiment, a method is disclosed. The method includes detecting a load miss at a central processing unit (CPU), stalling a read only buffer (ROB), speculatively retiring an instruction causing the ROB stall and subsequent instructions, keeping registers that have not been renamed in the ROB upon retirement,...

20060149930 - Systems and methods for improving performance of a forwarding mechanism in a pipelined processor: Systems and methods for forwarding instruction results from various pipeline stages to the initial stages of the pipelines, where the results can be used in the execution of subsequent instructions. In one embodiment, a forwarding mechanism is designed so that sets of one or more dynamic data selection circuits are...

20060149933 - Branch lookahead prefetch for microprocessors: A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and...

20060149935 - Load lookahead prefetch for microprocessors: The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such...

20060149934 - Using a modified value gpr to enhance lookahead prefetch: The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future...

20060149938 - Determining a register file region based at least in part on a value in an index register: According to some embodiments, a value is retrieved from a location in an index register. A region in a register file may then be determined based at least in part on the value. Information may then be stored into the determined region of the register file....

20060149939 - Multimedia coprocessor control mechanism including alignment or broadcast instructions: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes...

20060149936 - Processor core interface for external hardware modules and methods thereof: A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to one or more arbitrary functional units external to the processor core. The interface is to provide the arbitrary functional units...

20060149937 - Register file regions for a processing system: According to some embodiments, a dynamic region in a register file may be described for an operand. The described region may, for example, store multiple data elements, each data element being associated with an execution channel of an execution engine. Information may then be stored into and/or retrieved from the...

20060149940 - Implementation to save and restore processor registers on a context switch: A method and apparatus for enabling a processor to perform a save and restore on a context switch incrementally and on demand. In one embodiment, when OS switches to a new process, the processor saves only those registers that have been modified in the current process. The processor may not...

20060149941 - Method and apparatus for vector execution on a scalar machine: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed...

20060149942 - Microcontroller and assigned method for processing the programming of the micro-con- troller: In order to further develop a microcontroller (100) the programming of which is carried out in at least one machine-dependent assembler language in which the assembler commands, with the exception of conditional program jumps or branches, can be executed in essence independently of data, together with a method for processing...

20060149943 - System and method for simulating hardware interrupts: A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a “no operation” (or NOOP) instruction would normally be inserted. The instruction is inserted is a conditional branch instruction, called a BISLED, that branches if there is external data in a...

20060149945 - Facilitating value prediction to support speculative program execution: One embodiment of the present invention provides a system that predicts a result produced by a section of code in order to support speculative program execution. The system begins by executing the section of code using a head thread in order to produce a result. Before the head thread produces...

20060149944 - Method, apparatus, and computer program product for selectively prohibiting speculative conditional branch execution: A method, apparatus, and computer program product are disclosed for selectively prohibiting speculative conditional branch execution. A particular type of conditional branch instruction is selected. An indication is stored within each instruction that is the particular type of conditional branch instruction. A processor then fetches a first instruction from code...

20060149946 - Time-multiplexed speculative multi-threading to support single-threaded applications: One embodiment of the present invention provides a system that facilitates interleaved execution of a head thread and a speculative thread within a single processor pipeline. The system operates by executing program instructions using the head thread, and by speculatively executing program instructions in advance of the head thread using...

20060149947 - Branch instruction prediction and skipping method using addresses of precedent instructions: A method of predicting branch instructions and a method of skipping branch instructions for pipelines which need more than one cycle to predict branch direction and branch target addresses in microprocessors and digital signal processors are provided. The address of an instruction executed before the predicted branch is used as...

20060149948 - Branch predicting apparatus and branch predicting method: A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack stores, when an execution of a call instruction of a subroutine is completed, address information of a return destination of a corresponding return...

20060149949 - Data processing device with branch prediction mechanism: Phantom entries of entries in a branch history are completely detected using a flag identifying a phantom and a flag detecting the misalignment between the address of an instruction and an address where a branch has been predicted, which are provided for a queue executing branch instruction and controlling a...

20060149950 - Data processing device with branch prediction mechanism: Phantom entries of entries in a branch history are completely detected using a flag identifying a phantom and a flag detecting the misalignment between the address of an instruction and an address where a branch has been predicted, which are provided for a queue executing branch instruction and controlling a...

20060149951 - Method and apparatus for updating global branch history information: A method and apparatus for updating global branch history information are disclosed. A dynamic branch predictor within a data processing system includes a global branch history (GBH) buffer and a branch history table. The GBH buffer contains GBH information of a group of the most recent branch instructions. The branch...

20060149952 - Exception handling in a multiprocessor system: In one embodiment, a first processor of a multiprocessor system, encounters an exception and jumps to exception handler code at an architecture-defined exception vector. The processor is directed to a data structure which provides a programmable exception vector to additional exception handler code. This additional code may be executed as...

20060149953 - Conditional execution per lane: A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one operand store for holding operands on which an operation defined in an instruction is to be performed, wherein said operand store defines a plurality of lanes...