Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 05/06

20060112257 - Microprocessor architected state signature analysis: Techniques are disclosed for generating signatures representing modifications to architected state in a microprocessor. A plurality of signals representing a plurality of architected states of a goal microprocessor may be combined to produce a goal architected state signature of the goal microprocessor. The goal microprocessor may be actual or simulated...

20060112258 - Parallel data path architecture for high energy efficiency: Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performance. Also, since only necessary process units and function units...

20060112259 - Method and apparatus for instruction set architecture with control instructions for signal processors: An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control...

20060112260 - Method and apparatus of instruction execution for signal processors: An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control...

20060112261 - Method and apparatus for incremental commitment to architectural state in a microprocessor: Method and hardware apparatus are disclosed for reducing the rollback penalty on exceptions in a microprocessor executing traces of scheduled instructions. Speculative state is committed to the architectural state of the microprocessor at a series of commit points within a trace, rather than committing the state as a single atomic...

20060112262 - Branch prediction of unconditionally executed branch instructions: A data processing system 2 includes an instruction pipeline with a branch prediction mechanism. The branch prediction mechanism includes a branch history register 20 operating to store a value GHV which can be used to identify whether a newly encountered branch instruction is one which has been previously encountered. If...

20060107027 - General purpose micro-coded accelerator: A micro-coded accelerator may comprise multiple programmable control units, multiple special function units, a cross-bar switch to connect any of the control units to any one or more of the special function units, and a global memory to facilitate processing by these units. Each control unit may have an array...

20060107028 - Loop control circuit for a data processor: A data processor (200) includes an operation execution unit (225) for executing instructions from an instruction memory (210) indicated by a program counter (220). A loop control circuit (230) stores respective associated loop information for a plurality of instruction loops in a register bank (232). The loop information includes at...

20060101230 - Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stages: In one embodiment, a programmable processor searches an array of N data elements in response to N/M machine instructions, where the processor has a pipeline configured to process M data elements in parallel. In response to the machine instructions, a control unit directs the pipeline to retrieve M data elements...

20060101232 - Semiconductor integrated circuit: There are provided dedicated cell groups 1304, 1306 for executing memory access processing to built-in memories 1313, 1312 in a plurality of ALU cells. Further there are provided dedicated cell groups 1304, 1306 enabling access commonly available for built-in memories to a peripheral circuit 1201 or LSI external device 206....

20060101231 - Semiconductor signal processing device: An instruction for an arithmetic/logic operation to a main processing circuit is stored in the form of a micro program in a micro instruction memory, and the operation of the main processing circuit is controlled in accordance with the micro program, under the control of a controller. In the main...

20060101233 - Clustered instruction level parallelism processor: The basic idea of the invention is to provide a clustered ILP processor based on a fully-connected inter-cluster network with a non-uniform latency. A clustered Instruction Level Parallelism processor is provided. Said processor comprises a plurality of clusters (C1-C6) each comprising at least one register file (RF) and at least...

20060101234 - Systems and methods of balancing crossbar bandwidth: Systems and methods of balancing crossbar bandwidth in a multiprocessing system are disclosed. In an exemplary embodiment a system may comprise a crossbar switch having a plurality of links to processors in the multiprocessing system. A plurality of synchronizers is provided to receive micropackets from the links. At least one...

20060101235 - Microprocessor: The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of components are interconnected in a manner which allows connection between some of the components to be varied...

20060101236 - Method and apparatus for increasing processing speed using quantum coprocessor: A method and apparatus for increasing a processing speed using a quantum coprocessor are provided. The method includes receiving a command and data for performing a predetermined task, converting the command and the data into a signal having a format that the quantum coprocessor can receive if the command requests...

20060101237 - Data flow machine: Methods and apparatuses for automatically forming a data flow machine using a graph representing source code are provided. At least one first hardware element may be configured to perform at least one first function associated with a respective node in the graph. A firing rule for at least one of...

20060101238 - Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches: A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache...

20060101239 - Program-controlled unit having a prefetch unit: A program-controlled unit stores return addresses not only in a system stack but also in a return stack. The instructions which have already been taken into the program-controlled unit, but are not currently required, are stored in a storage device for alternative instructions. At times when the program-controlled unit is...

20060101240 - Digital signal processing circuit and digital signal processing method: According to an aspect of the present invention, there is provided with a digital signal processing circuit, including: an instruction memory which outputs an instruction code containing at least one instruction and a selection code; an extended-instruction storage which stores extended instructions; a selector which selects, from the extended-instruction storage,...

20060101241 - Instruction group formation and mechanism for smt dispatch: A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on...

20060101245 - Apparatus and method for matrix data processing: A matrix data processor is implemented wherein data elements are stored in physical registers and mapped to logical registers. After being stored in the logical registers, the data elements are then treated as matrix elements. By using a series of variable matrix parameters to define the size and location of...

20060101244 - Multipurpose functional unit with combined integer and floating-point multiply-add pipeline: A multipurpose functional unit is configurable to support a number of operations including floating-point and integer multiply-add, operations as well as other integer and/or floating-point arithmetic operations, Boolean operations, comparison testing operations, and format conversion operations....

20060101243 - Multipurpose functional unit with multiply-add and logical test pipeline: A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations....

20060101242 - Multipurpose multiply-add functional unit: A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations....

20060101247 - Apparatus and method for generating constant values: A data processing apparatus and method for generating constant values is provided. The data processing apparatus comprises a data processing unit operable in response to an instruction to perform a data processing operation on one or more data values. Shift logic is operable to selectively apply a shift operation to...

20060101246 - Bit manipulation method, apparatus and system: A bit manipulation processor, system and method are provided which reduces the number of operations performed during data processing. An additional register is used as a buffer. The buffer has a bit length which is preferably greater than the address boundaries in a memory or register address. A bitstream can...

20060101248 - Method and programmable unit for bit field shifting: A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is...

20060101249 - Arrangements for adaptive response to latencies: A response to the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. Broadly contemplated herein are braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered. These partial orders can be used to respond adaptively to memory latencies. It is...

20060101250 - Configurable computing machine and related systems and methods: A computing machine includes programmable integrated circuits, a configuration registry, and a processor. The registry stores a file that defines a circuit having portions, and the processor is, in response to the file, operable to instantiate one of the circuit portions on one of the programmable integrated circuits. Consequently, by...

20060101251 - System and method for simultaneously executing multiple conditional execution instruction groups: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously...

20060101253 - Computing machine with redundancy and related systems and methods: According to an embodiment of the invention, a computing machine comprises a pipeline accelerator, a host processor coupled to the pipeline accelerator, and a redundant processor, a redundant pipeline unit, or both, coupled to the host processor and to the pipeline accelerator. The computing machine may also include a system-restore...

20060101252 - Information processing apparatus and context switching method: An information processing apparatus which, when executing a plurality of predetermined units of processing, executes the predetermined units of processing in parallel by a processor by switching between contexts associated with the respective predetermined units. The processing apparatus comprises a plurality of register banks that respectively store the contexts associated...

20060101254 - Start transactional execution (ste) instruction to support transactional program execution: One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the...

20060101255 - Method and apparatus for clearing hazards using jump instructions: A method and apparatus for overlaying hazard clearing with a jump instruction within a pipeline microprocessor is described. The apparatus includes hazard logic to detect when a jump instruction specifies that hazards are to be cleared as part of a jump operation. If hazards are to be cleared, the hazard...

20060101256 - Looping instructions for a single instruction, multiple data execution engine: According to some embodiments, looping instructions are provided for a Single Instruction, Multiple Data (SIMD) execution engine. For example, when a first loop instruction is received at an execution engine information in an n-bit loop mask register may be copied to an n-bit wide, m-entry deep loop stack....

20060101257 - System and method to provide a processor with dynamic instruction set and decoder: A system and method to provide a processor with a dynamic instruction set and decoder is provided. One embodiment provides a micro-processor with a dynamic instruction set, the instruction set is updated on the fly. A single instruction can be interpreted in many different ways depending on the current configuration...

20060101258 - Microprocessor instructions for efficient bit stream extractions: A method of extracting bits of a bit stream including retrieving bits from the bit stream into an accumulator, specifying a size value specifying a number of bits to extract, storing a position value into a control register, and executing a bit extraction instruction. The bit extraction instruction includes copying...

20060095710 - Clustered ilp processor and a method for accessing a bus in a clustered ilp processor: The basic idea of the invention is to add switches along a bus, in order divide the bus into smaller independent segments by opening/closing said switches. A clustered Instruction Level Parallelism processor comprises a plurality of clusters (C1-C6) each comprising at least one register file (RF) and at least one...

20060095711 - Method for wiring allocation and switch configuration in a multiprocessor environment: A method for wiring allocation and switch configuration in a multiprocessor computer, the method including employing depth-first tree traversal to determine a plurality of paths among a plurality of processing elements allocated to a job along a plurality of switches and wires in a plurality of D-lines, and selecting one...

20060095714 - Clip instruction for processor: A processor ISA instruction which performs a clipping operation forcing a data element to be within a specified range. A SIMD processor ISA instruction which performs a clipping operation upon each data element in a source operand vector....

20060095713 - Clip-and-pack instruction for processor: A processor ISA instruction which performs a clipping operation forcing a data element to be within a specified range. A SIMD processor ISA instruction which performs a clipping operation upon each data element in a source operand vector. A SIMD processor ISA instruction which performs clipping upon each data elements...

20060095712 - Simd processor having enhanced operand storage interconnects: A SIMD processor includes an ALU having data interconnects facilitating the concurrent processing of overlapping data portions of at least one operand store. Such interconnects facilitate the calculation of shift-invariant convolutions, and sum of absolute differences between an operand in the operand store and another operand....

20060095717 - Processor having compound instruction and operation formats: A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with...

20060095716 - Super-reconfigurable fabric architecture (surfa): a multi-fpga parallel processing architecture for cots hybrid computing framework: A field programmable gate array includes a virtual bus interface that receives a control word from a host processor over a standard I/O bus. A configurable very long instruction word (VLIW) controller receives the control word via virtual bus interface signals mapped from the virtual bus interface. A reconfigurable communication...

20060095715 - Very long instruction word processor: The invention relates to a very long instruction word (VLIW) processor comprising a plurality of functional units (110, 130, 135), each for executing an operation, and a VLIW controller (100) connected to each of said functional units (110, 130, 135) and adapted to controlling said functional units (110, 130, 135)....

20060095723 - Method and apparatus for interfacing a processor to a coprocessor: A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register...

20060095719 - Microcontroller having partial-twin structure: A partial twin microprocessor structure which can run multiple tasks in parallel is disclosed. The partial-twin microprocessor structure comprises a first set of processing units to be shared by at least two tasks running in parallel, a plurality of program counters to store a plurality of program addresses for different...

20060095722 - Program subgraph identification: There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing...

20060095720 - Reuseable configuration data: There is provided an information processor for executing a program comprising a plurality of separate program instructions: processing logic operable to individually execute said separate program instructions of said program; an operand store operable to store operand values; and an accelerator having an array comprising a plurality of functional units,...

20060095718 - System and method for providing a persistent function server: A system and method for providing a persistent function server is provided. A multi-processor environment uses an interface definition language (idl) file to describe a particular function, such as an “add” function. A compiler uses the idl file to generate source code for use in marshalling and de-marshalling data between...

20060095721 - Tightly coupled accelerator: An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within...

20060095724 - Message-passing processor: A processor designed to directly execute machine code that is based on the asynchronous pi-calculus is disclosed. Such a processor may be an element of a multi-processor system that aims to provide a scalable, loosely-coupled architecture for executing programs based on the pi-calculus....

20060095726 - Independent hardware based code locator: A hardware code relocator compiles code and executes starting at any address in memory. A hardware mechanism external to a CPU re-directs an instruction to the appropriate physical location in memory by adding a vector base offset to a fetch address and retrieving the instruction based upon a new fetch...

20060095725 - Method and apparatus for executing instructions from an auxiliary data stream: System and method for the execution of instructions from an auxiliary data stream in a parallel processing system are presented. The data processing system includes a program sequencer, an array processor and data input/output logic. Rather than increasing the program memory size to accommodate the most extreme application requirements, a...

20060095727 - Information processing device and information processing method: An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period...

20060095728 - Method and apparatus to provide a source operand for an instruction in a processor: A method and apparatus for providing a source operand for an instruction to be executed in a processor. Some embodiments may include a register file unit that has registers and a scheduler to schedule instructions. In some embodiments, the scheduler is to asynchronously receive an instruction and a source operand...

20060095729 - Multithreaded processor with multiple concurrent pipelines per thread: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective...

20060095730 - Expansion of compute engine code space by sharing adjacent control stores using interleaved program addresses: Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores...

20060095733 - Hardware device for executing conditional instruction out-of-order fetch and execution method thereof: A hardware device for executing conditional instructions out-of-order and the execution method. An architecture is provided, enabling the hardware device such as a processor supporting the conditional instruction and a computer system to execute the instruction out-of-order. To this end, a conditional execution buffer is provided, and a register of...

20060095731 - Method and apparatus for avoiding read port assignment of a reorder buffer: An out-of-order subsystem of a processor includes a register alias table and allocation (RAT/ALLOC) unit, a reservation station (RS) and a reorder buffer (ROB). Destination identifiers of one or more execution results that are not yet stored in any register file of the ROB may be compared to source identifiers...

20060095732 - Processes, circuits, devices, and systems for scoreboard and other processor improvements: A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the...

20060095736 - Clustered superscalar processor and communication control method between clusters in clustered superscalar processor: A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction window whether there is a data dependency relationship between the instruction that will be stored in the instruction window and...

20060095734 - Processor with dependence mechanism to predict whether a load is dependent on older store: A processor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation...

20060095735 - Systems and methods for increasing register addressing space in instruction-width limited processors: A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file, which are communicatively coupled to each other and arranged to accommodate shortened instruction words in multiple-issue processors. These components are arranged to permit...

20060095738 - Back-end renaming in a continual flow processor pipeline: Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by diverting instructions dependent on long-latency operations from a flow of the processor pipeline and re-introducing the instructions into the flow when the long-latency...

20060095737 - Methods and apparatus for pipelined processing: In a first aspect, a first method is provided for pipelined processing. The first method includes the steps of (1) receiving a first instruction in an in-order execution processing pipeline; and (2) receiving a second instruction in the in-order execution processing pipeline before execution of the first instruction completes. The...

20060095740 - Apparatus and methods for utilization of splittable execution units of a processor: A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of...

20060095739 - Simd processor executing min/max instructions: A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output...

20060095741 - Store instruction ordering for multi-core processor: A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue....

20060095742 - Method and apparatus for using predicates in a processing device: A method of controlling an operation of a processing device that comprises at least a first and second predicate execution registers comprises predicating a first instruction on the first predicate execution register. A second instruction is predicated on the second predicate execution register. The first predicate execution register is set...

20060095743 - Vliw processor with copy register file: A compute program is executed in a VLIW processor, which contains a plurality of functional units and a plurality of register files that are each coupled to a respective subset of the functional units. When a first instruction is executed that results in writing of a result to a register...

20060095744 - Memory control circuit and microprocessor system: A memory control circuit for providing a small-circuit-size memory control circuit capable of reducing a branch penalty during the execution of a branch instruction in a CPU. A branch-destination buffer caches a branch-destination instruction and a branch-destination-instruction address determined by a branch instruction executed by the CPU. When the CPU...

20060095745 - Processes, circuits, devices, and systems for branch prediction and other processor improvements: A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken target addresses for branch instructions, an execution pipeline (1740) with a branch execution circuit (1870), and storage elements (in 1860) and control logic (2350) operable to establish...

20060095746 - Branch predictor, processor and branch prediction method: A branch predictor configured to communicate information between first and second thread execution units includes a first branch prediction table configured to store branch prediction information of the first thread execution unit. A second branch prediction table is configured to store branch prediction information of the second thread execution unit....

20060095747 - Branch prediction mechanism including a branch prediction memory and a branch prediction cache: A data processing system 2 incorporating an instruction pipeline 14 and a prefetch unit 16 is provided with a branch prediction mechanism using both a branch prediction memory 20 storing 1-bit values indicating strongly taken or strongly not taken together with a branch prediction cache indicating for certain selected branch...

20060095749 - Branch prediction mechanism using a branch cache memory and an extended pattern cache: A branch prediction mechanism includes a branch prediction memory 18 and an extended pattern cache 24. The extended pattern cache 24 detects predetermined repeating patterns of branch outcomes and stores a plurality of compressed representations of these such that when they recur their termination can be predicted. This enables program...

20060095748 - Information processing apparatus, replacing method, and computer-readable recording medium on which a replacing program is recorded: The present invention relates to an information processing apparatus predicting a branch destination of a branch instruction using a branch history register to realize effective replacement by enabling an unnecessary entry to be selected as an entry, which is an object of replacement, without using new resources in a full-associative...

20060095750 - Processes, circuits, devices, and systems for branch prediction and other processor improvements: A processor (1700) for processing instructions has a pipeline (1710, 1736, 1740) including a fetch stage (1710) and an execute stage (1870), a first storing circuit (aGHR 2130) associated with said fetch stage (1710) and operable to store a history of actual branches, and a second storing circuit (wGHR 2140)...

20060095751 - Method and system for providing zero overhead looping using carry chain masking: A method and system for reducing overhead on a loop of a plurality of instructions is disclosed. The loop is performed a particular number of times. The method and system include a mask register and addition logic. The mask register provides a carry mask having a first value for the...

20060095752 - [method for return instruction identification and associated method for return target pointer prediction]: A method and device for return instruction prediction in microprocessors and digital signal processors. The method and device uses a return target buffer, in which a return instruction address table serves to store addresses of return instructions, and a return target stack is used to store target pointers of return...