Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 04/06

20060090060 - Method and arrangement for bringing together data on parallel data paths: A processor arrangement having a strip structure for parallel data processing is configured so that local data from the individual processing units or strips is brought together in a rapid manner. Input data, intermediate data and/or output data from various processing units are linked together in an operation which is...

20060090061 - Continual flow processor pipeline: Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by diverting instructions dependent on long-latency operations from a flow of the processor pipeline and re-introducing them into the flow when the long-latency operations...

20060090062 - Reconfigurable processor: A processor includes a reconfigurable field of data processing cells. A register is provided where the register has a data stream memory designed to store a data stream and/or parts thereon. The register may be a RAM PAE....

20060090063 - Method for executing structured symbolic machine code on a microprocessor: The invention describes a method for executing structured symbolic machine code on a microprocessor. Said structured symbolic machine code contains a set of one or more regions, where each of said regions contains symbolic machine code containing, in addition to the proper instructions, information about the symbolic variables, the symbolic...

20060075209 - Method and system of communicating between peer processors in soc environment: A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a second processor. The transferring of the data bypasses memory. The method further includes reading the transferred data directly from the at least one...

20060075210 - Sensor-network processors using event-driven architecture: Event-driven processor architectures are particularly suited for use in multiple sensor node networks and simulators of such networks. A first variation of the processor is particularly suited for use in a sensor node in a wireless sensor network. Through use of the event-driven architecture and special message and timing coprocessors,...

20060075211 - Method and device for data processing: Designing a coupling of a traditional processor, in particular a sequential processor, and a reconfigurable field of data processing units, in particular a runtime-reconfigurable field of data processing units is described....

20060075212 - Programmable logic analyzer data analyzing method: A programmable logic analyzer data analyzing method includes the step of controlling a control circuit to fetch waveform data from the test sample and to store fetched waveform data in a memory, the step of controlling the control circuit to transmit the waveform data from the memory to a computer...

20060075213 - Modular integration of an array processor within a system on chip: A systolic array processor is integrated within a system on chip (SoC) in a format that is compatible with existing and emerging SoC technologies. The systolic array processor may be implemented as a co-processor to a general-purpose digital signal processor or as a functional unit of a very long instruction...