Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 02/06

20060041736 - Superscalar risc instruction scheduling: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data...

20060036832 - Virtual computer system and firmware updating method in virtual computer system: A virtual computer system includes computers (1, 2) each having a first operating system executed when the virtual computer system is built and a second operating system of when each computer operates individually. Each of the computers (1, 2) comprises a booting unit (35A) for booting the first or second...

20060036833 - Processing activity masking in a data processing system: A data processing system is provided with mechanisms such that when a data value is stored within a data register, further data values are stored within one or more further registers such that the total number of signal transitions from high to low and from low to high does not...

20060036834 - Trace reuse: A trace management architecture to enable the reuse of uops within one or more repeated traces. More particularly, embodiments of the invention relate to a technique to prevent multiple accesses to various functional units within a trace management architecture by reusing traces or sequences of traces that are repeated during...

20060036835 - Dsp processor architecture with write datapath word conditioning and analysis: An improved digital signal processing (DSP) processor architecture is presented in which word conditioning (e.g., rounding, saturation, etc.) and analysis operations (e.g., block floating point analysis) are implemented in the write datapath to memory. By moving word conditioning operations from the critical path to the write datapath, the throughput of...

20060036836 - Block-based branch target buffer: The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction...

20060036837 - Prophet/critic hybrid predictor: A hybrid prophet/critic predictor includes a first branch predictor to provide a first branch prediction for a branch under prediction (BUP) based on a branch history of the BUP and/or a program counter, and also includes a second branch predictor to provide a second branch prediction for the BUP based...

20060031658 - Method, apparatus, and computer program product for dynamically tuning a data processing system by identifying and boosting holders of contentious locks: A method, apparatus, and computer program product are disclosed for a simultaneous multithreading (SMT) data processing system for modifying the processing of software threads that acquire a contentious software lock. The system includes a processor that is capable of concurrently executing multiple different threads on the processor. The processor is...

20060031659 - Multi-processor reconfigurable computing system: A reconfigurable multi-processor computing system including a plurality of configurable processing elements each having a plurality of integrated high-speed serial input/output ports. Interconnects link the plurality of processing elements, wherein at least one of the integrated high-speed serial input/output ports of each processing element is connected by at least one...

20060031660 - Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements: The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC...

20060031661 - Processor for executing instructions in units that are unrelated to the units in wihcih instructions are read,and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor: When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator...

20060031662 - Processor implementing conditional execution and including a serial queue: A processor is disclosed including trace and profile logic for gathering and producing data corresponding to events occurring during instruction execution. In one embodiment, the trace and profile logic includes a serial queue for serializing data corresponding to a plurality of “discontinuity instructions” grouped together for simultaneous execution. A “discontinuity...

20060031663 - Synchronizing execution using a single-treaded scripting model: Providing synchronization of data between application instances that execute script, and in preferred embodiments, without the use of synchronization primitives in the script and without the ability to reschedule events in at least one of the instances. Blocking code is provided in the application instances that is adapted for checking...

20060026387 - Method and system for recognizing instructions and instruction blocks in computer code: Various embodiments of the present invention are directed to efficient and robust methods by which virtual-machine monitors can recognize individual instructions and blocks of instructions within guest-operating-system code. In a described embodiment of the present invention, the guest operating system recognizes the instructions by recognizing an overall form, or pattern,...

20060026388 - Computer executing instructions having embedded synchronization points: A computer operable to execute instructions having embedded synchronization points includes a first program counter and a second program counter. The computer also includes a synchronization unit electrically coupled to the first and second program counters. When a synchronization point is reached, the synchronization unit is operable to stall the...

20060026389 - Method for providing scratch registers for use by a virtual-machine monitor: In one embodiment of the present invention, a virtual-machine monitor detects entry and exit from guest-operating system code, storing the values of a set of high-order floating point registers in memory on entry, and restoring the values of the set of high-order floating point registers on exit. The virtual-machine monitor...

20060026390 - Storing contexts for thread switching: An electronic device comprising decode logic that decodes instructions and a stack coupled to the decode logic. A group of instructions causes the decode logic to push onto the stack, after halting processing of a first thread at a switch point and prior to processing a second thread, a minimum...

20060026391 - Automatic operand load and store: A processor that comprises decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in...

20060026392 - Method and system of informing a micro-sequence of operand width: A method and system of informing a micro-sequence of operand width. At least some of the illustrative embodiments may be a method comprising fetching a first opcode, asserting a flag if the first opcode modifies an operand width of a subsequent opcode, fetching a second opcode, triggering a micro-sequence based...

20060026394 - Optimizing data manipulation in media processing applications: A system comprising a processor containing a first stack internal to a core of the processor, at least some data values in the first stack corresponding to values in a second stack external to the core. The system also comprises a memory coupled to the processor. In an iterative process,...

20060026393 - Splitting execution of instructions between hardware and software: In some embodiments, a processor comprises fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The instruction is executed partly in the integer pipeline according to software and partly in the hardware state machine....

20060026395 - Compare instruction: A processor executes an instruction that causes a comparison to be performed between contents of a first register and contents of a second register and between the contents of the first register and a predetermined value. The instruction is particularly useful for determining whether an attempted access (either a load...

20060026396 - Memory access instruction with optional error check: A processor executes a load (or store) instruction that permits optional error checking to be performed. Based on a control bit in the load instruction, the processor executes the load instruction by causing contents of a source register to be compared to a predetermined value. If the contents of the...

20060026397 - Pack instruction: A processor executes an instruction that causes a source data field from a first source register to be copied to a destination register at a programmable position within the destination register. The instruction is particularly useful for generating media-based bitstreams (e.g., audio, video). In some embodiments, a system (e.g., a...

20060026398 - Unpack instruction: A processor executes an instruction that causes a source data field from a programmable position within a first source register to be copied to a destination register. The instruction is particularly useful for generating media-based bitstreams (e.g., audio, video). In some embodiments, a system (e.g., a communication device such as...

20060026399 - Information processing unit and store instruction control method: In order to increase the operation efficiency of the operation register for holding store data when executing store instruction to store data in a predetermined store area on the main memory or the cache memory, in the present invention, an instruction processing section is adapted so as, when an operation...

20060026400 - Automatic operand load, modify and store: A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in...

20060026403 - Compare instruction: A processor comprising fetch logic adapted to fetch instructions from memory and decode logic coupled to the fetch logic and adapted to decode the fetched instructions. If a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or...

20060026402 - Method and system of using a \"wide\" opcode other than prefix: A method and related system of using a “WIDE” opcode as other than a prefix. At least some of the illustrative embodiments may be a method comprising fetching an opcode (the opcode used in at least some circumstances as a prefix to other opcodes), and determining whether the opcode is...

20060026401 - Method and system to disable the \"wide\" prefix: A method and related system to disable the “WIDE” prefix. At least some of the illustrative embodiments may be a method comprising disabling an ability of an opcode to act as a prefix for other opcodes....

20060026405 - Identifying code for compilation: A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further comprises decode logic coupled to the fetch logic and adapted to process the set of instructions, and a clock coupled to the decode logic. When processed,...

20060026404 - Method and system to construct a data-flow analyzer for a bytecode verfier: The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic...

20060026407 - Delegating tasks between multiple processor cores: An electronic device comprising a first processor and a second processor, the second processor coupled to the first processor and adapted to receive an address from the first processor, to pause execution of a first thread at a switch point, and to use the address to retrieve and execute a...

20060026406 - Unprivileged context management: Embodiments of the present invention provide full benefit of the cover instruction provided by the Intel IA-64 architecture to code running at less than highest privilege level. In one embodiment of the present invention, prior to execution of a cover instruction by non-privileged code, the code obtains and stores the...

20060026409 - Branch instruction control apparatus and control method: The branch instruction control apparatus of the present invention is a control apparatus in which a plurality of entries in which data required for the implementation control of the branch instructions is stored in order of decoding successively from the top entry, and said apparatus comprises a mechanism which, when...

20060026408 - Run-time updating of prediction hint instructions: The present invention provides a system and method for runtime updating of hints in program instructions. The invention also provides for programs of instructions that include hint performance data. Also, the invention provides an instruction cache that modifies hints and writes them back. As runtime hint updates are stored in...

20060026410 - Branch predicting apparatus and branch predicting method: A return address in response to a return instruction corresponding to a call instruction is stored in a return address stack when a branch history detects presence of the call instruction. When the branch history detects the presence of the return instruction before a branch reservation station completes executing the...

20060026411 - Processor system and thread switching control method: The present invention relates to a processor system. The processor system is made up of a multithread control unit for selectively making switching among said threads to be executed in an arithmetic unit, a loop predicting unit for predicting a loop of an instruction string on the basis of a...

20060026412 - Removing local ram size limitations when executing software code: An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second...

20060026413 - Pattern matching architecture: A pattern matching unit includes a selection unit to divide an input datum and one or more reference templates into input bit-fields corresponding reference bit-fields, respectively. The number of bits in the input and reference bit-fields is programmable. A distance unit is also included to determine one or more distance...