Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 01/06

20060020767 - Data processing system and method for assigning objects to processing units: A data processing system has a program module for determining a re-distribution of objects, such as database tables, over processing units of a cluster of processing units, such as in a blade computing environment. An estimate of the required duration for applying the re-distribution is calculated in order to facilitate...

20060020768 - Vector processing apparatus, information processing apparatus, and vector processing method: A vector processing apparatus includes a plurality of vector pipeline computing units and an instruction control unit. The vector pipeline computing units operate in accordance with operation control information for instructing start and execution of processing. The instruction control unit generates operation control information and outputs the operation control information...

20060020769 - Allocating resources to partitions in a partitionable computer: Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies...

20060020770 - Processing unit for broadcast parallel processing: A processing unit includes a control processor and a plurality of element processors having register files. At least two of the element processors pre-receive different parameters, store the parameter data in the register files, receive the same memory address and the same instruction broadcast by the control processor, read the...

20060020771 - Parallel computer having a hierarchy structure: In a multiprocessor system of a hierarchy configuration as a parallel computer of a common-bus structure, a processing unit (120) in an intermediate stage has a processor (123) having a programmable function that is equal to a normal processor, an instruction memory (125), and a data memory (127). The processing...

20060020772 - Method and apparatus for compressing and decompressing instructions in a computer system: The apparatus and methods improve performance in a computer system by compressing a plurality of instructions having the same function with consecutively addressed operands and decompressing the compressed instruction by replicating the instruction with incremented operands....

20060020773 - System and method for register renaming: A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A...

20060020774 - Reconfigurable computing architecture for space applications: A reconfigurable computer includes a reconfigurable processing element configured to process raw payload data in accordance with a configuration that is applied to the reconfigurable processing element. The reconfigurable computer further includes a multi-port communication device comprising a first port at which at least a portion of the raw payload...

20060020775 - Multi-version register file for multithreading processors with live-in precomputation: Disclosed are selected embodiments of a processor that may include a plurality of thread units and a register file architecture to support speculative multithreading. For at least one embodiment, live-in values for a speculative thread are computed via execution of a precomputation slice and are stored in a validation buffer...

20060020776 - Multithread processor and register control method: The present invention relates to a multithread processor, and this multithread processor comprises a plurality of register windows each provided for each of threads and capable of storing data to be used for instruction processing in an arithmetic unit, a work register capable of mutually transferring data with respect to...

20060020777 - Data processing apparatus: In a data processing apparatus using a register window method performing data transmission from a master register to a work register during an exception handling, detecting a trap, discriminating whether or not a data transmission is required for the global registers by the trap, and transmitting data from the master...

20060015701 - Arithmetic node including general digital signal processing functions for an adaptive computing machine: An apparatus for processing operations in an adaptive computing environment is provided. The adaptive computing environment including at least one processing node. A node includes a memory configured to receive and store data. The data is received from a programmable interconnection network and stored. The node also includes an execution...

20060015702 - Method and apparatus for simd complex arithmetic: Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for...

20060015703 - Programmable processor architecture: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than...

20060015704 - Operation apparatus and instruction code executing method: An operation apparatus includes signal lines, a decoder connected with the signal lines and configured to sequentially decode first and second instruction codes on the signal lines, an instruction executing section configured to execute operation processing based on each of the decoding results of the first and second instruction codes...

20060015705 - Arrangement, system and method for vector permutation in single-instruction multiple-data mircoprocessors: A vector permutation system (100) for a single-instruction multiple-data microprocessor has a set of vector registers (110) which feed vectors to permutation logic (120) and then to a negate block (130) where they are permuted and selectively negated according to control parameters received from a selected one of a set...

20060015706 - Tlb correlated branch predictor and method for use thereof: Embodiments of the present invention relate to an apparatus and method to enable efficient branch prediction in super-scalar and other branching-enabled processors. In accordance with an embodiment of the present invention, a branch predictor may include a branch prediction circuit to predict a branch outcome in an executing instruction in...

20060015708 - Microprocessor with branch target determination in decoded microinstruction code sequence: In a microprocessor, customer code routines are decoded from ISA instructions into microinstructions and stored in a customer code store (CCS) for later, repeated execution. Branch target addresses in the ISA code, which use an ISA memory addressing format, are replaced with CCS branch target addresses in the decoded, stored...

20060015707 - Microprocessor with customer code store: A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA level code can specify a routine for storage into...

20060015709 - Reconfigurable state machine architecture and related method of execution: An architecture for a state machine (10) with a number of states of the machine, comprises a memory (14) having a set of addresses. The memory (14) is arranged to store at each of said addresses in the set the complete description of a respective one of said number of...

20060010305 - Processor system that controls data transfer between processor and coprocessor: A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit...

20060010306 - Reconfigurable operation apparatus: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs...

20060010307 - Latching processor state information: A data processing apparatus and method is disclosed. The data processing apparatus comprises a processor unit operable to execute data processing instructions, a processor state register within the processor unit operable to store processor state information associated with a data processing instruction being executed by the processor unit and a...

20060010308 - Microprocessor: A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to...

20060010309 - Selective execution of deferred instructions in a processor that supports speculative execution: One embodiment of the present invention provides a system which selectively executes deferred instructions following a return of a long-latency operation in a processor that supports speculative-execution. During normal-execution mode, the processor issues instructions for execution in program order. When the processor encounters a long-latency operation, such as a load...

20060010310 - Apparatus and method for handling btac branches that wrap across instruction cache lines: A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in...

20060010311 - Methods and apparatus for updating of a branch history table: Methods and apparatus are provided for enhanced instruction handling in processing environments. If branch misprediction occurs during instruction processing, a branch history table may be updated based upon the number of instructions to be fetched. The branch history table may be updated in accordance with a first mode if at...

20060004985 - Vector simd processor: A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction...

20060004986 - Data processing apparatus address range dependent parallelization of instructions: A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies....

20060004987 - System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor...

20060004988 - Single bit control of threads in a multithreaded multicore processor: A method and mechanism for controlling threads in a multithreaded multicore processor. A processor includes multiple cores, each of which are capable of executing multiple threads. A control register which is shared by each of the cores is utilized to control the status of the threads in the processing system....

20060004989 - Mechanism for selecting instructions for execution in a multithreaded processor: In one embodiment, a multithreaded processor includes a plurality of buffers, each configured to store instructions corresponding to a respective thread. The multithreaded processor also includes a pick unit coupled to the plurality of buffers. The pick unit may pick from at least one of the buffers in a given...

20060004990 - Distributed processing in a multiple processing unit environment: Method and apparatus for performing distributed processing in a multi-processing unit environment. A first processing unit modifies a complex operation to provide an operational request packet comprising a corresponding simplex operation and remainder. The packet is communicated to a second processing unit which processes the packet to arrive at a...

20060004994 - Processor: A processor executes a predetermined operation process by switching a connection structure between a plurality of arithmetic and logic unit modules. Each of the arithmetic and logic unit modules includes a plurality of arithmetic and logic units. The arithmetic and logic unit modules include a first arithmetic and logic unit...

20060004993 - Processor and pipeline reconfiguration control method: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it...

20060004992 - Reconfigurable circuit in which time division multiple processing is possible: The reconfigurable circuit of the present invention in which time division multiple processing is possible has a pipeline structure with the number of stages of an integral multiple of a given number, and comprises a plurality of processor elements having a processing unit whose configuration is variable according to first...

20060004991 - Semiconductor device: A semiconductor device includes a configuration memory for storing configuration data, an arithmetic unit whose circuit configuration can be reconfigured in accordance with the configuration data, and a fixed value memory for storing fixed value data to be supplied to the arithmetic unit. Since the configuration data and fixed value...

20060004995 - Apparatus and method for fine-grained multithreading in a multipipelined processor core: An apparatus and method for fine-grained multithreading in a multipipelined processor core. According to one embodiment, a processor may include instruction fetch logic configured to assign a given one of a plurality of threads to a corresponding one of a plurality of thread groups, where each of the plurality of...

20060004996 - Macroscalar processor architecture: A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an...

20060004997 - Method and apparatus for computing: A general purpose computing system comprises a novel apparatus and method for data processing. The computing system design of one application of the present invention includes an instruction pipe having a decompression circuit, a reprogrammable logic unit and a data bus. Instructions and data may be accessed via a shared...

20060004998 - Method and apparatus for speculative execution of uncontended lock instructions: A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively...

20060004999 - Operation apparatus and operation apparatus control method: An operation apparatus includes a plurality of operation device units; a configuration memory storing setting information provided for each predetermined state of the plurality of operation device units; and a sequencer controlling the plurality of operation device units by outputting transition destination addresses designating relevant information from configuration information comprising...