|Electrical computers and digital processing systems: memory patents - Monitor Patents|
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Electrical computers and digital processing systems: memoryBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 06/11/2015 > patent applications in patent subcategories.
06/04/2015 > patent applications in patent subcategories.
05/28/2015 > 57 patent applications in 26 patent subcategories.
20150149687 - Ordered memory pages transmission in virtual machine live migration: Systems and methods for virtual machine live migration. An example method may comprise: identifying, by a first computer system executing a virtual machine undergoing live migration to a second computer system, a plurality of stable memory pages comprised by an execution state of the virtual machine, wherein the plurality of... Agent: Red Hat Israel, Ltd.
20150149688 - Electronic device and method of managing memory of electronic device: A method of managing a memory by an electronic device is provided. The method includes configuring a swap data amount per unit time, identifying an actual use amount of swap data, and comparing the identified actual use amount of the swap data with the configured swap data amount per unit... Agent:
20150149690 - Recording device, access device, recording system, and recording method: A recording device operates in accordance with an instruction from an access device. The recording device comprising a nonvolatile memory that stores data, a communication unit that receives an instruction issued by the access device, and a memory controller that controls the nonvolatile memory. When a recording instruction for recording... Agent:
20150149689 - Systems and methods for revising permanent rom-based programming: An application program stored in a ROM includes a function lookup data structure in which functions called by the application program have identifiers and memory addresses at which the function is located and can be executed. Upon startup, the function lookup data structure is copied to a RAM as a... Agent:
20150149694 - Adaptive context disbursement for improved performance in non-volatile memory systems: A controller circuit for a non-volatile memory of one or more memory circuits is described. The controller is connectable by a port with the memory circuits through a bus structure and can operate the memory circuits according to one or more threads. The controller includes a command processing section to... Agent: Sandisk Technologies Inc.
20150149699 - Adaptive erase of a storage device: The various implementations described herein include systems, methods and/or devices used to enable adaptive erasure in a storage device. The method includes performing a plurality of memory operations including read operations and respective erase operations on portions of one or more non-volatile memory devices specified by the read operations and... Agent: Sandisk EnterpriseIPLLC
20150149703 - Apparatuses for securing program code stored in a non-volatile memory: An embodiment of an apparatus for securing program code stored in a non-volatile memory is introduced. A non-volatile memory contains a first region and a second region. Two NVMMCS (non-volatile memory management controllers respectively coupled to the two regions. A programming command-and-address decoder is coupled to the NVMMCS. The programming... Agent: Nuvoton Technology Corporation
20150149696 - Auto resume of irregular erase stoppage of a memory sector: Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory.... Agent: Spansion LLC
20150149708 - B-file abstraction for efficiently archiving self-expiring data: Systems and methods are provided for data processing and storage management. In an illustrative implementation an exemplary computing environment comprises at least one data store, a data processing and storage management engine (B-File engine) and at least one instruction set to instruct the B-File engine to process and/or store data... Agent: Microsoft Technology Licensing, LLC
20150149711 - Cache decice and memory system: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile... Agent:
20150149700 - Dimm device controller supervisor: The various implementations described herein include systems, methods and/or devices used to enable performing supervisory functions for a dual in-line memory module (DIMM), at a controller in the DIMM. The method includes upon power-up, determining a power supply voltage provided to the DIMM. In accordance with a determination that power... Agent: Sandisk EnterpriseIPLLC
20150149691 - Directly coupled computing, storage and network elements with local intelligence: An apparatus that collapses computing, storage and networking elements into a tightly coupled, deeply vertically integrated highly scalable system that additionally provides augmented intelligence within each of the computing, storage and networking elements. A method to collapse computing, storage and networking elements while augmenting each of their intelligence. A system... Agent:
20150149692 - Efficient reuse of segments in nonoverwrite storage systems: A non-overwrite storage system, such as a log-structured file system, that includes a non-volatile storage having multiple storage segments, a volatile storage having an unsafe free segments list (UFSL), and a controller for managing storage resources of the non-volatile storage. The controller can be configured to copy page data from... Agent: Apple Inc.
20150149698 - Eliminating or reducing programming errors when programming flash memory cells: Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper... Agent: Lsi Corporation
20150149709 - Hybrid storage: Example control methods of hybrid storage are provided, which are applied to each HDD-type storage device and each SSD-type storage device in a storage system having one or more HDD-type storage devices and one or more SSD-type storage devices. Each HDD-type storage device in the storage system is connected to... Agent:
20150149705 - Information-processing system: Information-processing system including a first information-processing unit, and a second information-processing unit, when the concept of wear leveling is applied to distribution of workloads to the respective information-processing units, the lives of the nonvolatile memories of the first information-processing unit and the second information-processing unit come to ends at almost... Agent: Hitachi, Ltd.
20150149702 - Method for data management and memory storage device and memory control circuit unit: A method for data management and a memory storage device and a memory control circuit unit thereof. The method includes: configuring a NVRAM and a VRAM; storing first data which includes writing data from a host system in the NVRAM; storing second data read from a rewritable non-volatile memory module... Agent: Phison Electronics Corp.
20150149707 - Microcontroller with integrated interface enabling reading data randomly from serial flash memory: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory.... Agent:
20150149710 - Nonvolatile memory device and sub-block managing method thereof: A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the... Agent:
20150149695 - System and method for computing message digests: A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message... Agent:
20150149706 - System and method for efficient flash translation layer: A method of maintaining and updating a logical-to-physical (LtoP) table in a storage device including a processor, a volatile memory, and a non-volatile memory, the storage device being in communication with a host, the method including receiving, by the processor, data for storing at a physical address in the non-volatile... Agent:
20150149697 - System and method for supporting atomic writes in a flash translation layer: A method of maintaining and updating a logical-to-physical (LtoP) table in a storage device including a processor, a volatile memory, and a non-volatile memory, the storage device being in communication with a host utilizing atomic writes, the method including receiving, by the processor, data for storing at a plurality of... Agent: Nxgn Data, Inc.
20150149693 - Targeted copy of data relocation: In a nonvolatile memory array that has a binary cache formed of SLC blocks and a main memory formed of MLC blocks, corrupted data along an MLC word line is corrected and relocated, along with any other data along the MLC word line, to binary cache, before it becomes uncorrectable.... Agent: Sandisk Technologies Inc.
20150149701 - Time estimating method, memory storage device, and memory controlling circuit unit: A time estimating method, a memory storage device, and a memory controlling circuit unit are provided for a rewritable non-volatile memory module having memory cells. The method includes: writing first data into first memory cells of the memory cells; reading the first memory cells according to a reading voltage, so... Agent: Phison Electronics Corp.
20150149704 - Transaction private log buffering for high performance of transaction processing: For each data change occurring transaction created as part of a write operation initiated for one or more tables in a main-memory-based DBMS, a transaction log entry can be written to a private log buffer corresponding to the transaction. All transaction log entries in the private log buffer can be... Agent:
20150149712 - Translation layer in a solid state storage device: Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable,... Agent: Micron Technology, Inc.
20150149713 - Memory interface design: An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and... Agent: Nvidia Corporation
20150149714 - Constraining prefetch requests to a processor socket: In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be... Agent:
20150149715 - Nonvolatile random access memory use: For nonvolatile random access memory (NVRAM) use, a query module identifies persistent data on a NVRAM in response to waking the NVRAM. A management module makes available the persistent data for use.... Agent: Lenovo (singapore) Pte, Ltd.
20150149716 - Write and read collision avoidance in single port memory devices: A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation... Agent:
20150149718 - A lower energy consumption and high speed computer system and a marching main memory adapted for the computer system, without the memory bottleneck: A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units... Agent:
20150149717 - Partial access mode for dynamic random access memory: Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation in the retention time among memory cells. Although active power increases by a factor of 2N, the refresh time increases by... Agent: Elpida Memory, Inc.
20150149719 - Flexible data storage system: Methods and systems for managing and locating available storage space in a system comprising data files stored in a plurality of storage devices and configured in accordance with various data storage schemes (mirroring, striping and parity-striping). A mapping table associated with each of the plurality of storage devices is used... Agent:
20150149720 - Control method, control device, and recording medium: A non-transitory computer-readable recording medium has stored therein a program that causes a computer to execute a control process. The control process includes: receiving an access request for a recording device that stores data; determining whether or not index information corresponding to the access request, which is received at the... Agent: Fujitsu Limited
20150149722 - Delaying cache data array updates: Systems, methods, and apparatuses for reducing writes to the data array of a cache. A cache hierarchy includes one or more L1 caches and a L2 cache inclusive of the L2 cache(s). When a request from the L1 cache misses in the L2 cache, the L2 cache sends a fill... Agent: Apple Inc.
20150149721 - Selective victimization in a multi-level cache hierarchy: Systems, methods, and apparatuses for implementing selective victimization to reduce power and utilized bandwidth in a multi-level cache hierarchy. Each set of an upper-level cache includes a counter that keeps track of the number of times the set was accessed. These counters are periodically decremented by another counter that tracks... Agent: Apple Inc.
20150149724 - Arithmetic processing device, arithmetic processing system, and method for controlling arithmetic processing device: An arithmetic processing device includes: a arithmetic cores, wherein the arithmetic core comprises: an instruction controller configured to request processing corresponding to an instruction; a memory configured to store lock information indicating that a locking target address is locked, the locking target address, and priority information of the instruction; and... Agent: Fujitsu Limited
20150149723 - High-performance instruction cache system and method: A method is provided for facilitating operation of a processor core coupled to a first memory containing executable instructions, a second memory faster than the first memory and a third memory faster than the second memory. The method includes examining instructions being filled from the second memory to the third... Agent:
20150149725 - Multi-threaded system for performing atomic binary translations: A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of... Agent:
20150149726 - Data distribution device and data distribution method: A data distribution device includes: a memory configured to store cache data of data to be distributed; and a processor coupled to the memory and configured to: read the cache data from the memory in accordance with a request message received from other devices to distribute the cache data to... Agent: Fujitsu Limited
20150149727 - Write and read collision avoidance in single port memory devices: A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation... Agent: International Business Machines Corporation
20150149728 - Semiconductor device and operating method thereof: A semiconductor device may include a first address cache configured to store a physical address of a semiconductor memory device and a write count associated with the physical address, an address monitor configured to update the physical address and the write count in the first address cache based on a... Agent:
20150149729 - Cache migration: Exemplary methods, apparatuses, and systems determine that a cache is to be migrated from a first storage device to a second storage device. The cache includes cache entries organized in a first list of cache entries and a second list of cache entries. Only a portion of all cache entries... Agent: Vmware, Inc.
20150149730 - Cache migration: Exemplary methods, apparatuses, and systems determine that a cache is to be migrated from a first storage device to a second storage device. Each cache entry within the cache includes a first indicator to indicate whether or not the cache entry has long-term utility. Only a portion of all cache... Agent: Vmware, Inc.
20150149731 - I/o controller and method for operating an i/o controller: An I/O controller, coupled to a processing unit and to a memory, includes an I/O link interface configured to receive data packets having virtual addresses; an address translation unit having an address translator to translate received virtual addresses into real addresses by translation control entries and a cache allocated to... Agent:
20150149732 - System and methods for cpu copy protection of a computing device: The present disclosure relates to techniques for system and methods for software-based management of protected data-blocks insertion into the memory cache mechanism of a computerized device. In particular the disclosure relates to preventing protected data blocks from being altered and evicted from the CPU cache coupled with buffered software execution.... Agent:
20150149733 - Supporting speculative modification in a data cache: Method and system for supporting speculative modification in a data cache are provided and described. In one embodiment, a speculative cache buffer includes a plurality of cache lines and a plurality of state indicators. At least one of the cache lines is operable to receive an evicted cache line from... Agent:
20150149734 - Combined transparent/non-transparent cache: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address.... Agent:
20150149736 - Fast restart of applications using shared memory: Technologies are described for restarting an application while maintaining data in memory (e.g., using shared memory). For example, shared memory can be associated with an application. The shared memory can also be associated with a holder process to maintain the shared memory from the time the application stops to the... Agent:
20150149735 - Memory system: Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum... Agent:
20150149737 - Method or system for access to shared resource: Methods and/or systems are provided that may be utilized to read from or write to a resource, such as a shared memory, for example.... Agent: Yahoo! Inc.
20150149738 - Continuous page read for memory: Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.... Agent:
20150149739 - Method of storing data in distributed manner based on technique of predicting data compression ratio, and storage device and system using same: A method of storing data in a distributed manner based on data compression ratio prediction, and a mass storage device and system using the method are disclosed. The device includes a compression ratio predicting unit, a compressing unit, and a control unit. When an address and first unit sized data... Agent: Research & Business Foundation Sungkyunkwan University
20150149740 - Data storage device and data processing system including the same: A data processing system includes a data storage device including memory cells, which are erased to an erasure state and programmed to program states to store data, and a host device suitable for accessing the data, wherein the data storage device programs a first memory cell to a first state... Agent: Sk Hynix Inc.
20150149741 - Storage system and control method thereof: A storage system has a plurality of physical blocks, a buffer and a controller. In response to an unmap command received from an operating machine, the controller moves a mapping between a physical block and a logical block of the storage system to a buffer to prepare a deallocation procedure.... Agent:
20150149742 - Memory unit and method: A memory unit and method are disclosed. The memory unit comprises: at least one controller interfaced with at least one corresponding persistent memory device operable to store files in accordance with a file system; and a file mapping unit operable, in response to a virtual file access request from a... Agent: Swarm64 As
20150149743 - Management method of virtual-to-physical address translation system using part of bits of virtual address as index: A management method of a virtual-to-physical address translation system includes the following steps: providing a first storage space, wherein the first storage space includes a plurality of buffer entries; providing a second storage space, wherein the second storage space includes a plurality of translation entries, and the translation entries correspond... Agent:05/21/2015 > 54 patent applications in 24 patent subcategories.
20150143019 - Inexpensive solid-state storage through write throttling: Many of the benefits of solid-state-based storage devices can be obtained, while minimizing the costs associated therewith, by write-throttling solid-state storage media in accordance with empirically derived capabilities. Untested solid-state storage media can be obtained inexpensively due to the lack of waste that is otherwise been inherent in the testing... Agent: Microsoft Corporation
20150143020 - Low latency memory access control for non-volatile memories: A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripheral banklet circuitry, coupled... Agent: International Business Machines Corporation
20150143033 - Controlling write speed of nonvolatile memory device: A system comprises a nonvolatile memory device having multiple download speeds, and a computing device connected to the nonvolatile memory device and configured to determine a download environment of the nonvolatile memory device and to set the nonvolatile memory device to one of the download speeds according to the determined... Agent:
20150143028 - Data storage apparatus and operating method thereof: A data storage apparatus includes a translation section suitable for performing a translation operation for translating first address mapping data to second address mapping data, and an operation memory device suitable for storing the second address mapping data.... Agent: Sk Hynix Inc.
20150143023 - Detecting access sequences for data compression on non-volatile memory devices: Techniques are presented to allow non-volatile memory system to operate more efficiently by determining ranges of logical addresses that a host typically accesses as together. For example, the system's controller can determine that the host always, or most always, writes or reads a contiguous set of logical addresses as a... Agent: Sandisk Technologies Inc.
20150143029 - Dynamic logical groups for mapping flash memory: A memory system or flash card may include a controller that indexes a global address table (GAT) with a single data structure that addresses both large and small chunks of data. The GAT may include both large logical groups and smaller logical groups for optimizing write amplification. The addressing space... Agent: Sandisk Technologies Inc.
20150143021 - Equalizing wear on storage devices through file system controls: Data stored in file blocks and storage blocks of a storage device may be tracked by the file system. The file system may track a number of writes performed to each file block and storage block. The file system may also track a state of each storage block. The file... Agent: Unisys Corporation
20150143036 - Exporting computational capabilities into a block-oriented disk memory: A memory controller is provided that includes a host system interface that receives requests from applications and sends read or write commands to a disk for data retrieval. A threadlet core provides threadlets to the host system interface that enable the host system interface to use a logical bit address... Agent:
20150143034 - Hybrid memory architectures: Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.... Agent:
20150143040 - Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same: A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More... Agent:
20150143031 - Method for writing data into storage device and storage device: A storage device includes a buffer memory and a flash memory, which can be connected with the host computer communicably. A method for writing data into the storage device includes: receiving a first write command from the host, the first write command including the data to be written, the address... Agent:
20150143024 - Redundant array of independent modules: A Redundant Array of Independent Modules (RAIM) system has the similar function and architecture as Redundant Array of Independent Disk (RAID) system. It includes a RAID controller coupled to send and receive information to and from a host through an interface and a plurality of modules coupled to the RAID... Agent: Sage Microelectronics Corp.
20150143022 - Removable memory card discrimination systems and methods: Removable memory card discrimination systems and methods are disclosed. In particular, exemplary embodiments discriminate between secure digital (SD) cards and other removable memory cards that comply with the SD form factor, but support the Universal Flash Storage (UFS) protocol. That is, a host may have a receptacle that supports the... Agent: Qualcomm Incorporated
20150143039 - Restoring virtualized gcu state information: Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, initial state information is stored which identifies an actual state of a garbage collection unit (GCU) of a memory during a normal operational mode. During a restoration mode after... Agent: Seagate Technology LLC
20150143027 - Solid state drive with raid functions: A single solid state drive (SSD) includes an SSD controller coupled to send and receive information to and from a host through an interface. The SSD controller includes an embedded RAID controller and a plurality of non-volatile memory modules (NVMs) coupled to the SSD controller. The SSD controller causes storage... Agent: Sage Microelectronics Corp.
20150143032 - Storage medium storing control program, method of controlling information processing device, information processing system, and information processing device: According to an embodiment, when data read from a first storage unit which is a backup source is not identical with data indicated by a first function, the read data is written to a second storage unit which is a backup destination. When the data read from the first storage... Agent: Kabushiki Kaisha Toshiba
20150143038 - Storage processor managing solid state disk array: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing stripping across the SSDs.... Agent:
20150143037 - System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class: An apparatus, computer program product, and associated method/processing unit are provided for utilizing a memory subsystem including a first memory of a first memory class, and a second memory of a second memory class communicatively coupled to the first memory. In operation, data is fetched using a time between a... Agent:
20150143026 - Temperature based flash memory system maintenance: A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations... Agent: Sandisk Technologies Inc.
20150143025 - Update block programming order: Certain MLC blocks that tend to be reclaimed before they are full may be programmed according to a programming scheme that programs lower pages first and programs upper pages later. This results in more lower page programming than upper page programming on average. Lower page programming is generally significantly faster... Agent: Sandisk Technologies Inc.
20150143030 - Update block programming order: Certain MLC blocks that tend to be reclaimed before they are full may be programmed according to a programming scheme that programs lower pages first and programs upper pages later. This results in more lower page programming than upper page programming on average. Lower page programming is generally significantly faster... Agent: Sandisk Technologies Inc.
20150143035 - User device having a host flash translation layer (ftl), a method for transferring an erase count thereof, a method for transferring reprogram information thereof, and a method for transferring a page offset of an open block thereof: A user device includes a storage device including a flash memory; and a host connected to the storage device via an interface and adapted to transmit data to the storage device. The host provides the storage device with erase count information of the flash memory using a host flash translation... Agent:
20150143041 - Storage control apparatus and control method: A storage control apparatus includes a plurality of control units that each controls access to one or more first storage areas among a plurality of first storage areas allocated to one or more storage media, and a storage unit configured to store information, for each of the control units, on... Agent:
20150143042 - Disk storage apparatus and data storage method: According to one embodiment, a disk storage apparatus includes a disk, a detector, and a controller. The disk includes a first recording area for recording with a first track density, and a second recording area for recording with a second track density lower than the first track density. The detector... Agent: Kabushiki Kaisha Toshiba
20150143043 - Decentralized online cache management for digital content: A first cache is provided to cache a first portion of a first block of digital content received over a network connection shared between a first user associated with the first cache and at least one second user. The first cache caches the first portion in response to the first... Agent: Alcatel-lucent Usa Inc.
20150143044 - Mechanism for sharing private caches in a soc: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity,... Agent: Apple Inc.
20150143045 - Cache control apparatus and method: Provided are a cache control apparatus and method for reducing a miss penalty. The cache control apparatus includes a first level cache configured to store data in a memory, a second level cache connected to the first level cache, and configured to be accessed by a processor when the first... Agent: Electronics And Telecommunications Research Institute
20150143048 - Multi-cpu system and computing system having the same: A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller... Agent:
20150143047 - Systems and methods for direct data access in multi-level cache memory hierarchies: Methods and systems for in direct data access in, e.g., multi-level cache memory systems are described. A cache memory system includes a cache location buffer configured to store cache location entries, wherein each cache location entry includes an address tag and a cache location table which are associated with a... Agent:
20150143046 - Systems and methods for reducing first level cache energy by eliminating cache address tags: Methods and systems which, for example, reduce energy usage in cache memories are described. Cache location information regarding the location of cachelines which are stored in a tracked portion of a memory hierarchy is stored in a cache location table. Address tags are stored with corresponding location information in the... Agent:
20150143049 - Cache control apparatus and method: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI... Agent: Electronics And Telecommunications Research Institute
20150143050 - Reuse of directory entries for holding state information: The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or... Agent: Netspeed Systems
20150143051 - Providing common caching agent for core and integrated input/output (io) module: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations... Agent:
20150143052 - Managing faulty memory pages in a computing system: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number... Agent: International Business Machines Corporation
20150143054 - Managing faulty memory pages in a computing system: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number... Agent:
20150143053 - System and method for improved storage request handling in host-side caches: A system and method of improved storage request handling in host-side caches includes a host-side cache with a cache controller, a plurality of request queues, and a cache memory. The cache controller is configured to receive a storage request, assign a priority to the storage request based on a queuing... Agent: Netapp, Inc.
20150143055 - Virtual machine backup: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines, a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag and a memory... Agent:
20150143056 - Dynamic write priority based on virtual write queue high water mark: A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback... Agent: International Business Machines Corporation
20150143057 - Adaptive data prefetching: A system and method for adaptive data prefetching in a processor enables adaptive modification of parameters associated with a prefetch operation. A stride pattern in successive addresses of a memory operation may be detected, including determining a stride length (L). Prefetching of memory operations may be based on a prefetch... Agent:
20150143058 - System, method, and computer program product for utilizing a data pointer table pre-fetcher: A system, method, and computer program product are provided for utilizing a data pointer table pre-fetcher. In use, an assembly of a data pointer table within a main memory is identified. Additionally, the data pointer table is pre-fetched from the main memory. Further, data is sampled from the pre-fetched data... Agent: Nvidia Corporation
20150143059 - Dynamic write priority based on virtual write queue high water mark: A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback... Agent: International Business Machines Corporation
20150143060 - On-chip memory (ocm) physical bank parallelism: According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory... Agent:
20150143062 - Controller, storage device, and control method: A controller of an embodiment includes: an interface unit configured to be connected to a storage unit and configured to execute a command performing one or more basic operations for the storage unit in a predetermined order; and a control unit configured to hold, for each category to which the... Agent: Kabushiki Kaisha Toshiba
20150143061 - Partitioned register file: A system includes a processing unit and a register file. The register file includes at least a first memory structure and a second memory structure. The first memory structure has a lower access energy than the second memory structure. The processing unit is configured to address the register file using... Agent: Nvidia Corporation
20150143066 - Data configuration and migration in a cluster system: A cluster system includes a plurality of computing nodes connected to a network. Each node is configured to access its own storage device, and to send and receive input/output (I/O) operations associated with its own storage device. Further, each node of the plurality of nodes may be configured to have... Agent:
20150143065 - Data processing method and apparatus, and shared storage device: A data processing method and apparatus, and a shared storage device, where the method includes receiving, by a shared storage device, a copy-on-write request sent by another storage device, where the copy-on-write request includes data on which copy-on-write is to be performed and a logical unit identifier and snapshot time... Agent:
20150143063 - Successive data fingerprinting for copy accuracy assurance: Systems and methods for checking data integrity of a data object copied between storage pools in a storage system by comparing data samples copied from data objects. A series of successive copy operations are scheduled over time for copying a data object from a source data store to a target... Agent:
20150143064 - Test-and-development workflow automation: Computerized methods and systems for automating a process of creating and mounting live copies of data to applications in accordance with workflows that specify procedures for creating and mounting the live copies of data to the applications. The methods and systems comprise executing at least one workflow associated with a... Agent:
20150143067 - Method and system for qualification of an element: A method and a system for creating and qualifying one or more elements, such as multimedia content or, more generally, a performance by an author. The invention more particularly aims at associating a qualification level with an element so that a consultation work can be available, as regards relevance, robustness,... Agent: Gerwin Sarl
20150143068 - Data management with modular erase in a data storage system: A system and method of data management with modular erase in a data storage system with a memory array having an erase block and a target block with the target block in a logical unit separate from the erase block including: performing an erase operation on the erase block, the... Agent: Sandisk EnterpriseIPLLC
20150143069 - Managing data delivery: Methods and systems for managing data and/or operations on data such as content are disclosed. A method can comprise receiving data from a source, determining timing information associated with the source and automatically modifying a storage operation of data received from the source based upon the timing information.... Agent: Comcast Cable Communications, LLC
20150143070 - Nonvolatile storage and operating methods of computing devices including the nonvolatile storage: An writing and reading method of a nonvolatile Storage, that includes a first partition and a second partition, and is configured to allow a read operation and a write operation with respect to the second partition only when an authentication is successful in a normal mode, may comprise: assigning a... Agent:
20150143071 - Memory event notification: Embodiments of apparatuses and methods for memory event notification are disclosed. In one embodiment, a processor includes address translation hardware and memory event hardware. The address translation hardware is to support translation of a first address, used by software to access a memory, to a second address, used by the... Agent:
20150143072 - Method in a memory management unit for managing address translations in two stages: A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address (VA) relating to a first memory access request. The MMU may identify, based on the first IPA, a first memory page entry in a second... Agent: Stmicroelectronics International N.v.Previous industry: Electrical computers and digital data processing systems: input/output
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