|Electrical computers and digital processing systems: memory patents - Monitor Patents|
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Electrical computers and digital processing systems: memoryBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/16/2013 > 46 patent applications in 21 patent subcategories.
20130124776 - Secure data storage in raid memory devices: A redundant array of independent disk (RAID) memory storage system comprising data storage blocks arranged in a first plurality of data rows and a second plurality of data columns, wherein parity data is stored in additionally defined parity blocks, and wherein numbers of data blocks in respective columns are different,... Agent: Xtremlo Ltd.
20130124777 - Storage system logical block address de-allocation management and data hardening: A bridge receives a power down command and in response converts the power down command to a data hardening command. The bridge issues the data hardening command to a solid state disk. In response to the data hardening command, data stored on the solid state disk is hardened. The hardening... Agent: Lsi Corporation
20130124780 - Apparatus to manage efficient data migration between tiers: A data storage system having a slow tier and a fast tier maintains hot data on the fast tier by migrating data from the slow tier to reserve space on the fast tier as data becomes hot over time. The system maintains a reserve space table and performs a mass... Agent: Lsi Corporation
20130124791 - Apparatus, system, and method for storage space recovery in solid-state storage: An apparatus, system, and method are disclosed for storage space recovery in solid-state storage. A sequential storage module sequentially writes data packets in a storage division. The storage division includes a portion of a solid-state storage. The data packets are derived from an object. The data packets are sequentially stored... Agent: Fusion-io, Inc
20130124785 - Data deleting method and apparatus: A data deleting method and apparatus is provided in embodiments of this application. The method comprises: when a file system detects a delete request for a target file, examining a security property of the target file, wherein the security property of a file comprises secret classified property; if the security... Agent: Huawei Technologies Co., Ltd.
20130124781 - Data scrambling based on transition characteristic of the data: A method of storing data includes receiving data to be written to a memory device. The method includes selecting a scrambling operation from at least a first scrambling operation and a second scrambling operation. The scrambling operation is selected based on a transition characteristic associated with the data. The method... Agent: Sandisk Technologies Inc.
20130124792 - Erase-suspend system and method: A method for suspending an erase operation performed on a group of memory cells in a flash memory circuit is disclosed. One example method includes initiating an erase operation on one or more memory cells, the erase operation including a plurality of erase pulses, checking for receipt of a memory... Agent: Stec, Inc.
20130124794 - Logical to physical address mapping in storage systems comprising solid state memory devices: The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions... Agent: International Business Machines Corporation
20130124786 - Memory module and memory controller for controlling a memory module: The memory module having a plurality of memory chips and a plurality of connections for connecting the memory module to a processor. At least part of the connections is configurable to be grouped into N sets of address and control connections for N separatively controllable groups of memory chips of... Agent: International Business Machines Corporation
20130124790 - Memory module, cache system and address conversion method: A memory system including a non-volatile memory, a cache memory, a control circuit, and a data processing device is configured. The high speed can be achieved by transferring data in the non-volatile memory to the cache memory to retain the same therein. When the data in the non-volatile memory is... Agent: Renesas Electronics Corporation
20130124784 - Memory system comprising nonvolatile memory device and related method of operation: A method of programming a nonvolatile memory device comprises receiving write data, detecting an address of a multi-level cell area associated with the write data, randomizing the write data using the address and programming the randomized data in a single-level cell area.... Agent: Samsung Electronics Co., Ltd.
20130124793 - Method for utilizing a memory interface to control partitioning of a memory module: Apparatuses and methods for implementing partitioning in memory cards and modules where conventional memory cards or modules have only a single partition. A representative memory card/module in accordance with the invention includes a memory device(s), and a memory interface which includes a data bus, a command line and a clock... Agent: Nokia Corporation
20130124783 - Method of operating nonvolatile memory devices storing randomized data generated by copyback operation: In an operating method for a nonvolatile memory device, first random data is sensed from a source area of the memory cell array, the first random data having been generated using first random sequence data. While sensing the first random data, third random sequence data is loaded to a page... Agent: Samsung Electronics Co., Ltd.
20130124778 - Method of storing host data and meta data in a nand memory, a memory controller and a memory system: A host device connected to memory devices, with each memory device having NAND memory chips and an associated controller. Each NAND memory chip can store a page of data in a single write operation, and can read a page of data from NAND memory in a single read operation, with... Agent: Greenliant LLC
20130124788 - Multi-level data protection for flash memory system: The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a FLASH memory system. The methods and apparatuses involve a system controller for a plurality of FLASH memory devices in the FLASH memory system that is capable of protecting data using... Agent: Texas Memory Systems, Inc.
20130124787 - Nand flash-based storage device and methods of using: A solid state drive having at least one NAND flash memory component organized in blocks, pages and cells. Each cell is adapted to store at least two bits. Each block of the memory component is adapted to be dynamically configured to store at least one bit per cell using a... Agent: Ocz Technology Group Inc.
20130124789 - Partial allocate paging mechanism: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or... Agent: Spansion LLC
20130124782 - Solid state drive and method for constructing logical-to-physical table thereof: A solid state drive and a method for constructing a logical-to-physical table of the solid state drive are provided. Once the solid state drive is powered on again, the logical-to-physical table and the bitmap table are directly read from the flash memory. Then, the blocks whose history numbers are higher... Agent: Lite-on It Corporation
20130124779 - System and method for data inversion in a storage resource: A method may comprise receiving a page of data to be stored on a storage resource. The method may also comprise determining, for each particular inversion mode of a plurality of inversion modes, the number of bits of the page of data to be inverted to store a representation of... Agent: Dell Products L.p.
20130124795 - Semiconductor device and data processing system: The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue... Agent:
20130124796 - Storage method and apparatus which are based on data content identification: The embodiments of the present invention provide a storage method and a storage apparatus which are based on data content identification. Through the storage method and the storage apparatus which are based on data content identification and provided in the embodiments of the present invention, the data from the host... Agent: Huawei Technologies Co., Ltd.
20130124798 - System and method for transferring data between different raid data storage types for current data and replay data: The present disclosure relates to a data storage system including a RAID subsystem having a first and second type of RAID storage. A virtual volume configured to accept I/O is stored on the first type of RAID storage, and snapshots of the virtual volume are stored on the second type... Agent: Compellent Technologies
20130124797 - Virtual disks constructed from unused distributed storage: A virtual disk is comprised of segments of unused capacity of physical computer-readable storage media co-located with computing devices that are communicationally coupled to one another through network communications. The computing devices execute one or more of a client process, a storage process and a controller process. The controller processes... Agent: Microsoft Corporation
20130124799 - Self-disabling working set cache: A method to monitor the behavior of a working set cache of a full data set at run time and determine whether it provides a performance benefit is disclosed. An effectiveness metric of the working set cache is tracked over a period of time by efficiently computing the amount of... Agent: Microsoft Corporation
20130124800 - Apparatus and method for reducing processor latency: There is provided a data processing system comprising a central processing unit, a processor cache memory operably coupled to the central processing unit and an external connection operably coupled to the central processing unit and processor cache memory in which a portion of the data processing system is arranged to... Agent: Freescale Semiconductor, Inc.
20130124801 - Sas host controller cache tracking: A technique to track a host controller cache that includes receiving from a host controller a command indicating whether a cache of the host controller has data which is to be stored to a storage system. In the event that the host controller fails, perform an operation to transfer control... Agent:
20130124802 - Class dependent clean and dirty policy: A method for cleaning dirty data in an intermediate cache is disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes may include... Agent:
20130124803 - Prefetching source tracks for destaging updated tracks in a copy relationship: A point-in-time copy relationship associates tracks in a source storage with tracks in a target storage. The target storage stores the tracks in the source storage as of a point-in-time. A write request is received including an updated source track for a point-in-time source track in the source storage in... Agent: International Business Machines Corporation
20130124804 - Data restoration program, data restoration apparatus, and data restoration method: A computer-readable recording medium stores a program that causes a computer capable of accessing a multicore processor equipped with volatile memories and a plurality of cores accessing the volatile memories, to execute a data restoration process. The data restoration process includes detecting a suspend instruction to any one of the... Agent: Fujitsu Limited
20130124805 - Apparatus and method for servicing latency-sensitive memory requests: A shared memory controller and method of operation are provided. The shared memory controller is configured for use with a plurality of processors such as a central processing unit or a graphics processing unit. The shared memory controller includes a command queue configured to hold a plurality of memory commands... Agent: Advanced Micro Devices, Inc.
20130124806 - Dynamic ram phy interface with configurable power states: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements... Agent: Advanced Micro Devices, Inc.
20130124807 - Enhanced software application platform: A system includes information for generating a first appliance based on first appliance information, information for generating a second appliance based on second appliance information, and information for configuring communication between the first appliance and the second appliance. The system further includes at least one processor configured to generate a... Agent:
20130124808 - Storage system and storage subsystem: Storage system arrangements having status information including both copy group summary status information providing a status of a group of the plurality of copy pairs, and detailed status information detailing a status of a copy pair included in the group; and wherein said status management unit monitors the status information... Agent:
20130124809 - Distributing data among data storage partitions based on a forecasted demand in a networked computing environment: Embodiments of the present invention provide an approach to forecast a potential demand for partitioned/sharded data and to distribute the data among a set of data partitions based on forecasted demand to optimize network characteristics (e.g., network bandwidth) and/or expedite data retrieval. For example, the data may be distributed among... Agent: International Business Machines Corporation
20130124811 - Dynamic storage hierarchy management: A data block may be moved between a first medium and a second medium. The movement of the data block involves measuring the access characteristic of the data block as the data block is stored on the first medium. The performance characteristics of the first medium and the second medium... Agent: Microsoft Corporation
20130124810 - Increasing memory capacity in power-constrained systems: A method for increasing a capacity of a memory is provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset... Agent: International Business Machines Corporation
20130124812 - Facilitation of simultaneous storage initialization and data destage: Various embodiments for storage initialization and data destage in a computing storage environment are provided. At least a portion of data on a storage device is initialized using a background process, while one of simultaneously and subsequently destaging the at least the portion of the data to the storage device... Agent: International Business Machines Corporation
20130124813 - Methods and systems for formatting storage volumes: Methods, systems, and computer storage mediums including a computer program product method for formatting storage volumes are provided. One method includes creating a storage volume including a global counter and partitioned into multiple storage segments including a segment counter and partitioned into multiple stripes, wherein the global counter and each... Agent: International Business Machines Corporation
20130124814 - Increasing memory capacity in power-constrained systems: A system, and computer program product for increasing a capacity of a memory are provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier... Agent: International Business Machines Corporation
20130124815 - Bank-based memory allocation to optimize memory bandwidth: A method for optimizing memory bandwidth using bank-based memory allocation is described. The method includes receiving a request for an allocation of memory. In response to receiving the request, memory is allocated to the request based on a performance ranking of memory banks in a plurality of memory banks. A... Agent: Nokia Corporation
20130124816 - Device requiring address allocation, device system and address allocation method: A device requiring address allocation, a device system, and an address allocation method. A control device in the device system transmits currently allocated address information and a contention start signal to each device requiring address allocation in the device system through a bus, and the devices requiring address allocation with... Agent: Montage Technology (shanghai) Co., Ltd.
20130124817 - Information processing apparatus: Performing data processing for data sets stored in each of a plurality of storage devices includes collecting access data indicating details of accesses to each of the plurality of storage devices and computing predicted changes in access frequency for each of the storage devices on the basis of the access... Agent: International Business Machines Corporation
20130124818 - System and method for controlling automated page-based tier management in storage systems: System and method for automated page-based management in storage systems. The system includes host computers, file servers and a storage system having automated page-based management means. The storage system interface receives instructions to change the condition for decision for migration regarding particular parts or the whole volume. The host computer... Agent: Hitachi, Ltd., Intellectual Property Group
20130124819 - Object transformation of arrays of formulas and values: Embodiments of the invention relate to reducing memory required to store an array of formulas and values corresponding to a formula-array. A set of formula-array representations is provided and arranged in a successive order. Each formula-array representation is evaluated for an associated memory requirement to support use thereof, followed by... Agent: International Business Machines Corporation
20130124820 - Data processing apparatus and method for performing memory transactions within such a data processing apparatus: A data processing apparatus has processing circuitry for executing a memory access instruction in order to generate a memory transaction comprising at least one address transfer specifying a memory address, and at least one associated data transfer specifying data to be accessed at the specified memory address. The apparatus is... Agent: Arm Limited
20130124821 - Method of managing computer memory, corresponding computer program product, and data storage device therefor: The invention concerns a method of managing computer memory, the method comprising the steps of maintaining (101) a page table entry for mapping a virtual address to a physical address and a cache comprising a plurality of data blocks and, in response to a reference to the virtual address, translating... Agent: Alcatel Lucent05/09/2013 > 40 patent applications in 19 patent subcategories.
20130117493 - Reliable memory mapping in a computing system: Methods, apparatus, and products for reliable memory mapping in a computing system, the computing system including a plurality of memory modules, including: determining, by a channel mapping module, a reliability rating for each of a plurality of memory controller address ranges; mapping, by the channel mapping module, critical system-level memory... Agent: International Business Machines Corporation
20130117494 - Optimizing available computing resources within a virtual environment: Methods and systems for the optimization of available computing resources within a virtual environment are disclosed. An exemplary method comprises determining the sizes of the computing resources available to the virtual machine and determining optimal data structures for the virtual machine based on the sizes of the computing resources. The... Agent:
20130117495 - Configurable memory system: An interface circuit that emulates a memory circuit having a first organization using a memory circuit having a second organization, wherein the second organization includes a number of banks, a number of rows, a number of columns, and a number of bits per column.... Agent: Google Inc.
20130117497 - Buffer management strategies for flash-based storage systems: Techniques are generally described related to a flash-based buffer management strategy. One example method for managing a buffer for a computer system may include monitoring, by a buffer management module, a plurality of operations being executed on the computer system and utilizing a plurality of buffer pages of the buffer.... Agent: Peking University
20130117501 - Garbage collection method for nonvolatile memory device: A nonvolatile memory device includes a memory area having free segments and first to fourth regions having used segments. The garbage collection method includes selecting a target segment from the used segments, moving a valid data block from the selected target segment to the used segments, and erasing data of... Agent: Samsung Electronics Co., Ltd.
20130117500 - Memory system and memory managing method thereof: A memory managing method is provided for a memory system, including a nonvolatile memory device and a memory controller controlling the nonvolatile memory device. The memory managing method includes determining whether a program-erase number of a memory block in the nonvolatile memory device reaches a first reference value; managing a... Agent: Samsung Electronics Co., Ltd.
20130117496 - Method and system for managing flash write: A method for managing flash memory operations in a flash memory, comprising; assigning a state code to said flash memory operations; updating a state code flag with the assigned state code upon completion of each of said flash memory operations; wherein the assignment of said state codes is selected in... Agent: Dsp Group Ltd.
20130117502 - Method for managing system firmware in nas server: A method for managing system firmware in a network attached storage (NAS) server comprises: synchronizing system firmware stored one or more of two or more hard disks (HDDs) and system firmware stored in a nonvolatile memory with each other; and confirming whether or not at least one valid HDD in... Agent: Hitachi-lg Data Storage Korea, Inc.
20130117499 - Reversible write-protection for non-volatile semiconductor memory device: A serial memory device having a non-volatile memory array including a plurality of memory blocks, one or more said plurality of blocks being capable of being placed in a locked or an unlocked state upon receiving designated lock or unlock signal sequences is provided. The unlock signal sequences comprises at... Agent:
20130117503 - Servicing non-block storage requests: An apparatus, system, and method are disclosed for servicing storage requests for a non-volatile memory device. An interface module is configured to receive a storage request for a data set of a non-volatile memory device from a client. The data set is different from a block of the non-volatile memory... Agent: Fusion-io, Inc.
20130117498 - Simulated nvram: Embodiments of the invention relate to leveraging disk controller cache memory to simulate non-volatile random access memory. At least one logical block address in cache memory of the disk controller is designated and set aside as permanently dirty. Read operations may be supported with data in the cache memory; including... Agent: International Business Machines Corporation
20130117504 - Embedded memory and dedicated processor structure within an integrated circuit: An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of... Agent: Xilinx, Inc.
20130117506 - Integrated circuit device, data storage array system and method therefor: An integrated circuit device comprises a data storage array controller for providing data storage array functionality for at least one data storage array. The data storage array controller comprises an address window controller arranged to receive at least one data storage device access command, and upon receipt of the at... Agent: Freescale Semiconductor, Inc.
20130117505 - Setting optimal space allocation policy for creating dependent snapshots to enhance application write performance and reduce resource usage: In one embodiment, a system includes a network storage controller having logic adapted for receiving a request to duplicate at least a portion of a volume stored on the first disk array, logic adapted for creating at least one dependent volume on the first disk array, and logic adapted for... Agent: International Business Machines Corporation
20130117508 - Electronic device system, electronic device, and storage medium: An SDIO device 102 stores a program and identification information, outputs the program from an SD pin unit 40, and outputs the identification information from an extended pin unit 41. An electronic device 101 has an SD pin unit 30 connected to an SD pin unit 40 and an extended... Agent: Sharp Kabushiki Kaisha
20130117507 - Memory storage apparatus, memory controller, and method for transmitting and identifying data stream: A memory storage apparatus, a memory controller and method for transmitting and identifying data streams are provided. The memory controller passes at least a portion of a data stream received from a host system to a smart card chip of the memory storage apparatus. Then, the host system accurately receives... Agent: Phison Electronics Corp.
20130117509 - Technique to share information among different cache coherency domains: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner... Agent:
20130117510 - System and method for managing an object cache: In order to optimize efficiency of deserialization, a serialization cache is maintained at an object server. The serialization cache is maintained in conjunction with an object cache and stores serialized forms of objects cached within the object cache. When an inbound request is received, a serialized object received in the... Agent: Recursion Software, Inc.
20130117511 - Data processing apparatus and method: A data processing apparatus has a cache having a normal mode and a retention mode in which the cache consumes less power than in the normal mode. An interconnect receives, from at least one other device, coherency access requests for data stored in the cache. In the normal mode, the... Agent: Arm Limited
20130117512 - Program converting apparatus, program converting method, and medium: According to one embodiment, a program converting device includes an access attribute determining unit, a non-sharing target classifying unit, and a converting unit. The access attribute determining unit calculates exclusive accesses from memory accesses by threads forming a source program and determines a memory access using a cache memory among... Agent: Kabushiki Kaisha Toshiba
20130117513 - Memory queue handling techniques for reducing impact of high latency memory operations: Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes... Agent: International Business Machines Corporation
20130117514 - Addressing cross-allocated blocks in a file system: A mechanism is provided for cross-allocated block repair in a mounted file system. A set of cross-allocated blocks are identified from a plurality of blocks within an inode of the mounted file system, based on a corresponding bit associated with each cross-allocated block in a duplicated block information bitmap being... Agent: International Business Machines Corporation
20130117517 - Data allocation system: A data control system facilitates transfer of a virtual disk from a primary storage system to a secondary storage system. The data control system, responsive to an instruction to transfer the virtual disk, wherein the virtual disk comprises a plurality of data blocks, determines whether each of the plurality of... Agent: Quantum Corporation
20130117515 - Primary data storage system with data tiering: The invention is directed to a primary data storage system for use in a computer network in which a network allows user computers to transfer data to/from the primary data storage system. In one embodiment, the primary data storage system implements a tiering strategy to move data between stores with... Agent: Nexgen Storage, Inc.
20130117516 - Primary data storage system with staged deduplication: The invention is directed to a primary data storage system for use in a computer network in which a network allows user computers to transfer data to and/or from the primary data storage system. In one embodiment of the invention, the storage processor operates to analyze the data associated with... Agent: Nexgen Storage, Inc.
20130117518 - System controller, information processing system and method of saving and restoring data in the information processing system: A system controller (1), which saves and restores data in a volatile memory (29A) in processing device (2A, 2B), is provided a non-volatile memory (12A) for provisional data and a non-volatile memory (12C) in a non-volatile area. The system controller (1) once saves the data in the non-volatile memory (12A)... Agent: Fujitsu Limited
20130117519 - Memory management in multi-threaded multi-processor computing system: Allocators are instantiated for each of a plurality of processors in a multi-threaded multi-processor computing system. The allocators selectively allocate and deallocate memory to threads executing on the associated processor. Related apparatus, systems, techniques and articles are also described.... Agent: Sap Ag
20130117520 - Method and apparatus for relocating data: Disclosed are an apparatus and method for recycling areas of a data storage device by relocating data. In one embodiment, a method may comprise selecting a first storage area based on a quantity of obsolete data in the first storage area, moving valid data from the first storage area to... Agent: Seagate Technology LLC
20130117523 - Data copying method and apparatus in a thin provisioned system: Data migration includes copying between normal volumes and thin provisioned volumes. Data in a normal volume can be copied to a thin provisioned volume. Alternatively, data structures can be provided to facilitate converting a normal volume into a thin provisioned volume without actual copying of data. Copying from a thin... Agent: Hitachi, Ltd.
20130117522 - Inter-process memory management: A memory allocator assigns temporary memory limits to each of a plurality of processes requiring memory. Thereafter, at least one assigned temporary memory limit is changed during execution of a corresponding process. Related apparatus, systems, techniques and articles are also described.... Agent: Sap Ag
20130117524 - Management of recycling bin for thinly-provisioned logical volumes: A method for data storage includes representing logical volumes by respective sets of pointers to physical partitions in which data used by the logical volumes is stored. One or more of the logical volumes are defined as provisionally deleted. A subset of the provisionally-deleted logical volumes is selected such that... Agent: International Business Machines Corporation
20130117521 - Managing chip multi-processors through virtual domains: A chip multi-processor (CMP) with virtual domain management. The CMP has a plurality of tiles each including a core and a cache, a mapping storage, a plurality of memory controllers, a communication bus interconnecting the tiles and the memory controllers, and machine-executable instructions. The tiles and memory controllers are responsive... Agent:
20130117527 - Method and apparatus for thin provisioning: Embodiments of the present invention provide a method and an apparatus for thin provisioning. The method includes: receiving a write IO instruction sent by a host; when the write IO instruction is not allocated a logical space and a pre-allocated space in an LUN is insufficient to be allocated to... Agent: Huawei Technologies Co., Ltd.
20130117525 - Method for implementing pre-emptive read reconstruction: The present invention is directed to a method for pre-emptive read reconstruction. In the method(s) disclosed herein, when a pre-emptive read reconstruction timer times out, if one or more drive read operations for providing requested stripe read data are still pending; and if stripe read data corresponding to the pending... Agent: Lsi Corporation
20130117526 - Shared temporary storage management in a shared disk database cluster: System, method, computer program product embodiments and combinations and sub-combinations thereof for temporary storage management in a shared disk database cluster are provided. Included is the reserving of units on-demand and of variable size from shared temporary storage space in the SDC. The utilization of the reserved units of the... Agent: Sybase, Inc.
20130117529 - Dispersed storage unit and method for configuration thereof: A dispersed storage (DS) unit for use within a dispersed storage network is capable of self-configuring using registry information provided to the DS unit. The registry information includes a slice name assignment indicating a range of slice names corresponding to a plurality of potential data slices of potential data objects... Agent: Cleversafe, Inc.
20130117528 - Partitioning data within a distributed data storage system using virtual file links: A record within a destination virtual file is generated on a destination node of a distributed data storage system. The record comprises (i) a link directed to a partition of a source virtual file stored on a source node and (ii) partition criteria characterizing the partition. The source virtual file... Agent: Sap Ag
20130117530 - Apparatus for translating virtual address space: The apparatus includes a virtual address space generation unit generating a virtual address space of a guest operating system, the guest operating system being executed in the virtual address space, and a virtual address space of a virtual machine monitor, the virtual machine monitor being executed in the virtual address... Agent: Electronics And Telecommunications Research Institute
20130117531 - Method, system, and apparatus for page sizing extension: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned.... Agent:
20130117532 - Interleaving address modification: An apparatus having a plurality of memory blocks and a circuit is disclosed. The circuit may be configured to (i) generate a second address by removing one or more first bits of a first address from one or more first locations defined by a first value, (ii) generate a third... Agent:05/02/2013 > 87 patent applications in 41 patent subcategories.
20130111101 - Semiconductor memory device and operating method thereof: A semiconductor memory device includes a path control unit configured to activate an address transmission path corresponding to a bank address, an address providing unit configured to provide a memory address to the path control unit in response to an active signal, and a plurality of memory banks each configured... Agent:
20130111102 - Semiconductor memory devices: A semiconductor memory device includes a selective data inversion unit and an inversion control unit. The selective data inversion unit inverts or maintains internal output data with a plurality of bits from a memory cell array to provide output data with a plurality of bits in response to an inversion... Agent:
20130111104 - Asynchronous data shift and backup between asymmetric data sources: Embodiments of the present invention provide a semiconductor storage device (SSD)-based storage system. Specifically, in a typical embodiment, the system comprises a SSD memory disk unit having (among other components) a memory controller and an asynchronous backup controller for providing asynchronous data shift and/or backup between multiple data storage units... Agent:
20130111109 - Capacitor save energy verification: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power... Agent: Agiga Tech Inc.
20130111110 - Capacitor save energy verification: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power... Agent: Agiga Tech Inc.
20130111111 - Capacitor save energy verification: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power... Agent: Agiga Tech Inc.
20130111114 - Distributed storage system, apparatus, and method for managing distributed storage in consideration of request pattern: A distributed storage management apparatus includes a monitoring unit configured to monitor a request pattern of each storage node of a plurality of storage nodes configured to distributively store data and at least one replica of the data; a group setting unit configured to receive a request and classify the... Agent: Samsung Electronics Co., Ltd
20130111103 - High-speed synchronous writes to persistent storage: A memory configured to provide a write requestor with a direct write programming interface to a disk device. A first persistent memory is configured for designating at least a portion its memory locations as central processing unit (CPU) load storable memory. The first persistent memory is also configured for receiving... Agent: International Business Corporation
20130111115 - Managing write operations in a computerized memory: A method, computer program product, and storage device for managing a computerized memory for storing data are disclosed. Data updates are performed by writing data updates out-of-place where data updates to outdated data are written to a subunit different from a subunit containing the outdated data. The subunit containing the... Agent: International Business Machines Corporation
20130111112 - Method for adjusting performance of a storage device and a semiconductor storage device therefor: A method of controlling a storage device, the method including calculating, in a controller of the storage device, data throughput of the storage device in a current period, comparing, in the controller, the data throughput to a reference value and adjusting, with the controller, an operation performance of the storage... Agent:
20130111113 - Nand flash memory controller exporting a nand interface: A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the... Agent:
20130111105 - Non-volatile data structure manager and methods of managing non-volatile data structures: Non-volatile data structure managers and methods to manage non-volatile data structures are disclosed. An example non-volatile data structure manager includes a persistent data structure (PDS) to maintain at least one version of a non-volatile heap; a PDS versioner to create a version of the PDS reflective of a state of... Agent:
20130111106 - Promotion of partial data segments in flash cache: Exemplary method, system, and computer program product embodiments for efficient track destage in secondary storage in a more effective manner, are provided. In one embodiment, by way of example only, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the... Agent: International Business Machines Corporation
20130111108 - Solid state drive and method for controlling cache memory thereof: A method for controlling a cache memory of a solid state drive is provided. The solid state drive has a flash memory. The flash memory has a plurality of blocks, wherein each block has a plurality of pages. The method includes the following steps. Firstly, a refreshed data corresponding to... Agent: Lite-on It Corporation
20130111117 - Storage array, storage system, and data access method: A storage array, a storage system, and a data access method. A data access method of a storage device includes: transferring data input from a user interface chip to a non-volatile storage device through a peripheral component interconnect express (PCIE) link, where the user interface chip and the non-volatile storage... Agent: Huawei Technologies Co., Ltd.
20130111116 - Storage device and computer using the same: A storage device includes a non-volatile memory, a cache memory and a memory controller. The non-volatile memory stores a logical-to-physical address translation table for managing partitioned data and storage locations thereof. The cache memory stores a data cache and a logical-to-physical address translation table cache which holds a portion of... Agent: Hitachi, Ltd.
20130111118 - System and method for storing data using a flexible data format: A flash storage device includes a flash storage for storing data and a controller for receiving a command in connection with user data and selecting a sector size associated with storing the user data. The controller allocates the user data among data sectors having the sector size and writes the... Agent: Stec, Inc.
20130111107 - Tier identification (tid) for tiered memory characteristics: A tier identification (TID) is to indicate a characteristic of a memory region associated with a virtual address in a tiered memory system. A thread may be serviced according to a first path based on the TID indicating a first characteristic. The thread may be serviced according to a second... Agent:
20130111119 - Ram block designed for efficient ganging: A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two... Agent:
20130111123 - A memory system that utilizes a wide input/output (i/o) interface to interface memory storage with an interposer and that utilizes a serdes interface to interface a memory controller with an integrated circuit, and a method: A memory system is provided in which at least one DRAM chip and a memory controller chip are mounted in a side-by-side relationship on an interposer. The DRAM chip is connected to the interposer via a Wide I/O interface to enable the DRAM chip and the memory controller chip to... Agent: Avago Technologies EnterpriseIP(singapore) Pte. Ltd.
20130111121 - Dynamically controlling cache size to maximize energy efficiency: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory... Agent:
20130111120 - Enabling a non-core domain to control memory bandwidth: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect... Agent:
20130111122 - Method and apparatus for network table lookups: An apparatus comprising a plurality of memory components each comprising a plurality of memory banks, a memory controller coupled to the memory components and configured to control and select a one of the plurality of memory components for a memory operation, a plurality of address/command buses coupled to the plurality... Agent: Futurewei Technologies, Inc.
20130111124 - Digital device configuration and method: A digital Storage Element is described. A device is configured including a Storage Element for access by a user responsive to a native control code. A processing arrangement executes a control program for controlling the overall device and executing at least a portion of the native control code as part... Agent: Benhov Gmbh, LLC
20130111125 - Shared cache module and method thereof: Shared cache modules, systems, and methods are provided herein. The shared cache module is useable with at least one initiator on a serial attached small computer system interface system. The shared cache module includes a memory device and a memory interface. The memory device assigns each of the at least... Agent:
20130111126 - Expander to enable virtual storage units corresponding to subdivisions within a physical storage unit: In at least some embodiments, an expander includes control logic to manage temporary connections and resource allocation between a storage access request initiator and a plurality of physical storage units, and to enable virtual storage units corresponding to subdivisions within at least one of the physical storage units by emulating... Agent:
20130111127 - Storage system and data processing method in storage system: When a snapshot virtual volume is provided to the host as an OS image of a virtual machine in a system where a single V-VOL is used by a single VM and all the VMs are started concurrently, burdensome Copy-on-Write (CoW) accesses placing heavy I/O loads on the storage occur... Agent: Hitachi, Ltd.
20130111128 - Method for implementing and application of a secure processor stick (sps): Systems and methods for implementing a secure processor stick are described. In one aspect, the system for implementing a secure processor stick with a computer, the system comprising: a secure processor stick, including: a processor; a memory coupled to said processor; a smart chip coupled to said processor, said smart... Agent: Cassis International Pte Ltd.
20130111129 - Computer system and storage management method: Data is placed in tiered storage with a suitable granularity according to application characteristics. The storage apparatus comprises a controller for managing storage areas, provided by storage media of a plurality of types of varying performance, as pools, and for assigning the storage areas in page units to a virtual... Agent: Hitachi, Ltd.
20130111131 - Dynamically adjusted threshold for population of secondary cache: The population of data to be inserted into secondary data storage cache is controlled by determining a heat metric of candidate data; adjusting a heat metric threshold; rejecting candidate data provided to the secondary data storage cache whose heat metric is less than the threshold; and admitting candidate data whose... Agent: International Business Machines Corporation
20130111130 - Memory including a reduced leakage wordline driver: A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is... Agent:
20130111132 - Cache memory that supports tagless addressing: Embodiments related to a cache memory that supports tagless addressing are disclosed. Some embodiments receive a request to perform a memory access, wherein the request includes a virtual address. In response, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache... Agent: Rambus Inc.
20130111133 - Dynamically adjusted threshold for population of secondary cache: The population of data to be inserted into secondary data storage cache is controlled by determining a heat metric of candidate data; adjusting a heat metric threshold; rejecting candidate data provided to the secondary data storage cache whose heat metric is less than the threshold; and admitting candidate data whose... Agent: International Business Machines Corporation
20130111134 - Management of partial data segments in dual cache systems: Various embodiments for movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor are provided. In one such embodiment, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of... Agent: International Business Machines Corporation
20130111138 - Multi-core processor system, computer product, and control method: A multi-core processor system includes shared memory shared by cores of a multi-core processor; first cache memories respectively for each of the cores; a second cache memory between the shared memory and the first cache memories, and storing shared data shared by the cores and referred to by at least... Agent: Fujitsu Limited
20130111139 - Optimizing a cache back invalidation policy: A method, a system and a computer program product for enhancing a cache back invalidation policy by utilizing least recently used (LRU) bits and presence bits in selecting cache-lines for eviction. A cache back invalidation (CBI) utility evicts cache-lines by using presence bits to avoid replacing a cache-line in a... Agent: International Business Machines Corporation
20130111137 - Processor-cache system and method: A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit... Agent: Shanghai Xin Hao Micro Electronics Co. Ltd.
20130111135 - Variable cache line size management: According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level... Agent: International Business Machines Corporation
20130111136 - Variable cache line size management: According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line from an upper level sectored cache to an unsectored lower level cache is to be performed, wherein the upper... Agent: International Business Machines Corporation
20130111140 - Cache memory apparatus, cache control method, and microprocessor system: A cache memory apparatus according to the present invention includes a cache memory that caches an instruction code corresponding to a fetch address and a cache control circuit that controls the instruction code to be cached in the cache memory. The cache control circuit caches an instruction code corresponding to... Agent: Renesas Electronics Corporation
20130111142 - Method for accessing cache and pseudo cache agent: Embodiments of the present invention disclose a method for accessing a cache and a pseudo cache agent (PCA). The method of the present invention is applied to a multiprocessor system, where the system includes at least one NC, at least one PCA conforming to a processor micro-architecture level interconnect protocol... Agent: Huawei Technologies Co., Ltd.
20130111141 - Multi-core interconnect in a network processor: A network processor includes multiple processor cores for processing packet data. In order to provide the processor cores with access to a memory subsystem, an interconnect circuit directs communications between the processor cores and the L2 Cache and other memory devices. The processor cores are divided into several groups, each... Agent: Cavium, Inc.
20130111143 - Multi-core system and external input/output bus control method: A multi-core system includes processor cores having caches; an external input/output bus connected to the processor cores; memory accessed by the processor cores via the external input/output bus; profile information indicating the volume of a write access to the memory by tasks concurrently allocated to the processor cores and whether... Agent: Fujitsu Limited
20130111144 - Efficient memory management in software caches: The use of heap memory is optimized by extending a cache implementation with a CacheInterface base class. An instance of a ReferenceToCache is attached to the CacheInterface base class. The cache implementation is registered to a garbage collector application. The registration is stored as a reference list in a memory.... Agent: International Business Machines Corporation
20130111145 - Mapping of valid and dirty flags in a caching system: An apparatus comprising a controller and a memory. The controller may be configured to generate (i) an index signal and (ii) an information signal in response to (i) one or more address signals and (ii) a data signal. The memory may be configured to store said information signal in one... Agent:
20130111146 - Selective population of secondary cache employing heat metrics: The population of data to be admitted into secondary data storage cache of a data storage system is controlled by determining heat metrics of data of the data storage system. If candidate data is submitted for admission into the secondary cache, data is selected to tentatively be evicted from the... Agent: International Business Machines Corporation
20130111147 - Methods and apparatus to access memory: Example methods, apparatus, and articles of manufacture to access memory are disclosed. A disclosed example method involves receiving at least one runtime characteristic associated with accesses to contents of a memory page and dynamically adjusting a memory fetch width for accessing the memory page based on the at least one... Agent:
20130111149 - Integrated circuits with cache-coherency: An improved cache coherency controller, method of operation, and system of such is provided. Traffic from coherent agents to shared targets can flow on different channels through the coherency controller. This improves quality of service for performance sensitive agents. Furthermore, data transfer is performed on a separate network from coherency... Agent: Arteris Sas
20130111148 - Three channel cache-coherency socket protocol: A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests... Agent: Arteris Sas
20130111150 - Method for preventing deadlock of node controller, and node controller: A method for preventing deadlock of a node controller includes receiving, by an NC of a current node, a request message from any node, and writing the request message into a processing queue; performing invalidation processing on the cache data block that includes the system address and is cached on... Agent: Huawei Technologies Co., Ltd.
20130111151 - Software translation lookaside buffer for persistent pointer management: Techniques are provided for performing OID-to-VMA translations during runtime. Vector registers are used to implement a “software TLB” to perform OID-to-VMA translations. Runtime dereferencing is performed using one or more vector registers to compare each OID that needs to be dereferenced against a set of cached OIDs. When a cached... Agent: Oracle International Corporation
20130111152 - Method for optimizing memory access in a microprocessor including several logic cores upon resumption of executing an application, and computer program implementing such a method: The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom... Agent: Bull Sas
20130111154 - Control device of virtual storage system, virtual storage system, and method for controlling virtual storage system: A control device of a virtual storage system includes a physical drive to store data of a logical volume in a storage medium and a plurality of processing devices to perform a mount process or an un-mount process for mounting the logical volume on a virtual drive that virtually stores... Agent: Fujitsu Limited
20130111153 - Distributed storage system, apparatus and method for managing a distributed storage in consideration of latency elements: A distributed storage managing apparatus id provided. The distributed storage managing apparatus includes a detector configured to detect a busy storage node having a latency element from among a plurality of storage nodes that distributively store data using a plurality of replicas, and a controller configured to transfer a request... Agent:
20130111156 - Flexible pin allocation: A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration... Agent: Juniper Networks, Inc.
20130111155 - Releasing blocks of storage class memory: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class... Agent: International Business Machines Corporation
20130111157 - Computer product, association method, and association apparatus: A computer-readable recording medium stores a program causing a computer to execute an association process that includes identifying a second storage location associated with a first storage location by referring to a memory unit configured to store storage location association information indicating relevance between the first storage location and the... Agent: Fujitsu Limited
20130111158 - Multi-core processor system, control program, and control method: A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit... Agent: Fujitsu Limited
20130111159 - Digital signal processing data transfer: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations... Agent: Imagination Technologies Limited
20130111160 - Selective space reclamation of data storage memory employing heat and relocation metrics: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics... Agent: International Business Machines Corporation
20130111162 - Store storage class memory information command: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class... Agent: International Business Machines Corporation
20130111161 - System and method for retention of historical data in storage resources: In accordance with embodiments of the present disclosure, a method may include receiving a read command. The method may also include determining if the read command is a command to read current data or historical data for a given logical address. The method may additionally include reading data stored on... Agent: Dell Products L.p.
20130111165 - Computer product, writing control method, writing control apparatus, and system: A computer-readable recording medium stores a program that causes a computer to execute a writing control process that includes receiving a writing request to write a first data to a first storage apparatus; determining a second data from among a series of data and based on a writing sequence of... Agent: Fujitsu Limited
20130111166 - Copying data in a dispersed storage network without replication: A method begins by a dispersed storage (DS) processing module receiving a request to copy a data object in a dispersed storage network (DSN). The method continues with the DS processing module identifying one or more sets of at least a decode threshold number of slice names for one or... Agent: Cleversafe, Inc.
20130111164 - Hardware compression using common portions of data: Methods and devices are provided for data compression. Data compression can include receiving a plurality of data chunks, sampling at least some of the plurality of data chunks extracting a common portion from a number of the plurality of data chunks based on the sampling, and storing a remainder of... Agent:
20130111163 - Multiple computing environments on a computer system: A first and a second computing environments are generated on a computer system based on a state of a logical storage unit of the computer system. The computing environments are associated with pieces of storage space located outside the logical storage unit. A write operation addressing the logical storage unit... Agent:
20130111167 - Uncached static short address translation table in the cache coherent computer system: A network unit, comprising a processor and a random access memory (RAM) component coupled to the processor, wherein the RAM component comprises a memory management unit (MMU) and a data RAM, wherein the MMU comprises a complete page address table for translating a virtual memory address received from the processor... Agent: Futurewei Technologies, Co.
20130111169 - Engine control unit for an internal combustion engine: A control unit for an internal combustion engine including a microcontroller having an integrated memory for receiving memory contents, in which the microcontroller is configured so that, in a first operation, memory areas are definable for providing a final memory protection and/or memory areas are provided with a preliminary memory... Agent:
20130111168 - Systems and methods for semaphore-based protection of shared system resources: An electronic system includes multiple data access components (DACs), a semaphores module, and a memory protection unit (MPU). Any of the DACs may issue an access request, which requests access to a shared system resource. A region descriptor associated with the shared system resource specifies default access permissions for the... Agent: Freescale Semiconductor, Inc.
20130111172 - Data migration between storage devices: A method for data migration between storage devices according to an embodiment of the invention comprises: collecting an original time domain sequence of workload parameters of a data volume in a low speed storage device; evaluating a workload period of the data volume based on the collected original time domain... Agent: International Business Machines Corporation
20130111174 - Moving blocks of data between main memory and storage class memory: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class... Agent: International Business Machines Corporation
20130111171 - Storage apparatus and data management method:
20130111170 - Storage apparatus and method of controlling storage apparatus: A storage apparatus provides a server apparatus with virtual volumes in thin provisioning; allocates a physical page to each pool page from a storage pool that is able to provide a plurality of types of physical pages classified into tiers, the pool page being an allocation unit of a storage... Agent: Hitachi, Ltd.
20130111173 - Using extended asynchronous data mover indirect data address words: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class... Agent: International Business Machines Corporation
20130111176 - Memory controller with staggered request signal output: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is... Agent: Rambus Inc.
20130111175 - Methods and apparatus to control generation of memory access requests: Example methods, apparatus, and articles of manufacture to control generation of memory access requests in processor systems are disclosed. A disclosed example method involves determining at a memory controller whether a memory access queue depth for a memory reference is greater than a first threshold. When the memory access queue... Agent:
20130111179 - Configure storage class memory command: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class... Agent: International Business Machines Corporation
20130111178 - Deconfigure storage class memory command: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class... Agent: International Business Machines Corporation
20130111177 - Implementing feedback directed numa mitigation tuning: A method, system and computer program product are provided for implementing feedback directed Non-Uniform Memory Access (NUMA) mitigation tuning in a computer system. During a page frame memory allocation for a process, predefined monitored performance metrics are compared with stored threshold values. Responsive to the compared values, selected use of... Agent: International Business Machines Corporation
20130111180 - Partitioning a memory into a high and a low performance partitions: Examples disclose partitioning a volatile memory into a high performance partition and a low performance partition. Further the example discloses retrieving an application with a high performance data and a low performance data from a non-volatile memory to place the high and the low performance data in the high and... Agent:
20130111181 - Methods and apparatus for increasing device access performance in data processing systems: A data processing system comprises a device and device access circuitry. The device is mapped to a first mapped address region and to a second mapped address region. The device access circuitry, in turn, is operative to access the device in accordance with a first set of memory attributes when... Agent: Lsi Corporation
20130111182 - Storing a small file with a reduced storage and memory footprint: An I/O request to store a file in a file-system is received. A determination is made whether the size of the file does not exceed a threshold size. Exceeding the threshold results in storing at least a portion of the file in a block of the file-system devoid of sub-blocks.... Agent: International Business Machines Corporation
20130111183 - Address translation apparatus, address translation method, and calculation apparatus: An address translation apparatus includes: a first address translation unit to hold, first address information, validity information and correspondence information, the first address information indicating correspondence between a virtual address and a physical address, the validity information indicating a validity of the first address information, and the correspondence information indicating... Agent: Fujitsu Limited
20130111184 - Method and system for caching attribute data for matching attributes with physical addresses: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics... Agent: Intellectual Venture Funding LLC
20130111185 - Chaining move specification blocks: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class... Agent: International Business Machines Corporation
20130111186 - Instruction address adjustment in response to logically non-significant operations: A method, apparatus, and program product execute instructions of an instruction stream and detect logically non-significant operations in the instruction stream. Then, based on that detection, a target or source address of a subsequent instruction is adjusted. In some instances, doing so enables a greater number of addresses, e.g., registers,... Agent: International Business Machines Corporation
20130111187 - Data read and write method and apparatus, and storage system: The present disclosure provides a data read and write method and apparatus and a storage system. The data read and write method includes: receiving, by a block storage driver of an origination device, a request for an LBA-based operation on a volume; converting the LBA-based operation request into a Key... Agent: Huawei Technologies Co., Ltd.04/25/2013 > 43 patent applications in 23 patent subcategories.
20130103882 - Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine: A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host machine context and executing a virtual machine application within a virtual machine context. A plurality of TLB (translation look aside buffer)... Agent: Intellectual Venture Funding LLC
20130103885 - Administering thermal distribution among memory modules of a computing system: A computing system includes a number of memory modules and temperature sensors. Each temperature sensor measures a temperature of a memory module. In such a computing system a garbage collector during garbage collection, determines whether a temperature measurement of a temperature sensor indicates that a memory module is overheated and,... Agent: International Business Machines Corporation
20130103884 - File system and control method thereof: A file system including a first memory unit which is non-volatile and has a plurality of blocks, a control unit configured to select one of the plurality of blocks of the first memory unit, determine whether the selected block is a valid block, control a data write with respect to... Agent: Samsung Electronics Co., Ltd.
20130103883 - Nonvolatile memory apparatus and write control method thereof: A nonvolatile memory apparatus includes a memory cell array, and a write operation controller configured to verify a write operation by comparing input data to the write operation controller with cell data written into the memory cell array, measure a resistance value after a first time is elapsed, and determine... Agent:
20130103890 - Calibrating memory: Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be... Agent: Micron Technology, Inc.
20130103892 - Combined memory block and data processing system having the same: A combined memory block includes a first memory unit configured to store data and an additional memory unit that forms a stacked structure with the memory unit, wherein the memory unit and the storage unit together form multi-level cells having variable resistance in storing data.... Agent:
20130103887 - Computing system with non-disruptive fast memory restore mechanism and method of operation thereof: A method for operating a computing system includes: monitoring a central interface for a power event; accessing a high-speed memory for pre-shutdown data; accessing a non-volatile memory during the power event for the pre-shutdown data previously stored on the high-speed memory; selecting a multiplexer for allowing external access to the... Agent: Smart Modular Technologies, Inc.
20130103886 - Dual-firmware for next generation emulation: Disclosed is a host bus adapter (HBA) that to receives an input/output (I/O) command from an operating system I/O driver. Firmware stored on the host bus adapter includes primary firmware and secondary firmware to process the I/O command. The HBA is to respond to the I/O command under the control... Agent:
20130103891 - Endurance enhancement coding of compressible data in flash memories: Methods described in the present disclosure may be based on a direct transformation of original data to “shaped” data. The disclosed methods may be performed “on-the-fly” and the disclosed methods may utilize an inherent redundancy in compressible data in order to achieve endurance enhancement and error reduction. In a particular... Agent: Sandisk Technologies Inc.
20130103895 - Flash memory storage system: A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among... Agent: Hitachi, Ltd
20130103888 - Memory array including multi-state memory devices: A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A memory control module may control operations of the memory array, and an encoder module may encode input data for storing to the memory array. The memory array may be... Agent:
20130103889 - Page-buffer management of non-volatile memory-based mass storage devices: Mass storage devices and methods that use at least one non-volatile solid-state memory device, for example, one or more NAND flash memory devices, that defines a memory space for permanent storage of data. The mass storage device is adapted to be operatively connected to a host computer system having an... Agent: Ocz Technology Group Inc.
20130103894 - Programming a memory device to increase data reliability: Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group... Agent: Micron Technology, Inc.
20130103893 - System comprising storage device and related methods of operation: A memory system comprises a storage device and a host. The host classifies pages stored in the storage device into a plurality of data groups according to properties of the pages, and transmits setup information regarding the classified data groups to the storage device.... Agent: Samsung Electronics Co., Ltd.
20130103898 - Driver for ddr2/3 memory interfaces: An apparatus is described that includes a combined drive and termination circuit programmable to interface to DDR2 and DDR3 memory modules. In an exemplary embodiment the apparatus includes a combined output/termination driver, an input driver and a calibration subsystem. The combined output/termination driver includes a number of pull-up circuits and... Agent: Analogies, S.a.
20130103896 - Memory module with memory stack and interface with enhanced capabilites: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory... Agent: Google Inc.
20130103897 - System and method for translating an address associated with a command communicated between a system and memory circuits: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.... Agent: Google Inc.
20130103899 - System on chip with reconfigurable sram: A system on chip includes electrical components and a first memory including memory blocks. A method of operating the system on chip includes generating an assignment of the memory blocks to the electrical components. The generating includes, initially, during a development phase of the system on chip, generating the assignment... Agent:
20130103901 - Dynamically switching command types to a mass storage drive: A method, device, and system are disclosed. In one embodiment method begins by receiving a first new mass storage disk access request. The method then determines the total number of access requests to the mass storage disk received in a window of time. If the total number of requests received... Agent:
20130103900 - Electronic system and method and apparatus for saving data thereof: An electronic system, and a method and an apparatus for saving data of the electronic system are provided. The electrical system includes a central processing unit (CPU), a temperature sensor, a first controller, a second controller, a first storage device and a second storage device. When the CPU enters a... Agent: Getac Technology Corporation
20130103902 - Method and apparatus for implementing protection of redundant array of independent disks in file system: Embodiments of the present invention disclose a method and an apparatus for implementing protection of RAID in a file system, and are applied in the field of communications technologies. In the embodiments of the present invention, after receiving a file operation request, the file system needs to determine the type... Agent: Huawei Technologies Co., Ltd.
20130103903 - Methods and apparatus for reusing prior tag search results in a cache controller: Methods and apparatus are provided for reusing prior tag search results in a cache controller. A cache controller is disclosed that receives an incoming request for an entry in the cache having a first tag; determines if there is an existing entry in a buffer associated with the cache having... Agent:
20130103904 - System and method to reduce memory access latencies using selective replication across multiple memory ports: In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated... Agent: Cavium, Inc.
20130103905 - Optimizing memory copy routine selection for message passing in a multicore architecture: In one embodiment, the present invention includes a method to obtain topology information regarding a system including at least one multicore processor, provide the topology information to a plurality of parallel processes, generate a topological map based on the topology information, access the topological map to determine a topological relationship... Agent:
20130103906 - Combining write buffer with dynamically adjustable flush metrics: In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions... Agent: Apple Inc.
20130103907 - Memory management device, memory management method, control program, and recording medium: A memory management device includes a prefetch execution unit which performs prefetching data from a first memory unit, and moving the data to a second memory unit, and an initial data preservation unit which preserves data including at least a part of the data items which are placed in the... Agent: Sony Corporation
20130103908 - Preventing unintended loss of transactional data in hardware transactional memory systems: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of... Agent: Advanced Micro Devices, Inc.
20130103909 - System and method to provide non-coherent access to a coherent memory system: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data... Agent: Cavium, Inc.
20130103910 - Cache management for increasing performance of high-availability multi-core systems: An apparatus and method for improving performance in high-availability systems are disclosed. In accordance with the illustrative embodiment, pages of memory of a primary system that are to be shadowed are initially copied to a backup system's memory, as well as to a cache in the primary system. A duplication... Agent: Avaya Inc.
20130103912 - Arrangement: An arrangement includes a first part and a second part. The first part includes a memory controller for accessing a memory, at least one first cache memory and a first directory. The second part includes at least one second cache memory configured to request access to said memory. The first... Agent: Stmicroelectronics (r&d) Ltd.
20130103911 - Method and apparatus for synchronizing a cache: An approach is provided for segmenting a cache into one or more cache segments and synchronizing the cache segments. An cache platform causes, at least in part, a segmentation of at least one cache into one or more cache segments. The cache platform further determines that at least one cache... Agent:
20130103914 - Apparatus, method, and storage medium for sampling data: A data sampling apparatus includes a plurality of first-in first-out memories and a processor that executes a procedure. The procedure includes classifying received data signals in accordance with types of the data signals; storing the classified data signals in the corresponding memories; calculating a sampling rate based on a ratio... Agent: Fujitsu Limited
20130103913 - Semiconductor storage device, system, and method: A semiconductor storage system includes: a difference determining circuit configured to determine a difference between the number of first state values of sample data written to a memory and the number of first state values of read data read from the memory; and a compensation value determining circuit configured to... Agent:
20130103915 - Secure memory access system and method: A secure memory access system and method for providing secure access to Hyper Management Mode memory ranges is presented.... Agent: Intellectual Venture Funding LLC
20130103916 - Clearing blocks of storage class memory: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class... Agent: International Business Machines Corporation
20130103917 - Efficient command mapping scheme for short data burst length memory devices: An exemplary system of the present disclosure comprises a memory controller, a command bus, a data bus, a memory device and a memory. The memory device is coupled to the memory controller by the command bus and the data bus. The memory stores instructions that when executed by the computer... Agent: Nvidia Corporation
20130103918 - Adaptive concentrating data transmission heap buffer and method: An apparatus includes a data container unloading circuit which frees a container either by discarding the contents or transmitting the contents to its destination. A data container loading circuit receives a plurality of submittals of various sizes and selects an appropriately sized free container. If no free container has sufficient... Agent: Barracuda Networks, Inc
20130103919 - Administering thermal distribution among memory modules with call stack frame size management: Administering thermal distribution among memory modules in a computing system that includes temperature sensors, where each temperature sensor measures temperature of a memory module and thermal distribution is effected by: determining, in real-time by a user-level application in dependence upon the temperature measurements of the temperature sensors, whether a memory... Agent: International Business Machines Corporation
20130103920 - File storage method and apparatus: A file storage method includes: splitting each of multiple files into one or more file block objects with different sizes; and writing the file block objects obtained from file splitting into corresponding large object storage files, wherein a preset number of large object storage files are pre-created in a storage... Agent: Huawei Technologies Co., Ltd.
20130103921 - Management method for a virtual volume across a plurality of storages: A first storage system includes a plurality of first storage devices and is coupled to a computer. A second storage system includes a plurality of second storage devices and is coupled to the first storage system. A first controller provides a thin provisioning logical volume (LU) to the computer. A... Agent: Hitachi, Ltd.
20130103922 - Method, computer program product and appartus for accelerating responses to requests for transactions involving data operations: Responding to IO requests made by an application to an operating system within a computing device implements IO performance acceleration that interfaces with the logical and physical disk management components of the operating system and within that pathway provides a system memory based disk block cache. The logical disk management... Agent:
20130103923 - Memory management unit speculative hardware table walk scheme: A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available translation-lookaside-buffer (TLB). The MMU determines whether a memory access operation associated with the given virtual address is the oldest, uncompleted memory access operation... Agent:Electrical computers and digital data processing systems: input/output
Next industry: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
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