|Electrical computers and digital processing systems: memory patents - Monitor Patents|
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Electrical computers and digital processing systems: memory June invention type 06/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 06/30/2011 > 75 patent applications in 31 patent subcategories. invention type
20110161548 - Efficient multi-level software cache using simd vector permute functionality: A cache manager receives a request for data, which includes a requested effective address. The cache manager determines whether the requested effective address matches a most recently used effective address stored in a mapped tag vector. When the most recently used effective address matches the requested effective address, the cache... Agent: International Business Machines Corporation
20110161549 - Memory control device and cache memory controlling method: A memory control device for controlling an access from a processing unit to a cache memory, the memory control device includes: an address estimation circuit for receiving a first read address of the cache memory from the processing unit and estimating a second read address on the basis of the... Agent: Fujitsu Semiconductor Limited
20110161550 - Sub-os virtual memory management layer: A binary memory image in system is modified. The system may or may not already have virtual memory management enabled. Virtual memory management is enabled and/or modified by inserting a sub-OS virtual memory management layer in the binary memory image. Part of the binary memory image may be compressed to... Agent:
20110161564 - Block management and data writing method, and flash memory storage system and controller using the same: A block management method for managing a plurality of physical blocks is provided. The method includes grouping the physical blocks into a plurality of physical units, grouping a portion of the physical units into a data area and a spare area, configuring a plurality of logical units, and grouping the... Agent: Phison Electronics Corp.
20110161563 - Block management method of a non-volatile memory: A block management method applicable to a non-volatile memory storage system is provided. The non-volatile memory storage system includes a plurality of chips. Each chip includes a plurality of physical blocks. The physical blocks form a plurality of physical block sets. Each logical block in a logical space corresponds to... Agent: National Taiwan University
20110161552 - Command tracking for direct access block storage devices: Described embodiments provide tracking and processing of commands received by a storage device. For each received command, the storage device determines one or more requested logical block addresses (LBAs), including a starting LBA and a length of one or more LBAs of the received command. The storage device determines whether... Agent: Lsi Corporation
20110161573 - Device identifiers for nonvolatile memory modules: A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user... Agent:
20110161557 - Distributed media cache for data storage systems: This disclosure is related to distributed media cache for data storage systems, such as disc drives, flash devices, or hybrid devices. In one example, a data storage device comprises a data storage medium and a controller adapted to selectively divide a media cache into a plurality of physically separate media... Agent: Seagate Technology LLC
20110161555 - Dynamic data flow management in a multiple cache architecture: The disclosure is related to systems and methods of dynamic dataflow in a multiple cache architecture. In an embodiment, a system having a data storage device with a multiple cache architecture may detect at least one attribute affecting a data storage workload or data storage performance. The system may select... Agent: Seagate Technology LLC
20110161560 - Erase command caching to improve erase performance on flash memory: Systems and methods are disclosed to reduce the number of partial logical groups that are erased by writing erase patterns to memory in a non-volatile memory system. When a non-aligned erase command is received, the logical addresses of data associated with the erase command may be marked as erased. If... Agent:
20110161572 - Executing applications from a semiconductor nonvolatile memory: A processor-based device (e.g., a wireless device) may include a processor and a semiconductor nonvolatile memory to directly execute an application (e.g., an execute-in-place application) using an associated database. Within a flash memory, in one embodiment, an executable program may be separately stored in a non-fragmented manner from a resident... Agent:
20110161571 - Flash memory device and method of programming flash memory device: A flash memory device performs a program operation using an incremental step pulse programming (ISPP) scheme comprising a plurality of program loops. In each of the program loops, a program pulse operation is performed to increase the threshold voltages of selected memory cells, and a program verify operation is performed... Agent: Samsung Electronics Co., Ltd.
20110161565 - Flash memory storage system and controller and data writing method thereof: A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to... Agent: Phison Electronics Corp.
20110161567 - Memory device for reducing programming time: A non-volatile memory device includes: first and second planes each comprising a plurality of non-volatile memory cells; first and second buffer corresponding to the first and second planes, respectively; an input/output control unit configured to selectively control input/output paths of data stored in the first and second page buffers; a... Agent: Hynix Semiconductor Inc.
20110161553 - Memory device wear-leveling techniques: The wear-leveling techniques include discovering a persistent state of one or more memory devices, or building and caching persistent state parameters for each logical unit of a given memory device if a persistent state is not discovered for a given memory device. The techniques may also include processing memory access... Agent: Nvidia Corporation
20110161569 - Memory module and method for exchanging data in memory module: The present application provides a memory module. The memory module includes one or more volatile memory devices, one or more non-volatile memory devices, and a data exchange controller. The data exchange controller controls data exchange between the volatile memory devices and the non-volatile memory devices.... Agent: Montage Technology (shanghai) Co., Ltd.
20110161554 - Method and controller for performing a sequence of commands: The embodiments described herein provide a method and controller for performing a sequence of commands. In one embodiment, a controller receives a command from a host to perform a memory operation in a flash memory device, wherein the command comprises at least one bit that indicates whether the command is... Agent:
20110161568 - Multilevel memory bus system for solid-state mass storage: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an... Agent: Bitmicro Networks, Inc.
20110161570 - Nonvolatile semiconductor memory devices, data updating methods thereof, and nonvolatile semiconductor memory systems: Integrated circuit memory devices utilize techniques to improve the timing of data update operations within a non-volatile memory, by more efficiently combining memory cell programming operations with threshold voltage adjust operations on erased memory cells. These adjust operations operate to narrow a threshold voltage distribution between memory cells that remain... Agent:
20110161559 - Physical compression of data with flat or systematic pattern: Systems and methods are disclosed to improve the performance of a memory system by freeing up physical memory areas that correspond to logical block address ranges that have repeated data patterns. A controller detects data patterns in incoming data. When a data pattern is detected, the data is not written... Agent:
20110161558 - Record sorting: A method, computer program product, and computing system for record sorting is described. The method may comprise splitting an incoming record into a separate key block and payload block. The method may further comprise storing the key block in a first memory. The method may also comprise assigning the payload... Agent:
20110161562 - Region-based management method of non-volatile memory: A region-based management method of a non-volatile memory is provided. In the region-based management method, the storage space of all chips in the non-volatile memory is divided into physical regions, physical block sets, and physical page sets, and a logical space is divided into virtual regions, virtual blocks, and virtual... Agent: National Taiwan University
20110161556 - Systems and methods for storing data in a multi-level cell solid state storage device: This disclosure is related to systems and methods for storing data in multi-level cell solid state storage devices, such as Flash memory devices. In one example, a multi-level cell memory array has programmable pages, a first page having a first programming time, and a second page having a second programming... Agent: Seagate Technology LLC
20110161551 - Virtual and hidden service partition and dynamic enhanced third party data store: A system reserves and manages a hidden service partition through components of the hardware platform of a computing device. The hidden partition is not accessible by way of a host operating system on the computing device. A hardware platform controller provisions a portion of nonvolatile storage through configuration settings of... Agent: Intel Corporation
20110161561 - Virtualization of chip enables: Virtual chip enable techniques perform memory access operations on virtual chip enables rather than physical chip enables. Each virtual chip enable is a construct that includes attributes that correspond to a unique physical or logical memory device.... Agent: Nvidia Corporation
20110161566 - Write timeout control methods for flash memory and memory devices using the same: A write timeout control method for a flash memory having a plurality of spare blocks and data blocks including a plurality of mother blocks is disclosed. The method includes the steps of: receiving a write command and a starting logical block address; determining an update mode according to a target... Agent: Silicon Motion, Inc.
20110161575 - Microcode refactoring and caching: Methods and apparatus relating to microcode refactoring and/or caching are described. In some embodiments, an off-chip structure that stores microcode is shared by multiple processor cores. Other embodiments are also described and claimed.... Agent:
20110161574 - Setting control apparatus and method for operating setting control apparatus: A setting control apparatus includes a setting control part, a special register, and a read-out control part. The setting control part makes stored in a temporary storage part a control value used in a processing circuit, in response to an input of the control value. The special register is electrically... Agent: Megachips Corporation
20110161577 - Data storage system, electronic system, and telecommunications system: A data storage system comprising a plurality of buffers configured to store data, a read pointer to indicate a particular one of the plurality of buffers from which data should be read, and a write pointer to indicate a particular one of the plurality of buffers to which data should... Agent: Micron Technology, Inc.
20110161576 - Memory module and memory system comprising memory module: A memory module comprises a plurality of semiconductor memory devices each having a termination circuit for a command/address bus. The semiconductor memory devices are formed in a substrate of the memory module, and they operate in response to a command/address signal, a data signal, and a termination resistance control signal.... Agent: Samsung Electronics Co., Ltd.
20110161579 - Method and system for minimizing impact of refresh operations on volatile memory performance: A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting... Agent: Qualcomm Incorporated
20110161578 - Semiconductor memory device performing partial self refresh and memory system including same: A semiconductor memory device capable of performing a partial self refresh and semiconductor memory system including same is provided. The semiconductor memory device includes: a memory circuit including a memory array; a skip address storage unit storing an address of an excluded region not requiring refresh in the memory array... Agent: Samsung Electronics Co., Ltd.
20110161580 - Providing dynamic databases for a tcam: A network device allocates a particular number of memory blocks in a ternary content-addressable memory (TCAM) of the network device to each database of multiple databases, and creates a list of additional memory blocks in an external TCAM of the network device. The network device also receives, by the external... Agent: Juniper Networks, Inc.
20110161581 - Semiconductor circuit apparatus: A semiconductor circuit apparatus having a commonly shared control unit that coordinates reading and writing timed activities in two ranked subcircuits is presented. The semiconductor circuit includes: first and second ranks; and a rank control block shared by the first and second ranks and configured to provide a column-related command... Agent: Hynix Semiconductor Inc.
20110161582 - Advanced disk drive power management based on maximum system throughput: The disclosed technology identifies bottlenecks in a hierarchical storage subsystem and, based upon the rate at which data may be transmitted through a particular bottleneck, determines the smallest number of disk drives required to match that transmission rate. If the required number of disks is less than the total number... Agent: International Business Machines Corporation
20110161583 - Memory card and memory system including semiconductor chips in stacked structure: A memory card and memory system are disclosed. The memory card includes a plurality of ports formed on an external surface of the memory card, a memory controller coupled to the plurality of ports and configured to communicate with an external host through the ports, and to generate a plurality... Agent:
20110161584 - System and method for inquiry caching in a storage area network: A system and method for servicing an inquiry command from a host device requesting inquiry data about a sequential device on a storage area network. The inquiry data may be cached by a circuitry coupled to the host device and the sequential device. The circuitry may reside in a router.... Agent:
20110161588 - Formation of an exclusive ownership coherence state in a lower level cache: In response to a memory access request of a processor core that targets a target cache line, the lower level cache of a vertical cache hierarchy associated with the processor core supplies a copy of the target cache line to an upper level cache in the vertical cache hierarchy and... Agent: International Business Machines Corporation
20110161591 - Increased nand flash memory read throughput: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data... Agent:
20110161587 - Proactive prefetch throttling: According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In... Agent: International Business Machines Corporation
20110161585 - Processing non-ownership load requests hitting modified line in cache of a different processor: Methods and apparatus to efficiently process non-ownership load requests hitting modified line (M-line) in cache of a different processor are described. In one embodiment, a first agent changes the state of a first data and forwards it to a second, requesting agent who stores the first data in an alternative... Agent:
20110161589 - Selective cache-to-cache lateral castouts: A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be... Agent: International Business Machines Corporation
20110161586 - Shared memories for energy efficient multi-core processors: Technologies are described herein related to multi-core processors that are adapted to share processor resources. An example multi-core processor can include a plurality of processor cores. The multi-core processor further can include a shared register file selectively coupled to two or more of the plurality of processor cores, where the... Agent:
20110161590 - Synchronizing access to data in shared memory via upper level cache queuing: A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve... Agent: International Business Machines Corporation
20110161593 - Cache unit, arithmetic processing unit, and information processing unit: A cache unit comprising a register file that selects an entry indicated by a cache index of n bits (n is a natural number) that is used to search for an instruction cache tag, using multiplexer groups having n stages respectively corresponding to the n bits of the cache index.... Agent: Fujitsu Limited
20110161592 - Dynamic system reconfiguration: In some embodiments system reconfiguration code and data to be used to perform a dynamic hardware reconfiguration of a system including a plurality of processor cores is cached and any direct or indirect memory accesses during the dynamic hardware reconfiguration are prevented. One of the processor cores executes the cached... Agent:
20110161594 - Information processing device and cache memory control device: An information processor includes processing units each processes an out-of-order memory access and includes a cache memory, an instruction port that holds instructions for accessing data in the cache memory, a first determinator that validates a first flag when a request for invalidating cache data is received after a target... Agent: Fujitsu Limited
20110161595 - Cache memory power reduction techniques: Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual... Agent:
20110161596 - Directory-based coherence caching: Techniques are generally described for methods, systems, data processing devices and computer readable media related to multi-core parallel processing directory-based cache coherence. Example systems may include one multi-core processor or multiple multi-core processors. An example multi-core processor includes a plurality of processor cores, each of the processor cores having a... Agent:
20110161597 - Combined memory including a logical partition in a storage memory accessed through an io controller: A computer system having a combined memory. A first logical partition of the combined memory is a main memory region in a storage memory. A second logical partition of the combined memory is a direct memory region in a main memory. A memory controller comprising a storage controller is configured... Agent: International Business Machines Corporation
20110161598 - Dual timeout caching: Embodiments of the present invention provide a method, system and computer program product for dual timer fragment caching. In an embodiment of the invention, a dual timer fragment caching method can include establishing both a soft timeout and also a hard timeout for each fragment in a fragment cache. The... Agent: International Business Machines Corporation
20110161600 - Arithmetic processing unit, information processing device, and cache memory control method: A processor holds, in a plurality of respective cache lines, part of data held in a main memory unit. The processor also holds, in the plurality of respective cache lines, a tag address used to search for the data held in the cache lines and a flag indicating the validity... Agent: Fujitsu Limited
20110161599 - Handling of a wait for event operation within a data processing apparatus: A data processing apparatus and method are provided for handling of a wait for event operation. The data processing apparatus forms a portion of a coherent cache system and has a master device for performing data processing operations, including a wait for event operation causing the master device to enter... Agent:
20110161601 - Inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc.... Agent:
20110161602 - Lock-free concurrent object dictionary: An object storage system comprises one or more computer processors or threads that can concurrently access a shared memory, the shared memory comprising an array of equally-sized cells. In one embodiment, each cell is of the size used by the processors to represent a pointer, e.g., 64 bits. Using an... Agent:
20110161603 - Memory transaction grouping: Various technologies and techniques are described for providing a transaction grouping feature for use in programs operating under a transactional memory system. The transaction grouping feature is operable to allow transaction groups to be created that contain related transactions. The transaction groups are used to enhance performance and/or operation of... Agent: Microsoft Corporation
20110161604 - Writer/reader/no-access domain data accessibility: Multiple types of executable agents operating within a domain. The domain includes mutable shared state and immutable shared state, with agents internal to the domain only operating on the shared state. Writer agents are defined to be agents that have read access and write access to mutable shared state and... Agent: Microsoft Corporation
20110161605 - Memory devices and methods of operating the same: A memory device includes a memory cell. The memory cell includes: a bipolar memory element and a bidirectional switching element. The bidirectional switching element is connected to ends of the bipolar memory element, and has a bidirectional switching characteristic. The bidirectional switching element includes: a first switching element and a... Agent: Samsung Electronics Co., Ltd.
20110161606 - Semiconductor memory device and method of testing the same: According to one embodiment, a nonvolatile semiconductor memory device is disclosed. The semiconductor memory device can include a first memory cell array and a second memory cell array acting in parallel each other, the first memory cell array including a plurality of first blocks and the second memory cell array... Agent: Kabushiki Kaisha Toshiba
20110161609 - Information processing apparatus and its control method: Proposed is an information processing apparatus and its control method capable of acquiring the operation results of the same point in time in a plurality of storage apparatuses in a highly reliable manner. With this information processing apparatus connected to a plurality of storage apparatuses and its control method, a... Agent: Hitachi, Ltd.
20110161608 - Method to customize function behavior based on cache and scheduling parameters of a memory argument: Disclosed are a method, a system and a computer program product of operating a data processing system that can include or be coupled to multiple processor cores. In one or more embodiments, each of multiple memory objects can be populated with work items and can be associated with attributes that... Agent: Ibm Corporation
20110161607 - Storage system and control method therefor: There is provided a storage technique for efficiently solving concentration of accesses to a particular storage medium. In the present invention, in a storage system having multiple storage media which are physically separated, duplicates of multiple blocks forming particular contents are generated, and the duplicated blocks are uniformly (in stripes)... Agent: Hitachi ,ltd.
20110161610 - Compiler-enforced agent access restriction: A compiler that enforces, at compile time, domain data access permissions and/or agent data access permissions on at least one agent to be created within a domain. The compiler identifies domain data of a domain to be created, and an agent to be created within the domain at runtime. The... Agent: Microsoft Corporation
20110161611 - Method for controlling semiconductor storage system configured to manage dual memory area: A method for controlling a semiconductor storage system configured to manage dual memory areas for protecting the system against abrupt and abnormal power disruptions is presented. The semiconductor storage systems has a first physical area and a second physical area, in which first data having a first logical block address... Agent: Paxdisk Co., Ltd.
20110161612 - Storage apparatus mounting frame, storage extension apparatus, and method of controlling storage apparatus: By having a storage apparatus attachment portion that secures a storage apparatus; a data read prevention processing unit that makes at least a part of data stored in the storage apparatus unreadable; and an input device that inputs a read prevention instruction for the storage apparatus, and configuring such that... Agent: Fujitsu Limited
20110161613 - Memory device, electronic system, and methods associated with modifying data and a file of a memory device: A memory device, system and method of editing a file in a non-volatile memory device is described. The memory device includes a controller and a memory array configured to copy an existing first file into a second file during editing and to maintain the first file while applying edits to... Agent: Micron Technology, Inc.
20110161615 - Memory management device, memory management method, and memory management program: One or more embodiments provide a technique of improving the conventional thread-local garbage collection (GC) so as to avoid fragmentation. A memory management device having a plurality of processors implementing transactional memory includes a write barrier processing unit which, when performing write barrier in response to initiation of a pointer... Agent: International Business Machines Corporation
20110161614 - Pre-leak detection scan to identify non-pointer data to be excluded from a leak detection scan: A computer-implemented method of detecting memory that may be reclaimed from application data objects that are no longer in use. When at least a first virtual memory region is newly committed for heap block storage, a pre-leak detection scan of other virtual memory regions can be performed to identify at... Agent: International Business Machines Corporation
20110161616 - On demand register allocation and deallocation for a multithreaded processor: A system for allocating and de-allocating registers of a processor. The system includes a register file having plurality of physical registers and a first table coupled to the register file for mapping virtual register IDs to physical register IDs. A second table is coupled to the register file for determining... Agent: Nvidia Corporation
20110161617 - Scalable performance-based volume allocation in large storage controller collections: A scalable, performance-based, volume allocation technique that can be applied in large storage controller collections is disclosed. A global resource tree of multiple nodes representing interconnected components of a storage system in a plurality of component layers is analyzed to yield gap values for each node (e.g., a bottom-up estimation).... Agent: International Business Machines Corporation
20110161618 - Assigning efficiently referenced globally unique identifiers in a multi-core environment: A mechanism is provided in a multi-core environment for assigning a globally unique core identifier. A Power PC® processor unit (PPU) determines an index alias corresponding to a natural index to a location in local storage (LS) memory. A synergistic processor unit (SPU) corresponding to the PPU translates the natural... Agent: International Business Machines Corporation
20110161622 - Memory access control device, integrated circuit, memory access control method, and data processing device: A memory access control unit is provided with a storage unit for storing a page table that stores a correspondence between a piece of data, a virtual page number, and a physical page number for all pages, and a conversion unit that includes a buffer for storing, for each of... Agent:
20110161621 - Micro-update architecture for address tables: Methods of maintaining an address table for mapping logical addresses to physical addresses include continuously consolidating main address maps and an update address map, and periodically compacting the update address map. Consolidating includes selecting a main address map, reading valid mapping entries from the main and update address maps, constructing... Agent:
20110161619 - Systems and methods implementing non-shared page tables for sharing memory resources managed by a main operating system with accelerator devices: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be,... Agent: Advanced Micro Devices, Inc.
20110161620 - Systems and methods implementing shared page tables for sharing memory resources managed by a main operating system with accelerator devices: Systems and methods are provided that utilize shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be,... Agent: Advanced Micro Devices, Inc.06/23/2011 > 72 patent applications in 33 patent subcategories. invention type
20110153908 - Adaptive address mapping with dynamic runtime memory mapping selection: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be... Agent: Intel Corporation
20110153909 - Efficient nested virtualization: In one embodiment of the invention, the exit and/or entry process in a nested virtualized environment is made more efficient. For example, a layer 0 (L0) virtual machine manager (VMM) may emulate a layer 2 (L2) guest interrupt directly, rather than indirectly through a layer 1 (L1) VMM. This direct... Agent:
20110153918 - Data writing method and data storage device: The invention provides a data writing method for a flash memory. First, a write command, a write address, and write data are received from a host. When a total number of block pairs in the flash memory is equal to a threshold value, and execution of the write command increases... Agent: Silicon Motion, Inc.
20110153919 - Device, system, and method for reducing program/read disturb in flash arrays: A method, device and computer readable medium for programming a nonvolatile memory block. The method may include programming information, by a memory controller, to the nonvolatile memory block by performing a sequence of programming phases of descending bit significances. The device may include a nonvolatile memory block; and a memory... Agent:
20110153920 - Electronic apparatus of recording data using non-volatile memory: An electronic apparatus for recording data using a non-volatile memory is provided. The electronic apparatus includes a non-volatile memory and a controller. The non-volatile memory stores a plurality of sets of playing information of the electronic apparatus. The controller is coupled to the non-volatile memory for receiving an input data... Agent: Sunplus Technology Co., Ltd.
20110153910 - Flash memory-interface: Flash-type memory access and control is facilitated (e.g., as random-access memory). According to an example embodiment, an interface communicates with and controls a flash memory circuit over a peripheral interface bus. The interface uses a FIFO buffer coupled to receive data from and store data for the flash memory circuit... Agent:
20110153916 - Hybrid memory architectures: Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.... Agent:
20110153912 - Maintaining updates of multi-level non-volatile memory in binary non-volatile memory: A method of operating a memory system is presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first portion, where data is stored in a binary format, and a second portion, where data is stored in a multi-state format. The... Agent:
20110153911 - Method and system for achieving die parallelism through block interleaving: A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write sequentially addressed data to the cache storage area... Agent:
20110153922 - Non-volatile memory device having assignable network identification: Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.... Agent: Micron Technology, Inc.
20110153913 - Non-volatile memory with multi-gear control using on-chip folding of data: A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format.... Agent:
20110153915 - Read preamble for data capture optimization: Systems and/or methods are provided that facilitate data capture optimization for devices accessing memories via a bus. In an aspect, a memory can output a read preamble prior to pushing data onto a bus. The read preamble can be a known sequence of one or more bits. A host device... Agent: Spansion LLC
20110153914 - Repurposing nand ready/busy pin as completion interrupt: A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.... Agent:
20110153917 - Storage apparatus and its control method: Proposed are a storage apparatus and its control method capable of performing power saving operations while covering the shortcomings of a flash memory such as the life being short and much time being required for rewriting data. This storage apparatus manages the storage areas provided by each of multiple nonvolatile... Agent: Hitachi, Ltd.
20110153921 - System embedding plural controller sharing nonvolatile memory: An embedded memory card system includes a first CPU, a second CPU, a nonvolatile memory storing data, and a device busy state machine selecting one of the first CPU and the second CPU to access the nonvolatile memory. The nonvolatile memory is accessed by the one of the first CPU... Agent:
20110153923 - High speed memory system: A high speed memory system includes a plurality of memory devices; a plurality of buffers; and a memory controller. The plurality of buffers is respectively coupled to the plurality of memory devices. The memory controller is coupled to the plurality of buffers, for generating a plurality of control signal to... Agent:
20110153926 - Controlling access to a cache memory using privilege level information: In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory... Agent:
20110153924 - Core snoop handling during performance state and power state transitions in a distributed caching agent: A method and apparatus may provide for detecting a performance state transition in a processor core and bouncing a core snoop message on a shared interconnect ring in response to detecting the performance state transition. The core snoop message may be associated with the processor core, wherein a plurality of... Agent:
20110153925 - Memory controller functionalities to support data swizzling: A memory controller that can determine a swizzling pattern between the memory controller and memory devices. The memory controller generates a swizzling map based on the determined swizzling pattern. The memory controller may internally swizzle data using the swizzling map before writing the data to memory so that the data... Agent:
20110153927 - Storage control device, electronic device, and storage control method: According to one embodiment, a storage control device includes a controller, a detector, and a refreshing module. The controller writes image data, which is to be output to a display module, to a storage device and outputs the image data from the storage device to the display module. The detector... Agent:
20110153928 - Memory utilization tracking: A hardware memory control unit that includes a register block and hardware logic. The register block includes, for a hardware memory segment, an access count register for storing an access count, a low threshold register for storing a low threshold, and a high threshold register for storing a high threshold.... Agent: Sun Microsystems, Inc.
20110153929 - Disk memory utilization management using available slot clusters: Efficient reclamation of available memory slots in a computer memory storage unit is achieved by identifying clusters of available memory spaces resulting from the deletion of a record from the storage unit. A cluster may include one or more contiguous available memory slots. An active cluster is elected by selecting... Agent: International Business Machines Corporation
20110153931 - Hybrid storage subsystem with mixed placement of file contents: A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a... Agent: International Business Machines Corporation
20110153932 - Multi-column addressing mode memory system including an integrated circuit memory device: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a... Agent: Rambus Inc.
20110153930 - Storage system and processing efficiency improving method of storage system: A storage system 200 has a storage device 240 providing a plurality of logical volumes 250 used as data storage areas of a host 100 and a plurality of MPPKs 210 executing data IO processes for the logical volumes 250 from the host 100 and, when it is determined whether... Agent: Hitachi, Ltd
20110153933 - Data storage on writeable removable media in a computing device: On a computing device making use of removable storage media, the mechanical nature of the process for removing of the media enables the device to detect the beginning of this process before it reaches the point where the removable media has been removed to the extent that it is no... Agent: Symbian Software Ltd.
20110153934 - Memory card and communication method between a memory card and a host unit: A memory card and a communication method between a memory card and a host unit are disclosed. High throughput of data between the memory card and the host unit is guaranteed by providing a communication interface between the memory card and the host unit including a first communication interface between... Agent: Stmicroelectronics Pvt. Ltd.
20110153936 - Aggregate symmetric multiprocessor system: An aggregate symmetric multiprocessor (SMP) data processing system includes a first SMP computer including at least first and second processing units and a first system memory pool and a second SMP computer including at least third and fourth processing units and second and third system memory pools. The second system... Agent: International Business Machines Corporation
20110153940 - Method and apparatus for communicating data between processors in mobile terminal: A data communication method between processors in a portable terminal and an apparatus thereof are provided. The method includes storing data to be transmitted from a first processor to a second processor in a transmission buffer, determining a size of a free space in a shared memory, sequentially transmitting the... Agent: Samsung Electronics Co. Ltd.
20110153935 - Numa-aware scaling for network devices: The present disclosure describes a method and apparatus for network traffic processing in a non-uniform memory access architecture system. The method includes allocating a Tx/Rx Queue pair for a node, the Tx/Rx Queue pair allocated in a local memory of the node. The method further includes routing network traffic to... Agent:
20110153939 - Semiconductor device, controller associated therewith, system including the same, and methods of operation: In one embodiment, the semiconductor device includes a data control unit configured to selectively process data for writing to a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a write operation, the group... Agent:
20110153937 - Systems and methods for maintaining transparent end to end cache redirection: The present disclosure presents systems and methods for maintaining original source and destination IP addresses of a request while performing intermediary cache redirection. An intermediary receives a request from a client destined to a server identifying a client IP address as a source IP address and a server IP address... Agent:
20110153938 - Systems and methods for managing static proximity in multi-core gslb appliance: The present invention is directed towards systems and methods for providing static proximity load balancing via a multi-core intermediary device. An intermediary device providing global server load balancing identifies a size of a location database comprising static proximity information. The intermediary device stores the location database to an external storage... Agent:
20110153941 - Multi-autonomous system anycast content delivery network: A content delivery network includes first and second sets of cache servers, a domain name server, and an anycast island controller. The first set of cache servers is hosted by a first autonomous system and the second set of cache servers is hosted by a second autonomous system. The cache... Agent: At&t Intellectual Property I, L.p.
20110153943 - Aggregate data processing system having multiple overlapping synthetic computers: A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth... Agent: International Business Machines Corporation
20110153945 - Apparatus and method for controlling the exclusivity mode of a level-two cache: A method of controlling the exclusivity mode of a level-two cache includes generating level-two cache exclusivity control information at a processor in response to an exclusivity mode indicator, and utilizing the level-two cache exclusivity control information to configure the exclusivity mode of the level-two cache.... Agent: Mips Technologies, Inc.
20110153942 - Reducing implementation costs of communicating cache invalidation information in a multicore processor: A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache including lower-level cache lines, where each of the lower-level cache lines may be configured to store data that corresponds to multiple higher-level cache lines. In... Agent:
20110153944 - Secure cache memory architecture: A variety of circuits, methods and devices are implemented for secure storage of sensitive data in a computing system. A first dataset that is stored in main memory is accessed and a cache memory is configured to maintain logical consistency between the main memory and the cache. In response to... Agent:
20110153946 - Domain based cache coherence protocol: Briefly stated, technologies are generally described for accessing a data block in a cache with a domain based cache coherence protocol. A first processor in a first tile and first domain can be configured to evaluate a request to access the data block. A cache in a second tile in... Agent:
20110153947 - Informaton processing device and information processing method: In an information processing device for processing VLIW includes memory banks, a memory banks are used to store an instruction word group constituting a very-long instruction. A program counter outputs an instruction address indicating a head memory bank containing a head part of the very long instruction of the next... Agent:
20110153948 - Systems, methods, and apparatus for monitoring synchronization in a distributed cache: Systems, apparatus, and method of monitoring synchronization in a distributed cache are described. In an exemplary embodiment, a first and second processing core process a first and second thread respectively. A first and second distributed cache slices store data for either or both of the first and second processing cores.... Agent:
20110153950 - Cache memory, cache memory system, and method program for using the cache memory: A cache memory includes: a plurality of MSHRs (Miss Status/Information Holding Registers); a memory access identification unit that identifies a memory access included in an accepted memory access request; and a memory access association unit that associates a given memory access with the MSHR that is used when the memory... Agent:
20110153949 - Delayed replacement of cache entries: A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry for replacement (“a replacement entry”) based on a generic replacement technique. If the replacement entry is an entry that... Agent: International Business Machines Corporation
20110153951 - Global instructions for spiral cache management: A pipelined cache memory and a method of operation support global operations within the cache. The cache may be a spiral cache, with a move-to-front M2F network for moving values from a backing store to a front-most tile coupled to a processor or lower-order level of a memory hierarchy and... Agent: International Business Machines Corporation
20110153952 - System, method, and apparatus for a cache flush of a range of pages and tlb invalidation of a range of entries: Systems, methods, and apparatus for performing the flushing of a plurality of cache lines and/or the invalidation of a plurality of translation look-aside buffer (TLB) entries is described. In one such method, for flushing a plurality of cache lines of a processor a single instruction including a first field that... Agent:
20110153953 - Systems and methods for managing large cache services in a multi-core system: A multi-core system that includes a 64-bit cache storage and a 32-bit memory storage that stores a 32-bit cache object directory. One or more cache engines execute on cores of the multi-core system to retrieve objects from the 64-bit cache, create cache directory objects, insert the created cache directory object... Agent:
20110153954 - Storage subsystem: Provided is a storage subsystem capable of speeding up the input/output processing for a cache memory. Microprocessor Packages manage information related to a VDEV ownership for controlling virtual devices and a cache segment ownership for controlling cache segments in units of Microprocessor Packages, and one Microprocessor among multiple Microprocessors belonging... Agent: Hitachi, Ltd.
20110153956 - Cache coherent switch device: In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the... Agent:
20110153955 - Software assisted translation lookaside buffer search mechanism: A computer implemented method searches a unified translation lookaside buffer. Responsive to a request to access the unified translation lookaside buffer, a first order code within a first entry of a search priority configuration register is identified. A unified translation lookaside buffer is then searched according to the first order... Agent: International Business Machines Corporation
20110153958 - Network load reducing method and node structure for multiprocessor system with distributed memory: Provided are a network load reducing method and a node structure for a multiprocessor system with a distributed memory. The network load reducing method uses a multiprocessor system including a node having a distributed memory and an auxiliary memory storing a sharer history table. The network load reducing method includes... Agent: Electronics And Telecommunications Research Institute
20110153957 - Sharing virtual memory-based multi-version data between the heterogenous processors of a computer platform: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit) GPU and a shared virtual memory supported by a physical private memory space of at least one heterogeneous... Agent:
20110153959 - Implementing data storage and dual port, dual-element storage device: A method for implementing data storage and a dual port, dual element storage device are provided. A storage device includes a predefined form factor including a first port and a second port, and a first storage element and a second storage element. A controller coupled between the first port and... Agent: Hitachi Global Storage Technologies Netherlands B.v.
20110153961 - Storage device with function of voltage abnormal protection and operation method thereof: The present invention discloses a storage device and an operation method thereof. The storage device includes a non-volatile memory for storing data, a control unit coupled to the non-volatile memory, a power supply unit coupled to an external power source and converting the external power source to a suitable voltage... Agent: A-data Technology (suzhou) Co., Ltd.
20110153960 - Transactional memory in out-of-order processors with xabort having immediate argument: Methods, systems, and apparatuses to provide an XABORT in a transactional memory access system are described. In one embodiment, the stored value is a context value indicating the context in which a transactional memory execution was aborted. A fallback handler may use the context value to perform a series of... Agent:
20110153962 - Endless memory: A storage device includes a controller that is configured to execute safe deletion operations so as to free up storage space on the device in response to triggering events. The safe deletion operations ensure that the data states of a host device making use of the storage device and the... Agent:
20110153963 - Memory controller and associated control method: A memory controller and an associated controlling method are provided. The memory controller is connected to a memory module, and includes a FIFO buffer for receiving valid data outputted from the memory module, a write pointer for indicating written data stored in the FIFO buffer, and a read pointer for... Agent: Mstar Semiconductor, Inc.
20110153968 - Data duplication control method: When there is a change in a group of volumes managed by a host computer, data duplication processing is immediately carried out against the changed volume. The host computer includes a volume-managing portion, a data duplication-controlling portion which executes the data duplication of data stored in a volume in a... Agent:
20110153964 - Prioritizing subgroups in a consistency group: A method which prioritizes the subgroups in a consistency group by usage and/or business process. Thereafter, in case of abnormal operation of the process for copying the consistency group from primary storage to secondary storage, only a portion of the subgroups of the consistency group are copied from primary storage... Agent: International Business Machines Corporation
20110153967 - Storage area dynamic assignment method: A storage system allocates a data storage area in response to an access request from a first computer if the capacity of a first physical storage device configuring a first logical storage area, provided to the first computer, is equal to or lower than a predetermined threshold. The storage system... Agent:
20110153966 - Storage controller and data management method: Upon receiving a primary/secondary switching command from a secondary host system, a secondary storage control device interrogates a primary storage control device as to whether or not yet to be transferred data that has not been remote copied from the primary storage control device to the secondary storage control device... Agent: Hitachi, Ltd.
20110153965 - Systems and methods for virtualizing storage systems and managing data independently: Method, data processing systems, and computer program products are provided for virtualizing and managing a storage virtualization system (SVS) in a storage management architecture. Source data is copied from the source storage media to target data in a target storage media based on a predefined copy policy in a copy... Agent: International Business Machines Corporation
20110153969 - Device and method to control communications between and access to computer networks, systems or devices: A network security device and method for one way or secure communication are disclosed. At least one processor is connected to a higher level network port and a lower level network port, and is connectable to a shared memory. The at least one processor is configured to send a data... Agent:
20110153970 - Method and apparatus for the execution of a program: An apparatus and a method is provided for the execution of a program by a program-controlled device, in which the program-controlled device receives instructions and automatically executes the program if it receives an access instruction for accessing a protected memory area. The invention further relates to a programmable transponder containing... Agent:
20110153971 - Data processing system memory allocation: The present invention provides a data processing system with multiple logical partitions that isolate memory resources for applications contained in the logical partitions. A method is provided for moving a specific memory quantity between two logical partitions by first computing a threshold amount. Then, if the specific memory quantity to... Agent: International Business Machines Corporation
20110153972 - Free space defragmention in extent based file system: Example apparatus, methods, data structures, and computers defragment unallocated space in a storage associated with an extent based file system. One example method locates a first unallocated area having a desired size and a desired location to receive an extent from a first end of an allocated area in the... Agent: Quantum Corporation
20110153973 - Hybrid solid-state memory system having volatile and non-volatile memory: A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is... Agent: Mosaid Technologies Incorporated
20110153974 - System and method of operating memory devices of mixed type: A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a... Agent: Mosaid Technologies Incorporated
20110153975 - Method for prioritizing virtual real memory paging based on disk capabilities: A method manages memory paging operations. Responsive to a request to page out a memory page from a shared memory pool, the method identifies whether a physical space within one of a number of paging space devices has been allocated for the memory page. If physical space within the paging... Agent: International Business Machines Corporation
20110153976 - Methods and apparatuses to allocate file storage via tree representations of a bitmap: Methods and apparatuses that search tree representations of a bitmap for available blocks to allocate in storage devices are described. An allocation request for a file may be received to initiate the search. In one embodiment, the bitmap may include an array of bits corresponding to blocks in the storage... Agent:
20110153978 - Predictive page allocation for virtual memory system: A virtual memory method for allocating physical memory space required by an application by tracking the page space used in each of a sequence of invocations by an application requesting memory space; keeping count of the number of said invocations; and determining the average page space used for each of... Agent: International Business Machines Corporation
20110153977 - Storage systems and methods: Systems and methods for information storage replication are presented. In one embodiment a storage flow control method includes receiving a memory operation indication; performing a pre-reserve allocation process before proceeding with the memory operation, wherein the pre-reserve allocation process includes converting available unallocated memory space to allocated memory space if... Agent: Symantec Corporation
20110153979 - Modified b+ tree to store nand memory indirection maps: Embodiments of the invention generally pertain to memory devices and more specifically to reducing the write amplification of memory devices without increasing cache requirements. Embodiments of the present invention may be represented as a modified B+ tree in that said tree comprises a multi-level tree in which all data items... Agent:06/16/2011 > 72 patent applications in 28 patent subcategories. invention type
20110145471 - Method for efficient guest operating system (os) migration over a network: A method, data processing system and computer program product enables efficient transfer of a virtual machine from a first data processing system (DPS) to a second DPS using a combination of Transmission Control Protocol (TCP) and Uniform Data Protocol (UDP). A virtual machine migration (VMM) utility identifies all memory pages... Agent: Ibm Corporation
20110145482 - Block management method for flash memory, and flash memory controller and flash memory storage device using the same: A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition.... Agent: Phison Electronics Corp.
20110145490 - Device and method of controlling flash memory: Disclosed is a flash memory controlling method and controlling device. The flash memory controlling method including calculating a cost for each of available block recycling schemes based on a multi-block erase function when the multi-block erase function is supported, the multi-block erase function being a function that simultaneously erases data... Agent:
20110145474 - Efficient use of flash memory in flash drives: A data storage device having non-volatile solid state memory permits efficient access by permitting multiple pending commands from a host device. A controller in the data storage device stores information about each command from the host device, and determines which stored command, if any, is presently able to be performed... Agent: Symwave, Inc.
20110145479 - Efficient use of hybrid media in cache architectures: A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized... Agent: Gear Six, Inc.
20110145484 - Exhaustive parameter search algorithm for interface with nand flash memory: The Exhaustive Parameter Search (EPS) algorithm of this invention enables communicating devices to access to a large variety of NAND Flash memories. The EPS algorithm exploits the fact that the parameters needed for successful initial communication with NAND Flash memory (block Size and page Size) have only few possible values.... Agent: Texas Instruments Incorporated
20110145473 - Flash memory cache for data storage device: A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device includes a controller configured to manage the cache by consolidating information concerning obsolete data stored in the cache with information... Agent: Nimble Storage, Inc.
20110145481 - Flash memory management method and flash memory controller and storage system using the same: A flash memory management method for managing a plurality of physical units of a flash memory chip is provided. The flash memory management method includes grouping a portion of the physical units into a data area and a spare area; configuring a plurality of logical units and setting mapping relationships... Agent: Phison Electronics Corp.
20110145488 - Flash memory module, storage apparatus using flash memory module as recording medium and address translation table verification method for flash memory module: A purpose of the invention is to immediately return the operation in a flash memory module from low power consumption mode to regular mode. A flash memory controller having memory that stores an address translation table for translating between a logical page address and a physical page address in the... Agent: Hitachi, Ltd.
20110145480 - Flash memory storage system for simulating rewritable disc device, flash memory controller, computer system, and method thereof: A flash memory storage system including a flash memory chip, a connector, and a controller is provided. The flash memory chip has a plurality of physical blocks. The connector is configured to couple to a host system. The controller is coupled to the flash memory chip and the connector. The... Agent: Phison Electronics Corp.
20110145477 - Flash translation layer using phase change memory: A FLASH translation layer (FTL) includes a translation table that is maintained in non-FLASH memory. The translation table maps logical addresses to physical addresses and may be maintained in phase change memory (PCM). A bad block table (BBT) may also be maintained in non-FLASH memory.... Agent:
20110145489 - Hybrid storage device: A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one... Agent: Super Talent Electronics, Inc.
20110145486 - Memory management device and method: According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level... Agent:
20110145472 - Method for address space layout randomization in execute-in-place code: A method for dynamically (i.e., upon boot) rewriting, in a failure resistant manner, of part of, or the entirety of, the flash memory for a device allows for a changing of location for logical blocks of execute-in-place code. Conveniently, the rewriting results in a randomization, of varying degree, of the... Agent: Research In Motion Limited
20110145485 - Method for managing address mapping table and a memory device using the method: An address mapping table includes arrays each being allocated to a logical address and in which a physical address mapping the logical address is stored. In the case where the physical address mapped to the logical address is changed, a value of a difference between a pre-changed physical address and... Agent: Samsung Electronics Co., Ltd.
20110145478 - Method to improve a solid state disk performance by using a programmable bus arbiter: A method to improve a solid state disk performance by using a programmable bus arbiter is generally presented. In this regard, in one embodiment, a method is introduced comprising delaying a request from a solid state drive for access to an interface for a time to allow a host to... Agent:
20110145487 - Methods and apparatus for soft demapping and intercell interference mitigation in flash memories: Methods and apparatus are provided for soft demapping and intercell interference mitigation in flash memories. In one variation, a target cell in a flash memory device capable of storing at least two data levels, s, per cell is read by obtaining a measured read value, r, for at least one... Agent: Lsi Corporation
20110145476 - Persistent content in nonvolatile memory: Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations. Persistent storage may be maintained by systems with or without memory management units.... Agent:
20110145475 - Reducing access contention in flash-based memory systems: Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting... Agent: International Business Machines Corporation
20110145483 - Semiconductor memory device and method of processing data for erase operation of semiconductor memory device: A semiconductor memory device comprises a plurality of memory blocks, and erase flag storage block storing erase flag information to indicate erase states of the plurality of memory blocks. The erase flag information can be used to monitor completion of erase operations of the memory blocks and to update erase... Agent: Samsung Electronics Co., Ltd.
20110145491 - Method for controlling access to regions of a memory from a plurality of processes and a communication module having a message memory for implementing the method: A method for controlling access to regions of a memory from a plurality of processes. In order to allow a plurality of processes to access the most recent data packets stored in the memory without any loss of data and without a waiting period, according to the present invention a... Agent:
20110145493 - Independently controlled virtual memory devices in memory modules: Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module (500) includes at least one virtual memory device and a demultiplexer register (502) disposed between the at least one virtual memory device and a memory controller. The demultiplexer register receives a command... Agent:
20110145492 - Polymorphous signal interface between processing units: A single interconnect is provided between a first processor and a second processor, such that the first processor may access a common memory through the second processor while the second processor can be mostly powered off. The first processor accesses the memory through a memory controller using a standard dynamic... Agent: Advanced Micro Devices, Inc.
20110145494 - Virtual tape server and method for controlling tape mounting of the same: A method of a virtual tape server (VTS) for processing a mount request from a host system, the method comprising the steps of receiving a logical-volume (LVOL) mount request from the host system using a virtual-tape drive (VTD) of the virtual tape server; determining whether the logical volume is present... Agent: International Business Machines Corporation
20110145496 - Trace-assisted startup optimization from a virtual disk: The disclosed embodiments provide a system that manages the use of a virtual disk. During operation, the system obtains trace data associated with a startup process that reads blocks from the virtual disk. Next, the system physically rearranges the blocks based on the trace data to increase the speed of... Agent: Moka5, Inc.
20110145495 - Virtual volume control method involving device stop: Provided is a storage system capable of starting/stopping a disk drive. At the time of allocating a logical device, it is judged, based on attributes including a purpose of the logical device, whether or not control can be performed in terms of start/stop of an allocation target disk drive to... Agent:
20110145497 - Cluster families for cluster selection and cooperative replication: An apparatus, system, and method are disclosed to create cluster families for cluster selection and cooperative replication. The clusters are grouped into family members of a cluster family base on their relationships and roles. Members of the cluster family determine which family member is in the best position to obtain... Agent: International Business Machines Corporation
20110145499 - Asynchronous file operations in a scalable multi-node file system cache for a remote cluster file system: Asynchronous file operations in a scalable multi-node file system cache for a remote cluster file system, is provided. One implementation involves maintaining a scalable multi-node file system cache in a local cluster file system, and caching local file data in the cache by fetching file data on demand from the... Agent: International Business Machines Corporation
20110145498 - Instrumentation of hardware assisted transactional memory system: Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods... Agent: Microsoft Corporation
20110145500 - Semiconductor device and data processing system: A high-speed, low-cost data processing system capable of ensuring expandability of memory capacity and having excellent usability while keeping constant latency is provided. The data processing system is configured to include a data processing device, a volatile memory, and a non-volatile memory. As the data processing device, the volatile memory,... Agent:
20110145501 - Cache spill management techniques: An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful cache lines from a source cache are intelligently selected for spill. Furthermore, another learning mechanism—cache spill prediction—may be implemented separately... Agent:
20110145502 - Meta-data based data prefetching: A technique for prefetching data into a cache memory system includes prefetching data based on meta information indicative of data access patterns. A method includes tagging data of a program with meta information indicative of data access patterns. The method includes prefetching the data from main memory at least partially... Agent:
20110145503 - On-line optimization of software instruction cache: A method for computing includes executing a program, including multiple cacheable lines of executable code, on a processor having a software-managed cache. A run-time cache management routine running on the processor is used to assemble a profile of inter-line jumps occurring in the software-managed cache while executing the program. Based... Agent: International Business Machines Corporation
20110145504 - Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules: Various embodiments of the present invention are directed multi-core memory modules. In one embodiment, a memory module (500) includes memory chips, and a demultiplexer register (502) electronically connected to each of the memory chips and a memory controller. The memory controller groups one or more of the memory chips into... Agent:
20110145505 - Assigning cache priorities to virtual/logical processors and partitioning a cache according to such priorities: Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. The mechanisms identify a plurality of high priority... Agent: International Business Machines Corporation
20110145506 - Replacing cache lines in a cache memory: In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the... Agent:
20110145508 - Automatic determination of read-ahead amount: Read-ahead of data blocks in a storage system is performed based on a policy. The policy is stochastically selected from a plurality of policies in respect to probabilities. The probabilities are calculated based on past performances, also referred to as rewards. Policies which induce better performance may be given precedence... Agent: International Business Machines Corporation
20110145509 - Cache directed sequential prefetch: A technique for performing stream detection and prefetching within a cache memory simplifies stream detection and prefetching. A bit in a cache directory or cache entry indicates that a cache line has not been accessed since being prefetched and another bit indicates the direction of a stream associated with the... Agent: International Business Machines Corporation
20110145507 - Method of reducing response time for delivery of vehicle telematics services: A method of operating a predictive data cache includes receiving a request for telematics service from a telematics service requester, determining the subject matter of the request, querying a predictive data cache to determine if the predictive data cache includes a service response to the subject matter of the request... Agent: General Motors LLC
20110145512 - Mechanisms to accelerate transactions using buffered stores: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block... Agent:
20110145511 - Page invalidation processing with setting of storage key to predefined value: Processing within a multiprocessor computer system is facilitated by: setting, in association with invalidate page table entry processing, a storage key at a matching location in central storage of a multiprocessor computer system to a predefined value; and subsequently executing a request to update the storage key to a new... Agent: International Business Machines Corporation
20110145510 - Reducing interprocessor communications pursuant to updating of a storage key: Processing within a multiprocessor computer system is facilitated by: deciding by a processor, pursuant to processing of a request to update a previous storage key to a new storage key, whether to purge the previous storage key from, or update the previous storage key in, local processor cache of the... Agent: International Business Machines Corporation
20110145513 - System and method for reduced latency caching: A reduced latency memory system that prevents memory bank conflicts. The reduced latency memory system receives a read request and write request. The read request is then handled by simultaneously fetching data from a main memory and a cache memory. The address of the read request is compared with a... Agent:
20110145514 - Method and apparatus for inter-processor communication in mobile terminal: A method for inter-processor communication in a mobile terminal is disclosed. The method of inter-processor communication for a mobile terminal having a first processor, a second processor, and a shared memory includes determining, by the first processor, the size of data to be sent to the second processor, comparing the... Agent: Samsung Electronics Co. Ltd.
20110145515 - Method for modifying a shared data queue and processor configured to implement same: According to one exemplary embodiment, a method for modifying a shared data queue accessible by a plurality of processors comprises receiving an instruction from one of the processors to produce a modification to the shared data queue, running a microcode program in response to the instruction, to attempt to produce... Agent: Advanced Micro Devices, Inc.
20110145516 - Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadata: A method and apparatus for accelerating a Software Transactional Memory (STM) system is herein described. A data object and metadata for the data object may each be associated with a filter, such as a hardware monitor or ephemerally held filter information. The filter is in a first, default state when... Agent:
20110145520 - Audio signal processing apparatus and method, and communication terminal apparatus: A signal processing technology achieved in a signal processing module, which is physically separate from a control module for controlling overall operations of a signal processing apparatus, is provided. Input of new data to a system memory is recognized. Upon the recognition of the input of the new data, the... Agent: Electronics And Telecommunications Research Institute
20110145521 - Data processing semiconductor device: In a data processing semiconductor device, a control unit which controls reading, writing, or erasing of data in a rewritable nonvolatile memory area has an operation mode that, referring to the input temperature data, controls a temperature range in which writing or erasing of data is performed to be narrower... Agent: Renesas Electronics Corporation
20110145519 - Data writing apparatus and data writing method: According to one embodiment, a data writing apparatus includes a memory and write module. The memory includes a storage area including a physical block having a data area and redundancy area. The write module is configured to write a data block obtained by dividing data, in the data area of... Agent: Kabushiki Kaisha Toshiba
20110145517 - Dynamic reuse and reconfiguration of logical data objects in a virtual tape system: An embodiment of the invention comprises a virtual tape system supporting at least one Write Once Read Many (WORM) logical tape and at least one read-write logical tape, comprising a processor configured to a first task and/or a second task. The first task initializes a new logical data object from... Agent: International Business Machines Corporation
20110145522 - Memory command delay balancing in a daisy-chained memory topology: A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay... Agent:
20110145518 - Systems and methods for using pre-computed parameters to execute processes represented by workflow models: Systems and methods consistent with the invention may include initiating an execution of the business process, the business process being represented by a workflow model that includes a synchronization point, retrieving, from a memory device of the computer system, a pre-computed parameter corresponding to the workflow model, and executing, using... Agent: Sap Ag
20110145523 - Eliminating duplicate data by sharing file system extents: A hardware and/or software facility to enable emulated storage devices to share data stored on physical storage resources of a storage system. The facility may be implemented on a virtual tape library (VTL) system configured to back up data sets that have a high level of redundancy on multiple virtual... Agent: Netapp, Inc.
20110145524 - Information recording medium, information recording device, information recording method, information reproducing device, and information reproducing method: According to the present invention, the size of defect management information is reduced by using a top spare area 102 and middle spare areas 103 in the ascending order of their physical block addresses and spare areas can be expanded more easily by using only the last spare area 104... Agent:
20110145525 - Method and system for storing and operating on advanced historical access data: Storing and operating an information object. An indicator associated with the information object is read. The indicator indicates that a historical information is stored for the information object. Responsive to determining from the historical information that the information object has been historically accessed, (a) future access time based on the... Agent: International Business Machines Corporation
20110145526 - Cloud scale directory services: Embodiments described herein are directed to providing scalability to software applications. A computer system partitions a portion of data stored in a directory services system into multiple different data partitions. Each data partition includes a primary writable copy and at least one secondary read-only copy of the data. The computer... Agent: Microsoft Corporation
20110145527 - Consistency without ordering dependency: Aspects of the subject matter described herein relate to maintaining consistency in a storage system. In aspects, one or more objects may be updated in the context of a transaction. In conjunction with updating the objects, logical copies of the objects may be obtained and modified. A request to write... Agent: Microsoft Corporation
20110145529 - Controller: A controller includes a first judging part that judges abnormality of a first memory part, and a second judging part that judges abnormality of a second memory part based on (1) results of comparing with each other data having a same content written in the second memory part multiple times,... Agent: Fujitsu Ten Limited
20110145528 - Storage apparatus and its control method: Proposed are a storage apparatus and its control method capable of restoring data of a virtual page to an appropriate device hierarchy according to its data value. This storage apparatus stores, in a backup-destination storage medium, data stored in the respective physical pages allocated with the virtual volume and management... Agent: Hitachi Computer Peripherals Co., Ltd.
20110145531 - Information processing apparatus and memory protection method: A memory protection method of dividing the address space of a memory into two or more protection regions, and protecting the memory from an unauthorized access to a protection region by a program includes a definition step of defining the relation between protection regions, a determination step of, when the... Agent: Canon Kabushiki Kaisha
20110145530 - Leveraging memory isolation hardware technology to efficiently detect race conditions: One embodiment includes method acts for detecting race conditions. The method includes beginning a critical section, during which conflicting reads and writes should be detected to determine if a race condition has occurred. This is performed by executing at a thread one or more software instructions to place a software... Agent: Microsoft Corporation
20110145533 - Method, arrangement, data processing program and computer program product for exchanging message data in a distributed computer system: A method for exchanging message data in a distributed computer system between a sending and a receiving hardware system. The sending hardware system includes a first memory system and a receiving hardware system which includes a second memory system with a second data buffer and a second memory region. The... Agent: International Business Machines Corporation
20110145532 - Storage system and processing efficiency improving method of storage system: A storage system 200 has a storage device 240 providing a plurality of logical volumes 250 used as data storage areas of a host 100 and a plurality of MPPKs 210 executing data IO processes for the logical volumes 250 from the host 100 and, when it is determined whether... Agent: Hitachi, Ltd.
20110145534 - Efficient loading of data into memory of a computing system: A method for deploying one or more virtual machines on a host computing system is provided. The method comprises receiving mapping information from a data storage system. The mapping information associates a first data chunk stored in the data storage system with a unique identifier to support deployment of a... Agent: International Business Machines Corporation
20110145535 - Method for rearranging logical volume: A method for rearranging a logical volume including arranging a logical volume rearranging program on a particular server and using the logical volume rearranging program to acquire server/storage mapping information from each server and performance information from each storage subsystem. Moreover, the logical volume rearranging program acquires request I/O performance... Agent:
20110145537 - Data storage management in heterogeneous memory systems: A data storage management system is provided, which includes multiple storage entities with differing storage characteristics. A controller is communicatively coupled to each of the multiple storage entities. The controller is configured to associate one or more storage attributes of a received object with one or more of the different... Agent: Seagate Technology LLC
20110145539 - Memory allocation in a broker system: Memory allocation in a Broker system for managing the communication between a plurality of clients and a plurality of servers. The method may include allocating memory for a plurality of memory pools; and dividing each memory pool into memory blocks of a size which is specific to the type of... Agent:
20110145536 - Memory leak detection during dynamic memory allocation: A method to detect memory leaks during dynamic memory allocation comprises generating statistical information regarding allocated chunks in a memory heap during a dynamic memory allocation process, with the statistical information including same-sized chunk information related to the number of allocated chunks being identical in size. The statistical information is... Agent:
20110145538 - Storage region management method, storage region allocation method and program: A storage area management method for a data storage apparatus partitions an acquired storage area into storage areas with differing power-of-2 sizes and manages each of them. Also, a storage area allocation method receives an allocation request for a storage area that includes a requested allocation size, and acquires an... Agent: S. Grants Co., Ltd.
20110145540 - Dynamically reallocating computing components between partitions: Systems, methods and computing components are provided for dynamically reallocating a plurality of computing components among one or more logical partitions. A first computing component that is allocated to a first partition may have a management processor. A second computing component may be allocated to a second partition. The management... Agent:
20110145541 - Method and system to accelerate address translation: In a method to accelerate address translation into a physical address, a computer maps a virtual memory area with a large page, the virtual memory area including multiple virtual pages satisfying a predetermined condition and being handled in units of pages, the large page having a larger area than each... Agent: International Business Machines Corporation
20110145542 - Apparatuses, systems, and methods for reducing translation lookaside buffer (tlb) lookups: Circuits and related systems and methods for providing virtual address translation are disclosed. In one embodiment, a circuit comprises a comparator configured to receive as an input a current virtual address and a current attribute associated with the current virtual address, and a prior physical address and a prior virtual... Agent: Qualcomm Incorporated06/09/2011 > 51 patent applications in 29 patent subcategories. invention type
20110138101 - Maintaining data coherence by using data domains: A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain,... Agent: International Business Machines Corporation
20110138100 - Method and system for concurrent background and foreground operations in a non-volatile memory array: A method and system for permitting host write operations in one part of a flash memory concurrently with another operation in a second part of the flash memory is disclosed. The method includes receiving data at a front end of a memory system, selecting at least one of a plurality... Agent:
20110138102 - Data storage management using a distributed cache scheme: A method for accessing data stored in a distributed storage system is provided. The method comprises determining whether a copy of first data is stored in a distributed cache system, where data in the distributed cache system is stored in free storage space of the distributed storage system; accessing the... Agent: International Business Machines Corporation
20110138116 - Direct-attached/network-attached storage device: A multi-port data storage device that can be used simultaneously by both a direct-attached device and a network-attached device, comprising a hard disk drive (HDD), a DAS port, an NAS port, and a controller for controlling access to the HDD by the DAS port and the NAS port.... Agent:
20110138106 - Extending ssd lifetime using hybrid storage: A hybrid storage device uses a write cache such as a hard disk drive, for example, to cache data to a solid state drive (SSD). Data is logged sequentially to the write cache and later migrated to the SSD. The SSD is a primary storage that stores data permanently. The... Agent: Microsoft Corporation
20110138111 - Flash memory device and method of programming same: A flash memory device comprises a memory cell array comprising memory cells arranged in rows and columns. A first page of data is programmed in selected memory cells of the memory cell array, and a second page of data is subsequently programmed in the selected memory cells. The first page... Agent: Samsung Electronics Co., Ltd.
20110138103 - Intra-block memory wear leveling: A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones... Agent: International Business Machines Corporation
20110138117 - Memory controller, nonvolatile storage device, accessing device, nonvolatile storage system, and method and program for writing data: A digital still camera performs temporary high-speed writing when capturing a large number of images in a short time. Lengthy processing for erased block allocation or copying performed inside a nonvolatile storage device may disable the captured images to be written completely (may cause some frames to drop). A nonvolatile... Agent:
20110138110 - Method and control unit for performing storage management upon storage apparatus and related storage apparatus: A storage apparatus has a first storage unit and a second storage unit. A method for performing storage management upon the storage apparatus includes: storing an input data into the first storage unit; and, while the input data is being stored into the first storage unit, checking whether the input... Agent:
20110138109 - Method for wear-leveling and apparatus thereof: A method for Wear-Leveling includes: utilizing a comparison circuit to compare an average erase count with an erase count of a first data block; and utilizing a first free block as a replacement for storing data content of the first data block so as to make the first data block... Agent:
20110138108 - Method of active flash management, and associated memory device and controller thereof: A method of active Flash management is provided. The method is applied to a controller of a memory device, where the controller is utilized for accessing a Flash memory in the memory device, and the Flash memory includes a plurality of blocks. The method includes: extracting high level information of... Agent:
20110138114 - Methods and apparatus for interfacing between a flash memory controller and a flash memory array: Methods and apparatus are provided for interfacing between a flash memory controller and a flash memory array. The interface comprises a communication channel between the flash memory controller and the flash memory array, wherein the communication channel carries data for a target cell in the flash memory array on a... Agent:
20110138104 - Multi-write coding of non-volatile memories: Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code... Agent: International Business Machines Corporation
20110138105 - Non-volatile memories with enhanced write performance and endurance: Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously... Agent: International Business Machines Corporation
20110138113 - Raid storage systems having arrays of solid-state drives and methods of operation: RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data... Agent: Ocz Technology Group, Inc.
20110138115 - Solid state memory (ssm), computer system including an ssm, and method of operating an ssm: In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the... Agent: Samsung Electronics Co., Ltd.
20110138107 - Usb non-volatile memory system for an electronic engine controller: An electronic engine controller has a processor, a data controller, and a non-volatile memory. During an engine operation, power is supplied to the processor, data controller, and non-volatile memory from an engine power source. Sensor data is received at the processor which supplies the sensor data to the data controller.... Agent: Hamilton Sundstrand Corporation
20110138112 - Virtualization of storage devices: Systems and techniques relating to storage technologies are described. A described technique includes operating drives such as a solid state drive (SSD) and a disk drive, where the SSD and the disk drive are virtualized as a single logical drive having a logical address space, where the logical drive maps... Agent:
20110138118 - Memory disc composition method and apparatus using main memory: Provided is a memory disc composition method and apparatus using a main memory. The memory disc composition method configures a disc using the main memory in an x86 based Linux operating system (OS) by excluding an area to be used by the OS from the main memory and fixing a... Agent: Electronics And Telecommunications Research Institute
20110138119 - Storage control system including virtualization and control method for same: The storage system includes a plurality of storage devices and a controller that manages a virtual volume including a plurality of virtual storage areas, and manages a storage pool including a plurality of storage areas prepared on the storage devices in order to allocate a storage area in the storage... Agent: Hitachi, Ltd.
20110138120 - Information processor, and optical disc drive used in information processor: The speed of recording or reproduction of data to or from an HDD in an information processor is increased. This is achieved without an increase in device size, system changes, or other inconvenience. A cache memory configured by, for example, a flash memory for the data to be recorded to... Agent:
20110138121 - Card reader: The present invention discloses a card reader comprising a plurality of card slots for inserting the memory cards, and a circuit for integrating storage space of the memory cards into an integrated storage medium. The integrated storage medium is used as one external disk.... Agent:
20110138122 - Gather and scatter operations in multi-level memory hierarchy: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter... Agent:
20110138123 - Managing data storage as an in-memory database in a database management system: System, method, computer program product embodiments and combinations and sub-combinations thereof for managing data storage as an in-memory database in a database management system (DBMS) are provided. In an embodiment, a specialized database type is provided as a parameter of a native DBMS command. A database hosted entirely in-memory of... Agent: Sybase, Inc.
20110138124 - Trace mode for cache memory system: A cache, including a cache memory, is configurable to operate in a cache mode and a trace mode. When the cache is operating in the cache mode, the cache memory stores a copy of a portion of data that is stored in another memory external to the cache, and a... Agent: Stmicroelectronics (research & Development) Limited
20110138125 - Event tracking hardware: An event tracking hardware engine having N (≧2) caches is invoked when an event of interest occurs, using a corresponding key. The engine stores, for each of the different kinds of events, a corresponding cumulative number of occurrences, by carrying out additional steps. In some instances, the additional steps include... Agent: International Business Machines Corporation
20110138126 - Atomic commit predicated on consistency of watches: Mechanisms for performing predicated atomic commits based on consistency of watches is provided. These mechanisms include executing, by a thread executing on a processor of the data processing system, an atomic release instruction. A determination is made as to whether a speculative store has been lost, due to an eviction... Agent: International Business Machines Corporation
20110138127 - Automatic detection of stress condition: A stress of a computerized system may be detected based on actions performed by the computerized system in respect to a storage system, such as comprising a secondary storage. The stress detection may be performed automatically based on an age of data blocks accessed by the storage system. The stress... Agent: International Business Machines Corporation
20110138128 - Technique for tracking shared data in a multi-core processor or multi-processor system: A technique to track shared information in a multi-core processor or multi-processor system. In one embodiment, core identification information (“core IDs”) are used to track shared information among multiple cores in a multi-core processor or multiple processors in a multi-processor system.... Agent:
20110138129 - Cache management for a number of threads: The illustrative embodiments provide a method, a computer program product, and an apparatus for managing a cache. A probability of a future request for data to be stored in a portion of the cache by a thread is identified for each of the number of threads to form a number... Agent: International Business Machines Corporation
20110138131 - Probabilistic offload engine for distributed hierarchical object storage devices: A method and system having a probabilistic offload engine for distributed hierarchical object storage devices is disclosed. According to one embodiment, a system comprises a first storage system and a second storage system in communication with the first storage system. The first storage system and the second storage system are... Agent: Scality, S.a.
20110138130 - Processor and method of control of processor: A processor includes: a processing unit that has a first unit; a second unit that holds part of the data held by the first unit; a third unit that receives from the processing unit a first request including first attribute information for obtaining a first logical value and a second... Agent: Fujitsu Limited
20110138132 - Rescinding ownership of a cache line in a computer system: A method of rescinding ownership of a cache line in a computer system includes constructing a table of caching agent representations in which each caching agent representation is accompanied by a validity indicator. The method continues with receiving a cache line sharing list, with each entry of the cache line... Agent:
20110138133 - Variable-width memory module and buffer: A memory module having a plurality of memory devices and a memory buffer that translates between a variable width primary data port and a plurality of fixed width secondary data ports, each of which is coupled to one of the memory devices. The translation is effected by distributing the width... Agent:
20110138134 - Software transactional memory for dynamically sizable shared data structures: We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. An interesting feature of... Agent:
20110138135 - Fast and efficient reacquisition of locks for transactional memory systems: A system and method is disclosed for fast lock acquisition and release in a lock-based software transactional memory system. The method includes determining that a group of shared memory areas are likely to be accessed together in one or more atomic memory transactions executed by one or more threads of... Agent:
20110138136 - Storage system and controlling methods for the same: For the purpose of optimizing the performance separation according to the usage status of the protocol and the storage system performance, in a storage system 1 including multiple storage devices 2400 which includes a storage controlling unit 2410 performing data write to or data read from a storage drive 2200... Agent: Hitachi, Ltd.
20110138137 - Recording medium for archiving data, recording method, recording apparatus, reproducing method, and reproducing apparatus: A recording medium for archiving data, a recording method, a recording apparatus, a reproducing method, and a reproducing apparatus are disclosed. The recording medium includes a data area for recording user data and a management area for managing information recorded on the recording medium. The management information includes data archiving... Agent: Lg Electronics Inc.
20110138140 - Data processing system: A data processing system has a plurality of storage systems. In this system, data replication is performed at high speed and efficiency while maintaining data integrity. In addition, when failure has occurred in a configuration element, the time necessary to resume the data replication is reduced. In accordance with an... Agent:
20110138139 - Method and apparatus for increasing an amount of memory on demand when monitoring remote mirroring performance: A method and storage system for increasing an amount of memory in a queuing area on. The storage system includes first and second storage subsystems connected to each other via a path. A primary volume in the first storage subsystem and a remote secondary volume in the second storage subsystem... Agent: Hitachi, Ltd.
20110138138 - Write set boundary management for heterogeneous storage controllers in support of asynchronous update of secondary storage: A data storage system including at least one storage controller having a first color policy and operative to store data onto a first data storage unit at a primary site as part of a current color of the primary site, at least one storage controller having a second color policy... Agent: International Business Machines Corporation
20110138141 - Execute only access rights on a von neuman architectures: A microcontroller system, such as a system-on-a-chip integrated circuit, including a processor (e.g., a Von Neumann processor), memory, and a memory protection unit (MPU), where the MPU provides execute-only access rights for one or more protected areas of the memory. The MPU can allow instructions fetched from within a protected... Agent: Atmel Rousset S.a.s.
20110138142 - Method and system for automatically preserving persistent storage: Computer-based methods, techniques, and systems for automatically protecting a storage device from unwanted alterations are provided. Example embodiments provide a Disk Access Redirection System, which includes a Redirection Driver, an Available Space Table (“AST”), a Protected Space Redirection Table (“PSRT”), and optionally an Unprotected Space Table (“UST”). The Redirection Driver... Agent:
20110138143 - Storage controller and storage control method: A storage controller having a plurality of storage devices and a control circuit providing a plurality of virtual volumes, to each of which a storage area in a plurality of pool volumes provided with the plurality of storage devices can be mapped for writing data in response to a write... Agent: Hitachi, Ltd.
20110138144 - Computer program, apparatus, and method for managing data: A computer in a disk node executes a data management program. A deduplication-eligible data unit detection module detects a data unit whose deduplication grace period after last write time has expired. A deduplication address fetch module interacts with an index server to obtain a deduplication address associated with a unique... Agent: Fujitsu Limited
20110138145 - Parallel nested transactions in transactional memory: Various technologies and techniques are disclosed for supporting parallel nested transactions in a transactional memory system. Multiple closed nested transactions are created for a single parent transaction, and the closed nested transactions are executed concurrently as parallel nested transactions. Various techniques are used to ensure effects of the parallel nested... Agent: Microsoft Corporation
20110138147 - Dynamic reallocation of physical memory responsive to virtual machine events: Described are methods and systems for dynamically reallocating memory amongst virtual machines executing within a virtualization environment. A computer can execute a virtualization environment that can include one or more virtual machines and that can include a memory manager. The memory manager can dynamically reallocate memory by identifying a maximum... Agent:
20110138146 - Kernel subsystem for handling performance counters and events: A system for handling performance counters and events includes an operating system that receives a request of a first application for performance data associated with a type of event to be performed by a second application, causes a hardware counter pertaining to the event type to be activated, and provides... Agent:
20110138148 - Dynamic data storage repartitioning: Embodiments of the present invention enable dynamic repartitioning of data storage in response to one or more triggers. In embodiments, a trigger may be a user-initiated action, a system-generated action, and/or an inference based on storage usage parameters. Applications of the present invention are its use in embodiments of a... Agent:
20110138149 - Preventing duplicate entries in a non-blocking tlb structure that supports multiple page sizes: One embodiment provides a system that prevents duplicate entries in a non-blocking TLB that supports multiple page sizes and speculative execution. During operation, after a request for translation of a virtual address misses in the non-blocking TLB, the system receives a TLB fill. Next, the system determines a page size... Agent: Sun Microsystems, Inc.
20110138150 - Data allocation in a distributed storage system: A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are... Agent: International Business Machines Corporation06/02/2011 > 28 patent applications in 21 patent subcategories. invention type
20110131363 - Mechanism for remapping post virtual machine memory pages: According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.... Agent:
20110131365 - Data storage system and method: A data storage system and method are disclosed. The data storage system includes a first and a second memory and a memory control unit. The first memory is non-volatile, and the second memory is designed to store dynamic information of the first memory. The memory control unit includes a snapshot... Agent: Via Technologies, Inc.
20110131369 - Logic device: A logic device for communicating with a memory package with a first protocol, communicating with a memory controller with a second protocol, and for performing a protocol conversion between the first and the second protocol.... Agent: International Business Machines Corporation
20110131366 - Memory management unit and memory management method: According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error... Agent:
20110131368 - Method and apparatus for managing erase count of memory device: A non-volatile memory device having a hidden cell located separate from data storage cells, and a method of effectively managing an erase count of the non-volatile memory device. The method includes preparing the non-volatile memory device that includes a hidden cell located separate from data storage cells and is not... Agent:
20110131367 - Nonvolatile memory device, memory system comprising nonvolatile memory device, and wear leveling method for nonvolatile memory device: A nonvolatile memory device comprises a memory core and a controller for controlling the wear level of a memory block in the nonvolatile memory device. The controller determines the wear level of a memory block by obtaining data of an actual wear level from a charge measurement cell of a... Agent: Samsung Electronics Co., Ltd.
20110131364 - Reprogramming a non-volatile solid state memory system: A non-volatile memory system (10) is provided. The system comprises: non-volatile memory (11) divided into a plurality of segments (11) each segment having an address in an address space, means for copying any one segment to be reprogrammed into a first RAM (RAM1), the first RAM having a size at... Agent: Matsushita Electric Industrial Co., Ltd.
20110131370 - Disabling outbound drivers for a last memory buffer on a memory channel: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the... Agent:
20110131371 - Method and system for refreshing dynamic random access memory: A method and system for refreshing DRAM having a plurality of banks, each of the banks including a plurality of rows includes dividing all banks in DRAM into a plurality of groups of banks, each of the groups having n banks, wherein n is an integer greater than or equal... Agent: International Business Machines Corporation
20110131372 - Optimizing segment access in binary translation: A mechanism for a binary translator to emit code that will pre-generate information about a memory segment when a segment selector is assigned to a segment register. The binary translator emits code that will be executed when a memory access using that segment register is encountered and the emitted code... Agent: Vmware, Inc.
20110131373 - Mirroring data between redundant storage controllers of a storage system: In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to... Agent:
20110131375 - Command tag checking in a multi-initiator media controller architecture: Described embodiments provide a method of allocating resources of a media controller for a data transfer. A data transfer request is received from at least one host device, and includes a host device ID and a data transfer request ID. The media controller generates a Tag ID of the data... Agent:
20110131374 - Direct memory access for loopback transfers in a media controller architecture: Described embodiments provide for transferring data from one location to another location in a memory of a media controller. A transmit data path and a receive data path of the media controller are linked with a generic direct memory access (GDMA). The transmit data path includes a transmit (TX) buffer... Agent:
20110131376 - Method and apparatus for tile mapping techniques: An approach for improving tile-map caching techniques is provided. Whether a tile object is stored in a first cache that is configured to store a plurality of tile objects associated with a map is determined. It is also determined whether a resource locator associated with the tile object is stored... Agent: Nokia Corporation
20110131377 - Multi-core processing cache image management: A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at... Agent: Honeywell International Inc.
20110131378 - Managing access to a cache memory: Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at least one separate lock attribute for each cache area such that only a processor thread having possession of the lock attribute corresponding to a particular... Agent: International Business Machines Corporation
20110131379 - Processor and method for writeback buffer reuse: A processor may include a writeback configured to perform a first writeback operation to store corresponding writeback data back to a lower-level memory upon eviction of the writeback data, and a writeback buffer configured to store the writeback data after the writeback data has been evicted from the writeback cache... Agent:
20110131380 - Altering prefetch depth based on ready data: A system comprises a controller and a buffer accessible to the controller. The controller is configured to prefetch data from a storage medium in advance of such prefetch data being requested by a host device, some of such prefetch data being retrieved from the storage medium and stored in the... Agent:
20110131381 - Cache scratch-pad and method therefor: An address containing data to be accessed is determined in response to executing an instruction received at a processor core of a microprocessor. During a scratch-pad mode of operation, it is determined whether a set of cache lines of a data cache is accessible based upon the memory location from... Agent: Advanced Micro Devices, Inc.
20110131382 - Extract cache attribute facility and instruction therefore: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.... Agent: International Business Machines Corporation
20110131383 - Modular command structure for memory and memory system: A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device.... Agent: Mosaid Technologies Incorporated
20110131384 - Systems and methods for integrating storage resources from storage area network in machine provisioning platform: Embodiments relate to systems and methods for integrating storage resources from a storage area network in a machine provisioning platform. A provisioning platform can communicate generate and maintain a provisioning profile encoding the software, hardware, and/or other resources to be provisioned to a target physical and/or virtual machine. The provisioning... Agent:
20110131385 - Data processing circuit with arbitration between a plurality of queues: Requests from a plurality of different agents (10) are passed to a request handler via a request concentrator. In front of the request concentrator the requests are queued in a plurality of queues (12). A first one of the agents is configured to issue a priority changing command with a... Agent:
20110131386 - Device, control method thereof, and program: An unmount state storing unit configured to store a state of unmount processing to end access processing to a memory card attached to a device from a host computer is provided. During a period from immediately after a host computer executes the unmount processing until detaching of the memory card... Agent: Canon Kabushiki Kaisha
20110131387 - Managing unallocated storage space using extents and bitmaps: A computing device executing a file system maintains a search tree that includes extents for managing first regions of unallocated storage space and bitmaps for managing second regions of unallocated storage space. For each region of unallocated storage space, the file system determines whether to manage that region using an... Agent:
20110131388 - Accessing multiple page tables in a computer system: A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to... Agent: Vmware, Inc.
20110131389 - Method for updating data in memories using a memory management unit: A method for updating, in the background, data stored in physical memories without affecting the current operations performed by the microprocessor. When the update is completely terminated, the application switches from an old version to a new version. This switching occurs by a reconfiguration of the page table during which... Agent: Nagravision Sa
20110131390 - Deduplication of data on disk devices using low-latency random read memory: Deduplication of data using a low-latency random read memory (LLRRM) is described herein. Upon receiving a block, if a matching block stored on a disk device is found, the received block is deduplicated by producing an index to the address location of the matching block. In some embodiments, a matching... Agent:Previous industry: Electrical computers and digital data processing systems: input/output
Next industry: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
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