|Electrical computers and digital processing systems: memory patents - Monitor Patents|
USPTO Class 711 | Browse by Industry: Previous - Next | All
01/2010 | Recent | 13: May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: memory January recently filed with US Patent Office 01/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/28/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100023671 - Enhanced microprocessor or microcontroller: A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area,... Agent: Baker Botts L.l.p
20100023673 - Avoidance of self eviction caused by dynamic memory allocation in a flash memory storage device: The operating firmware of a portable flash memory storage device is stored in the relatively large file storage memory, which is non executable. It is logically parsed into overlays to fit into an executable memory. The overlays can be of differing sizes to organize function calls efficiently while minimizing dead... Agent: Weaver Austin Villeneuve Sampson LLP
20100023674 - Flash dimm in a standalone cache appliance system and methodology: A method, system and program are disclosed for accelerating data storage in a cache appliance cluster that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a multi-rank flash DIMM cache memory by pipelining multiple page write and page program operations to different flash... Agent: Hamilton & Terrile, LLP
20100023682 - Flash-memory system with enhanced smart-storage switch and packed meta-data cache for mitigating write amplification by delaying and merging writes until a host read: A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries... Agent: Stuart T Auvinen
20100023681 - Hybrid non-volatile memory system: The present invention presents a hybrid non-volatile system that uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit the relative advantages of each these technology with respect to the others. In an exemplary embodiment, the memory system includes a controller and a flash... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100023672 - Method and system for virtual fast access non-volatile ram: A method of writing data to a non-volatile memory with minimum units of erase of a block, a page being a unit of programming of a block, may read a page of stored data addressable in a first increment of address from the memory into a page buffer, the page... Agent: Brinks Hofer Gilson & Lione/sandisk
20100023680 - Method for controlling non-volatile semiconductor memory system: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of... Agent: Hogan & Hartson L.L.P.
20100023678 - Nonvolatile memory device, nonvolatile memory system, and access device: When an access device accesses a nonvolatile memory device, the nonvolatile memory device or the access device detects or calculates a temperature T of the nonvolatile memory device. A temperature-adaptive control part of the nonvolatile memory device controls an access rate to a nonvolatile memory on the basis of the... Agent: Mark D. Saralino (pan) Renner, Otto, Boisselle & Sklar, LLP
20100023676 - Solid state storage system for data merging and method of controlling the same according to both in-place method and out-of-place method: A solid state storage system includes a controller configured to divide memory blocks of a flash memory area into first blocks and second blocks corresponding to the first blocks, newly allocates pages of the second blocks when an external write command is requested. The controller is also configured to allocate... Agent: Ladas & Parry LLP
20100023677 - Solid state storage system that evenly allocates data writing/erasing operations among blocks and method of controlling the same: A solid state storage system that evenly allocates data writing/erasing operations among blocks is presented. The solid state storage system includes a controller. The controller is configured to set a representative value that becomes a block allocation reference in accordance with predetermined information of blocks in a flash memory area.... Agent: Ladas & Parry LLP
20100023679 - Systems and techniques for non-volatile memory buffering: An apparatus, system, method, and article for non-volatile memory buffering are described. The apparatus may include a data storage manager to store a data item in a rewritable non-volatile memory buffer. The data item may have a file size less than or equal to a threshold value. The rewritable non-volatile... Agent: Kacvinsky LLC C/o Intellevate
20100023675 - Wear leveling method, and storage system and controller using the same: A wear leveling method for a flash is provided, wherein the flash memory includes a plurality of physical blocks grouped into at least a data area and a spare area. The method includes setting a first predetermined threshold value as a wear-leveling start value and randomly generating a random number... Agent: J C Patents
20100023683 - Associative matrix observing methods, systems and computer program products using bit plane representations of selected segments: Associative matrix compression methods, systems, computer program products and data structures compress an association matrix that contains counts that indicate associations among pairs of attributes. Selective bit plane representations of those selected segments of the association matrix that have at least one count is performed, to allow compression. More specifically,... Agent: Myers Bigel Sibley & Sajovec
20100023684 - Method and apparatus for reducing power consumption in a content addressable memory: Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration circuitry is configured to prevent at least... Agent: Qualcomm Incorporated
20100023686 - Method for improving raid 1 reading efficiency: A method for improving redundant array of inexpensive disks 1 (RAID 1 array) reading efficiency, which includes providing a disk head address of each disk in a RAID 1 array; receiving a read command and providing a reading file address of the read command; choosing a first preferred disk from... Agent: Brian M. Mcinnis
20100023687 - Method for providing a customized response from a disk array: The present invention discloses a method for providing a customized response from disk array, which is implemented on a disk array server having disks. The method comprises steps of receiving a request packet from a front end server, determining whether the request packet is for a response of disk environment... Agent: Brian M. Mcinnis
20100023685 - Storage device and control method for the same: A storage device is provided with: a first management section that manages a storage area provided by one or more hard disk drives on a basis of a predetermined unit created using one or more parameters; a second management section that manages, on a basis of a pool configured by... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC
20100023688 - Symmetrical storage access on intelligent digital disk recorders: A method includes designating at least three storage partitions on at least two logical drives, placing a first storage partition on a first of the logical drives adjacent to a second storage partition on a second of the logical drives separate from the first logical drives, and creating a third... Agent: Robert D. Shedd, Patent Operations Thomson Licensing LLC
20100023689 - Memory device and method of reproducing data using the same: A memory device having a resume function is provided. The memory device provides the resume function that generates and stores reproduction history information when reproduction of data is stopped due to the generation of an interrupt, providing the production history information to a newly connected reproducing apparatus, and resuming reproducing... Agent: North Star Intellectual Property Law, PC
20100023690 - Caching dynamic contents and using a replacement operation to reduce the creation/deletion time associated with html elements: An event to delete a structured object of a Web page rendered in a browser can be detected. The structured object comprises an HTML element set that was dynamically created for the Web page. The structured object can be placed in a cache without deleting memory allocations for the structured... Agent: Patents On Demand, P.A. Ibm-rsw
20100023693 - Method and system for tiered distribution in a content delivery network: A tiered distribution service is provided in a content delivery network (CDN) having a set of surrogate origin (namely, “edge”) servers organized into regions and that provide content delivery on behalf of participating content providers, wherein a given content provider operates an origin server. According to the invention, a cache... Agent: Law Office Of David H. Judson
20100023692 - Modular three-dimensional chip multiprocessor: A chip multiprocessor die supports optional stacking of additional dies. The chip multiprocessor includes a plurality of processor cores, a memory controller, and stacked cache interface circuitry. The stacked cache interface circuitry is configured to attempt to retrieve data from a stacked cache die if the stacked cache die is... Agent: Hewlett-packard Company Intellectual Property Administration
20100023691 - System and method for improving a browsing rate in a home network: A system and method for improving a browsing rate in a Universal Plug and Play (UPnP) Audio/Video (AV) home network. A control point predicts browse data using a pre-fetching operation and pre-fetches and stores the predicted browse data, which is temporarily stored in a cache implemented in the control point.... Agent: The Farrell Law Firm, LLP
20100023694 - Memory access system, memory control apparatus, memory control method and program: A memory control apparatus disposed in a memory access system having a bus, a single storage unit with a bank structure and a bus arbitrating unit, includes: an access-request accepting means for accepting sequential access requests for data located at sequential addresses in the storage unit, sequential access requests for... Agent: Rader Fishman & Grauer PLLC
20100023695 - Victim cache replacement: A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core, the lower level cache victim determines whether the memory access request hits or misses in the directory of the... Agent: Dillon & Yudell LLP
20100023696 - Methods and system for resolving simultaneous predicted branch instructions: A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states.... Agent: Qualcomm Incorporated
20100023697 - Testing real page number bits in a cache directory: Testing real page number bits in a cache directory is provided. A specification of a cache to be tested is retrieved in order to test the real page number bits of the cache directory associated with the cache. A range within a real page number address of the cache directory... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20100023698 - Enhanced coherency tracking with implementation of region victim hash for region coherence arrays: A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence... Agent: Dillon & Yudell LLP
20100023699 - System and method for usage analyzer of subscriber access to communications network: A system and a method are described, whereby a data cache enables the realization of an efficient design of a usage analyzer for monitoring subscriber access to a communications network. By exploiting the speed advantages of cache memory, as well as adopting innovative data loading and retrieval choices, significant performance... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20100023700 - Dynamically maintaining coherency within live ranges of direct buffers: Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20100023701 - Cache line duplication in response to a way prediction conflict: Embodiments of the present invention provide a system that handles way mispredictions in a multi-way cache. The system starts by receiving requests to access cache lines in the multi-way cache. For each request, the system makes a prediction of a way in which the cache line resides based on a... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP
20100023703 - Hardware transactional memory support for protected and unprotected shared-memory accesses in a speculative section: A system and method is disclosed for implementing a hardware transactional memory system capable of executing a speculative section of code containing both protected and unprotected memory access operations. A processor in a multi-processor system is configured to execute a section of code that performs a transaction using shared memory,... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20100023702 - Shared java jar files: Techniques are disclosed for sharing programmatic modules among isolated virtual machines. A master JVM process loads data from a programmatic module, storing certain elements of that data into its private memory region, and storing other elements of that data into a “read-only” area of a shareable memory region. The master... Agent: Osha Liang L.L.P./sun
20100023704 - Virtualizable advanced synchronization facility: A system and method for executing a transaction in a transactional memory system is disclosed. The system includes a processor of a plurality of processors coupled to shared memory, wherein the processor is configured to execute a section of code, including a plurality of memory access operations to the shared... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20100023705 - Processor architecture having multi-ported memory: A data processing system includes a multiport memory module including a plurality of first ports and a plurality of second ports. The data processing system includes a plurality of first buses and a plurality of second buses. A plurality of hardware acceleration modules configured to communicate with respective ones of... Agent: Harness, Dickey & Pierce P.L.C
20100023706 - Coexistence of advanced hardware synchronization and global locks: A computer-implemented method and article of manufacture is disclosed for enabling computer programs utilizing hardware transactional memory to safely interact with code utilizing traditional locks. A thread executing on a processor of a plurality of processors in a shared-memory system may initiate transactional execution of a section of code, which... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20100023707 - Processor with support for nested speculative sections with different transactional modes: A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20100023709 - Asymmetric double buffering of bitstream data in a multi-core processor: An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords for interpretation. The processor includes a general purpose unit (GPU) and a special purpose unit (SPU). The GPU includes GPU buffers and the SPU includes SPU buffers. After populating... Agent: Mark P. Kahler
20100023710 - Systems, methods, and apparatus for subdividing data for storage in a dispersed data storage grid: An efficient method for breaking source data into smaller data subsets and storing those subsets along with coded information about some of the other data subsets on different storage nodes such that the original data can be recreated from a portion of those data subsets in an efficient manner.... Agent: Garlick Harrison & Markison (cs)
20100023708 - Variable-length code (vlc) bitstream parsing in a multi-core processor with buffer overlap regions: An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords that the processor organizes into functionally common subsets. The processor includes a general purpose processor (GPU) and one or more special purpose processor (SPUs). An SPU of the processor... Agent: Mark P. Kahler
20100023711 - Interleaver memory allocation method and apparatus: According to one embodiment, memory is allocated between an interleaver buffer and a de-interleaver buffer in a communication device based on downstream and upstream memory requirements. The upstream de-interleaver memory requirement is determined based on upstream channel conditions obtained for a communication channel used by the communication device. The memory... Agent: Coats & Bennett/infineon Technologies
20100023712 - Storage subsystem and method of executing commands by controller: A storage subsystem capable of processing time-critical control commands while suppressing deterioration of the system performance to a minimum. When various commands are received in a multiplex manner via the same port from plural host devices, the channel adapter of the storage subsystem extracts commands of a first kind from... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC
20100023713 - Archive system and contents management method: There is provided an archive system that performs processing on arbitrary contents, the system including a grouping section that groups multiple archive nodes included in a cluster, a policy section that defines a requirement for performing processing on the arbitrary contents, and a control section that determines a group for... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC
20100023714 - Parallel data storage system: A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A... Agent: Mcdermott Will & Emery LLP
20100023717 - Remote copy system and remote site power saving method: A computer migrates to the same remote controller, from among a plurality of remote virtual computers at a remote site, two or more remote virtual computers belonging to a group configured from remote virtual computers with similar remote copy patterns. In the remote controller, these two or more remote virtual... Agent: Brundidge & Stanger, P.C.
20100023716 - Storage controller and storage control method: Difference information between two snapshots from a first point-in-time snapshot, which has been copied, to an Nth point-in-time snapshot, which constitutes the latest point-in-time snapshot, is acquired to a memory module. The memory module stores two or more pieces of difference information. The two or more pieces of difference information... Agent: Mattingly & Malur, P.C.
20100023715 - System for improving start of day time availability and/or performance of an array controller: An apparatus comprising a storage array, a controller, a cache storage area and a backup storage area. The storage array may include a plurality of storage devices. The controller may be configured to send one or more commands configured to control reading and writing data to and from the storage... Agent: Christopher P Maiorana, PC Lsi Corporation
20100023720 - Method and apparatus for recognizing changes to data: The present invention refers to a method and apparatus, in which changes to relevant data are made easily recognizable. The data is stored in the same sector of a flash memory as a program which is used for the start-up or operation of a device. Due to the characteristics of... Agent: Michael Best & Friedrich LLP
20100023719 - Method and circuit for protection of sensitive data in scan mode: A reset generator for resetting at least one register in a register bank. The register generator comprises a scan mode input terminal configured to input a scan mode signal, a system reset input terminal configured to input a system reset signal, a secure reset output terminal configured to output a... Agent: Dickstein Shapiro LLP
20100023718 - Methods for data-smuggling: The present invention discloses methods for an application, running on a host system, to access a restricted area of a storage device, the method including the steps of: providing a file system for running on the host system; restricting access, by the file system, to the restricted area; sending an... Agent: Mpg, LLP And Sandisk
20100023721 - Memory system and host device: A memory system includes a nonvolatile memory, and a memory controller for performing control to extend the maximum value of a logical address by erasing data of the nonvolatile memory which has become unnecessary in accordance with a command from the outside, and reassigning the data which has become unnecessary... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100023723 - Paging memory contents between a plurality of compute nodes in a parallel computer: Methods, apparatus, and products are disclosed for paging memory contents between a plurality of compute nodes in a parallel computer that includes: identifying, by a master node, a memory allocation request for an application executing on the master node, the memory allocation request requesting additional computer memory for use by... Agent: Ibm (roc-blf)
20100023722 - Storage device for use in a shared community storage network: A storage device configured to join a shared community storage network. All or a portion of the storage device is registered with the community storage network as a storage node. Once registered with the network, third party data may be stored on the storage node and remotely accessed by third... Agent: Perkins Coie LLP Patent-sea
20100023724 - Network based virtualization performance: The disclosed embodiments support improvements in network performance in networks such as storage area networks. This is particularly important in networks such as those implementing virtualization. These improvements, therefore, support improved mechanisms for performing processing in network devices such as switches, routers, or hosts. These improvements include various different mechanisms... Agent: Weaver Austin Villeneuve & Sampson LLP
20100023725 - Generation and update of storage groups constructed from storage devices distributed in storage subsystems: A plurality of storage subsystems and a plurality of storage devices are maintained, and wherein each storage subsystem includes at least one storage device of the plurality of storage devices. A plurality of storage groups is generated, wherein each storage group includes one or more storage devices selected from the... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37
20100023726 - Dual hash indexing system and methodology: A method, system and program are disclosed for accelerating data storage in a cache appliance that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a cache memory by using a dual hash technique to rapidly store and/or retrieve connection state information for cached... Agent: Hamilton & Terrile, LLP
20100023727 - Ip address lookup method and apparatus by using bloom filter and multi-hashing architecture: The present invention relates to an IF address lookup apparatus using a Bloom filter and a multi-hashing architecture that includes a buffering means that outputs a prefix of an inputted address having the number of bits reduced by one bit whenever a control signal is received at the time of... Agent: Ampacc Law Group01/21/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100017560 - Memory controller, nonvolatile memory device, access device, and nonvolatile memory system: It has been difficult for an access device to obtain a remaining capacity of a memory from a nonvolatile memory device having a plurality of interfaces. A capacity parameter generation part 127 and a capacitor parameter notification part 128 are provided in a memory controller 120. When data is written... Agent: Greenblum & Bernstein, P.L.C
20100017557 - Memory controller, nonvolatile memory device,access device, and nonvolatile memory system: A nonvolatile memory device reads and writes file data according to a file ID designated by an access device. The nonvolatile memory device includes a capacity parameter decision part 260 which generates a capacitance parameter related to a usable capacity of a nonvolatile memory 210. Even if a defective region... Agent: Greenblum & Bernstein, P.L.C
20100017558 - Memory device operable in read-only and re-writable modes of operation: A one-time programmable (OTP) memory device and methods for use therewith are provided. These embodiments can be used to provide compatibility between a memory device that uses an OTP (or few-time programmable (FTP)) memory array and host devices that use a file system, such as the DOS FAT file system,... Agent: Brinks Hofer Gilson & Lione/sandisk
20100017559 - Memory device operable in read-only and write-once, read-many (worm) modes of operation: One-time programmable (OTP) and write-once read-many (WORM) memory devices and methods for use therewith are provided. These embodiments can be used to provide compatibility between a memory device that uses an OTP (or few-time programmable (FTP)) memory array and host devices that use a file system, such as the DOS... Agent: Brinks Hofer Gilson & Lione/sandisk
20100017555 - Memory storage device and control method thereof: A control method of a memory storage device for writing an updated data from a host to the memory storage device is provided. The memory storage device provides storage space which is divided into a plurality of physical blocks to access the updated data. The control method includes the following... Agent: Rosenberg, Klein & Lee
20100017562 - Memory system: To provide a memory system that can store data smaller than a block size and data larger than the block size without deteriorating writing efficiency, and can dynamically change a parallelism according to the data. The memory system according to an embodiment of the present invention comprises a DRAM 11,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100017563 - Microcontroller based flash memory digital controller system: Some embodiments includes a digital control system having a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling... Agent: Schwegman, Lundberg & Woessner / Atmel
20100017556 - Non-volatile memory storage system with two-stage controller architecture: The present invention discloses a non-volatile memory storage system with two-stage controller, comprising: a plurality of flash memory devices; a plurality of first stage controllers coupled to the plurality of flash memory devices, respectively, wherein each of the first stage controllers performs data integrity management as well as writes and... Agent: Tung & Associates
20100017561 - Selectively accessing memory: Devices, systems, methods, and other embodiments associated with selectively accessing memory are described. In one embodiment, a method detects an indication indicative of whether to program fast access pages or slow access pages of a flash memory. In response to the detected indication, data is programmed from a volatile memory:... Agent: Kraguljac & Kalnay, LLC - Marvell
20100017554 - System and method for managing a plugged device: An electronic device is provided including a non-volatile memory, a connection interface, a processor and at least one resource. The at least one resource has at least one configuration. The non-volatile memory stores the configuration for the resource. The processor generates the configuration for the resource. When plugged into the... Agent: Quintero Law Office, PC
20100017564 - Controller, data storage device, and data communication system having variable communication speed: A main controller for use within a data storage device including a first data storage device and a second data storage device is disclosed. The controller includes a memory configured to store a plurality of protocol program data, and a processor configured to receive a host control signal from a... Agent: Volentine & Whitt PLLC
20100017565 - Data storage device and system having improved write speed: A data storage device is provided, including a first data storage device electrically storing write data, a second data storage device magnetically storing write data, and a controller partitioning write data into first and second write data portions. The first write data portion is programmed to the first data storage... Agent: Volentine & Whitt PLLC
20100017566 - System, method, and computer program product for interfacing computing device hardware of a computing device and an operating system utilizing a virtualization layer: A system, method, and computer program product are provided for interfacing computing device hardware of a computing device and an operating system. A portable memory device adapted for removable communication with a computing device including computing device hardware is provided. The portable memory device includes an operating system, and a... Agent: Zilka-kotab, PC
20100017567 - Cache memory control circuit and processor: A cache memory control circuit includes a selecting section configured to select each way or two or more ways in a cache memory in which plural ways have been divided by a predetermined division number, in a predetermined order; a detecting section configured to detect a cache hit in each... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100017568 - Cache used both as cache and staging buffer: In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry... Agent: Mhkkg, PC/apple, Inc.
20100017569 - Pcb including multiple chips sharing an off-chip memory, a method of accessing off-chip memory and a mcm utilizing fewer off-chip memories than chips: A PCB having fewer off-chip memories than chips, a MCM, and a method of accessing an off-chip shared memory space. In one embodiment, the method includes: (1) generating a memory request at a first chip of the printed circuit board, (2) transforming the memory request to a shared memory request... Agent: Hitt Gaines, PC Lsi Corporation
20100017570 - Method for storing data as well as a transponder, a read/write-device, a computer readable medium including a program element and such a program element adapted to perform this method: A method for storing or reading data in a memory array of a transponder and a corresponding transponder, read/write device and program element is described. Therein, a data file system for storing data within the memory array is defined by a predetermined protocol. The data structure comprises: a capability container... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100017571 - Content write-in device: It is possible to classify a continuous content into separate series to be written into a storage medium. A reception device receives a digital broadcast program and EIT and generates program attribute information according to the information associated with the series contained in EIT. Upon reception of a write-into-DVD instruction... Agent: Mr. Jackson Chen
20100017572 - Transactional memory support for non-coherent shared memory systems using selective write through caches: A method of controlling memory operations in a transactional shared memory system having a plurality of nodes connected through an interconnect network. The method includes initiating a memory operation at a first node including a first memory controller and a transaction table where the transaction table is configured to store... Agent: Osha Liang L.L.P./sun
20100017573 - Storage system, copy control method of a storage system, and copy control unit of a storage system: A storage system and a copy control method enabling copying of data stored in a first volume connected with a higher-level device to a second volume. The system and method include controlling an update using a first management table for managing an update during a period from reception of a... Agent: Staas & Halsey LLP
20100017574 - Storage system, method of controlling storage system, and storage device: The present invention provides a storage system and a method of controlling the storage system, in which a second site rapidly resumes system process when a first site is damaged. The storage system comprises a first site including a first storage device, a second site including a second storage device,... Agent: Mattingly & Malur, P.C.
20100017576 - Data transference to virtual memory: Some embodiments comprise a method for selecting data to be transferred to a storage space of virtual memory and include identifying a set of data and determining subsets. Determining subsets may allow for delays before transferring the subsets and allow access to memory of the subsets during the delays. Accesses... Agent: Ibm Corporation (jss) C/o Schubert Osterrieder & Nickelson PLLC
20100017575 - Security system for external data storage apparatus and control method thereof: A security system for an external data storage apparatus and a control method thereof, in which a data storage is driven by reading an identification (ID), which is input through a key input unit for the purpose of security of the external data storage apparatus, and then checking whether or... Agent: Renner Otto Boisselle & Sklar, LLP
20100017577 - Storage controller and method for controlling the same: A storage controller facilitating extending storage capacity while suppressing investment related to storage capacity is provided. System configuration information, including content of a definition of a virtual volume having a storage capacity that is larger than a real storage capacity including the storage capacity of a storage device unit, and... Agent: Brundidge & Stanger, P.C.
20100017578 - Storing compressed data: A method of processing data for storage in a storage medium coupled to a processing unit adapted to access data stored in the storage medium as one or more pages of data, each page having a predetermined page size and a corresponding virtual memory address, the method comprising: obtaining a... Agent: Potomac Patent Group PLLC01/14/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100011147 - Virtualizing an iommu: In one embodiment, a system comprises one or more input/output (I/O) devices; an I/O memory management unit (IOMMU) coupled to receive memory requests sourced by the I/O devices and configured to provide address translation for the memory requests; and a virtual machine monitor (VMM) configured to manage one or more... Agent: Mhkkg / Globalfoundries
20100011148 - Method and apparatus to facilitate using a policy to modify a state-to-state transition as comprises a part of an agnostic stored model: A stored model is comprised of a plurality of candidate contextually-described states along with state-to-state transitions between at least some of this plurality of candidate contextually-described states. This stored model can be agnostic with respect to any particular application. One can then access at least one policy as pertains to... Agent: Motorola/fetf
20100011153 - Block management method, and storage system and controller using the same: A block management method for managing a multi level cell (MLC) NAND flash memory is provided, wherein the MLC NAND flash memory has a plurality of physical blocks grouped into at least a data area and a spare area, each of the physical blocks has a plurality of pages divided... Agent: J C Patents
20100011159 - Combined mobile device and solid state disk with a shared memory architecture: A mobile device includes a system-on-chip (SOC) that includes a mobile device control module, a solid state disk (SSD) control module, and a random access memory (RAM) control module. The mobile device control module executes application programs for the mobile device. The solid-state disk (SSD) control module controls SSD operations.... Agent: Harness, Dickey & Pierce P.L.C
20100011154 - Data accessing method for flash memory and storage system and controller using the same: A data accessing method for a flash memory and a storage system and a controller using the same are provided. The data accessing method includes grouping a plurality of physical blocks of the flash memory into a data area, a spare area, and a random area and when a write... Agent: J C Patents
20100011151 - Data accessing method, and storage system and controller using the same: A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block... Agent: J C Patents
20100011150 - Data collection and compression in a solid state storage device: Methods for programming compressed data to a memory array, memory devices, and memory systems are disclosed. In one such method, memory pages or blocks that are partially programmed with valid data are found. The data is collected from these partially programmed pages or blocks and the data is compressed. The... Agent: Leffert Jay & Polglaze, P.A.
20100011155 - Data processor with flash memory, and method for accessing flash memory: A data processor includes a flash memory that stores a plurality of types of data therein, a random access memory that stores record data information therein, and a controller that can access the flash memory and the RAM. The record data information indicates a head address in the flash memory... Agent: Mcginn Intellectual Property Law Group, PLLC
20100011152 - Data programming methods and devices: A data programming device is provided and comprises a non-volatile memory, a volatile memory, and a memory control unit. The non-volatile memory is arranged for programming data. The volatile memory is arranged for temporarily storing data. The memory control unit is arranged for receiving data and determining whether the data... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100011149 - Data storage devices accepting queued commands having deadlines: A data storage device accepts queued read and write commands that have deadlines. The queued read and write commands are requests to access the data storage device. The deadlines of the queued read and write commands can be advisory deadlines or mandatory deadlines.... Agent: Steven J. Cahill/ Hitachi Gst
20100011157 - Device and method for backing up data on non- volatile memory media, of the nand flash type, designed for onboard computers: The present invention relates to a device making it possible to manage a flash memory component designed for onboard computers notably in the aviation field. In particular, the invention makes it possible to use NAND flash memory media in fields such as aviation, by virtue of its judicious organisation and... Agent: Darby & Darby P.C.
20100011158 - Memory controller, memory system, and control method for memory system: A memory controller for performing processing for writing data in an interleaved manner and in units of pages in a semiconductor memory section made up of chip 0 and chip 1, each of the chips composed of a large number of memory cells capable of storing two-bit data in one... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100011156 - Memory device and management method of memory device: A memory device includes a plurality of blocks, and the plurality of blocks may include a plurality of pages. The memory device may translate an external physical address into internal physical address using a non-volatile address translation memory. The memory device may access one page of a plurality of pages... Agent: North Star Intellectual Property Law, PC
20100011161 - Memory emulation using resistivity sensitive memory: Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element,... Agent: Unity Semiconductor Corporation
20100011160 - Method and system for providing security to processors: There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are... Agent: Texas Instruments Incorporated
20100011162 - Method and system for performing raid level migration: A RAID level migration system and method are provided that enable RAID level migration to be performed without the use of a hardware RAID controller with NVRAM for storing the migration parameters. Eliminating the need for a hardware controller having NVRAM significantly reduces the costs associated with performing RAID level... Agent: Smith Frohwein Tempel Greenlee Blaha LLC
20100011164 - Memory systems and methods of initiallizing the same: A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access... Agent: Volentine & Whitt PLLC
20100011163 - Portable device for managing memory cards: A portable device includes n (n≧2) electrical sockets, each of which is configured to accommodate and to electrically engage a removable external memory card; an input device for selecting accommodated and electrically engaged external memory cards for data reading; and an output device for outputting information that is derived from... Agent: Toler Law Group
20100011165 - Cache management systems and methods: A multi mode cache system that uses a direct mapped cache scheme for some addresses and an associative cache scheme for other addresses.... Agent: Ericsson Canada Inc. Patent Department
20100011166 - Data cache virtual hint way prediction, and applications thereof: A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20100011167 - Heterogeneous processors sharing a common cache: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.... Agent: Intel Corporation C/o Cpa Global
20100011168 - Method and apparatus for cache flush control and write re-ordering in a data storage system: Methods and apparatus for cache flush control and write re-ordering in a data storage system are provided. A cache flush control method includes cache flushing information stored in a cache memory to a first storage apparatus of a plurality of storage apparatuses included in a data storage system when a... Agent: Stanzione & Kim, LLP
20100011169 - Cache memory: Disclosed is a cache memory, design structure, and corresponding method for improving cache performance comprising one or more cache lines of equal size, each cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and a predict... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20100011170 - Cache memory device: A cache memory device includes an address generation unit, a data memory, a tag memory, and a hit judging unit. The address generation unit generates a prefetch index address included in a prefetch address based on an input address supplied from a higher-level device. The tag memory stores a plurality... Agent: Young & Thompson
20100011171 - Cache consistency in a multiprocessor system with shared memory: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and... Agent: Gardere Wynne Sewell LLP Intellectual Property Section
20100011172 - Microcontroller systems having separate address and data buses: A microcontroller system includes at least one processor and at least one storage unit for storing data received from or to be sent to the processor. At least two read clients are provided in the processor for retrieving data from the storage unit, and at least one write client is... Agent: Greer, Burns & Crain
20100011173 - Downgrade memory apparatus, and method for accessing a downgrade memory: A method for accessing a downgrade memory and a downgrade memory apparatus are provided. The downgrade memory apparatus comprises at least one management unit and a controller. The management unit comprises a plurality of blocks, each block having a plurality of pages, and each page having a plurality of sectors,... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC
20100011174 - Mixed data rates in memory devices and systems: Mixed data rates in a memory system is disclosed. The system includes at least one semiconductor memory device and another device defining a ring topology. The semiconductor memory device includes input circuitry for receiving a clock signal having a frequency at least substantially equal to a frequency x. A first... Agent: Mosaid Technologies Incorporated
20100011175 - Semiconductor integrated circuit and access controlling method of semiconductor memory: An area detection unit detects a main rectangular area to which an access start address indicated by one-dimensional access information is included among main rectangular areas corresponding to two-dimensional access information. An address conversion unit divides the detected main rectangular area into sub rectangular areas, detects a sub rectangular area... Agent: Arent Fox LLP
20100011176 - Performance of binary bulk io operations on virtual disks by interleaving: A method and system are provided for executing a binary bulk input/output (IO) operation on a first virtual disk and a second virtual using interleaving. The performance improvement due to the method is expected to increase as more information about the configuration of the virtual disks and their implementation are... Agent: Beck And Tysver P.l.l.c.
20100011180 - Information processing appartaus, content control method, and storage medium: According to one embodiment, a storage medium configured to be connectable to apparatuses for processing an encrypted content, the medium stores a content key of the encrypted content, and a copy control list includes information indicating one of the apparatuses which is a copying destination of the encrypted content.... Agent: Patterson & Sheridan, L.L.P.
20100011177 - Method for migration of synchronous remote copy service to a virtualization appliance: A method, system, computer program product, and computer program storage device for receiving and processing I/O requests from a host device and providing data consistency in both a primary site and a secondary site, while migrating a SRC (Synchronous Peer to Peer Remote Copy) from a backend storage subsystem to... Agent: Scully, Scott, Murphy & Presser, P.C.
20100011181 - Methods for synchronizing storage system data: In accordance with one example, a method for comparing data units is disclosed comprising generating a first digest representing a first data unit stored in a first memory. A first encoded value is generated based, at least in part, on the first digest and a predetermined value. A second digest... Agent: Brandon N. Sklar. Esq. (patent Prosecution) Kaye Scholer, LLP
20100011179 - Remote copy system and method: A remote copy system includes a first storage device performing data transmission/reception with a host computer, a second storage device receiving data from the first storage device, and a third storage device receiving data from the second storage device. The first storage device includes a logical volume, the second storage... Agent: Mattingly & Malur, P.C.
20100011178 - Systems and methods for performing backup operations of virtual machine files: Backup systems and methods are disclosed for a virtual computing environment. Certain examples include a system having a backup management server that communicates with a host server having at least one virtual machine. The management server coordinates with the host server to perform backup copies of entire virtual machine disks... Agent: Knobbe Martens Olson & Bear LLP
20100011182 - Techniques for scheduling requests for accessing storage devices using sliding windows: A system includes a storage device and a scheduler. The scheduler determines if deadlines of requests for accessing the storage device fall within first and second sliding windows. The scheduler issues requests that are in the first sliding window in a first order of execution and requests that are in... Agent: Steven J. Cahill/ Hitachi Gst
20100011184 - Management method and a management system for volume: It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk volume. In response to changes in contents of operation to alter a storage configuration... Agent: Brundidge & Stanger, P.C.
20100011183 - Method and device for establishing an initial state for a computer system having at least two execution units by marking registers: A method for establishing an initial state in a computer system having at least two execution units, a switchover between a performance mode and a compare mode being performed, and during the switchover from the performance mode to the compare mode, an initial state for the compare mode being generated,... Agent: Kenyon & Kenyon LLP
20100011185 - Storage system and method for storage capacity change of host-device-specified device: A controller in a storage system receives a capacity change command specifying a device, and changes, to a volume capacity value indicating a storage capacity following the capacity change command, a volume capacity value of a virtual volume associated with the device specified in management information, which includes the volume... Agent: Brundidge & Stanger, P.C.
20100011187 - Performance enhancement of address translation using translation tables covering large address spaces: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used... Agent: Intel Corporation C/o Cpa Global
20100011186 - Synchronizing a translation lookaside buffer with an extended paging table: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB),... Agent: Caven & Aghevli LLC C/o Cpa Global
20100011188 - Microprocessor that performs speculative tablewalks: A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory whose physical address specified by a memory access instruction is missing in the TLB, performs... Agent: Huffman Law Group, P.C.01/07/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100005217 - Multi-mode memory device and method: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100005219 - 276-pin buffered memory module with enhanced memory system interconnect and features: A memory module including a plurality of memory channel connectors for communicating with a memory controller via a plurality of high-speed channels. The memory module also includes a plurality of memory devices arranged in one or more ranks, and a plurality of independently operable hub devices. Each hub device includes... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20100005220 - 276-pin buffered memory module with enhanced memory system interconnect and features: A memory module that includes a first group of memory devices arranged in one or more ranks and a second group of memory devices arranged in one or more ranks. The memory module also includes a first and second port, wherein the first port is operable simultaneously with and independently... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20100005221 - Address generation for multiple access of memory: A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network... Agent: Harrington & Smith, PC
20100005218 - Enhanced cascade interconnected memory system: A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20100005222 - Optimizing virtual memory allocation in a virtual machine based upon a previous usage of the virtual memory blocks: The allocation of virtual memory within a virtual machine based upon the previous mapping of virtual memory blocks to physical memory blocks is optimized. Virtual memory blocks that have been mapped to a corresponding physical memory block over virtual memory blocks that are unmapped when fulfilling an allocation request can... Agent: Patents On Demand, P.A. Ibm-rsw
20100005223 - Method for field-programming a solid-state memory device with a digital media file: The preferred embodiments described herein provide a method for field-programming a solid-state memory device with a digital media file. In one preferred embodiment, a solid-state memory device is provided that comprises a memory array comprising a plurality of field-programmable memory cells. A digital media file is selected for storage in... Agent: Brinks Hofer Gilson & Lione/sandisk
20100005228 - Data control apparatus, storage system, and computer program product: A data control apparatus includes a mapping-table managing unit that manages a mapping table that is associated with a corrupted-data recovery function of recording data and error correcting code data as redundant data that is given separately from the data, distributed and stored in units of stripe blocks in the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100005230 - Data storing methods and apparatus thereof: A data storing method for non-volatile memory is provided, wherein the non-volatile memory includes at least one memory block having a plurality of strong pages and weak pages. A logic block writing command is received for storing the corresponding writing data into the memory block. It is then determined whether... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100005229 - Flash memory apparatus and method for securing a flash memory from data damage: A method for securing a flash memory from data damage is provided. After writing of data to a plurality of written pages of a first block of a flash memory is completed, a last weak page of the written pages is determined. A first strong page corresponding to the last... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100005224 - Foldable usb flash memory device that can be manufactured in any desired shape and size suitable for different types of host devices: An enhanced design for the USB flash memory devices implemented with the USB specifications. The main idea in this design is to create two-section USB flash memory devices and both the sections be joined together with the help of rotating hinges and pivots so that both the sections can rotate... Agent: Ram Gupta
20100005232 - Memory controller interface: A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and SRAM memory devices to instead operate using NAND flash and SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed... Agent: Dimock Stratton LLP/research In Motion Limited
20100005227 - Memory controller, nonvolatile memory device, access device, and nonvolatile memory system: A file to be read or written is designated and accessed from an access device side to a nonvolatile memory device. In an initialization after start-up of the power source, an empty capacity detector detects empty capacity parameters of a nonvolatile memory with dividing the memory into a plurality of... Agent: Greenblum & Bernstein, P.L.C
20100005231 - Method and system for hardware implementation of resetting an external two-wired eeprom: Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal... Agent: Mcandrews Held & Malloy, Ltd
20100005226 - Nonvolatile memory device, access device, and nonvolatile memory system: An access device 100 includes an access speed information part 112 for informing an access speed required for data recording by the access device 100 to a nonvolatile memory device 200. The nonvolatile memory device includes an access condition determination part 212 for determining an access condition required for meeting... Agent: Greenblum & Bernstein, P.L.C
20100005225 - Nonvolatile memory device, nonvolatile memory system, and host device: A nonvolatile memory device has a file system manager and manages the file system of a file to be recorded. The nonvolatile memory device measures time by obtaining time information from outside in each writing file data or based on time information preliminarily obtained. At the time of writing file... Agent: Greenblum & Bernstein, P.L.C
20100005235 - Computer system: A computer system includes a CPU and a system on chip (SoC) processor electronically connected with the CPU in the computer system. The CPU and the SoC processor do not work simultaneously. The CPU processes work and a service when the computer system is powered on. The SoC processor continues... Agent: PCe Industry, Inc. Att. Steven Reiss
20100005234 - Enabling functional dependency in a multi-function device: In one embodiment, the present invention includes a method for reading configuration information from a multi-function device (MFD), building a dependency tree of a functional dependency of functions performed by the MFD based on the configuration information, which indicates that the MFD is capable of performing at least one function... Agent: Trop, Pruner & Hu, P.C.
20100005233 - Storage region allocation system, storage region allocation method, and control apparatus: There are provided a memory space allocation method and a memory space allocation device that aim at higher-speed accesses when a memory is shared by a plurality of circuits. In this memory, one data is accessed by issuing addresses a plurality of times. Memory allocation is performed so that high-order... Agent: Young & Thompson
20100005236 - Automatically assigning a multi-dimensional physical address to a data storage device: A method of assigning a multi-dimensional physical address to a tape-based data storage device is provided. The method includes accessing a first signal from a first communication path electrically coupled to a first tape-based data storage device, wherein the first signal indicates a physical position of the first tape-based data... Agent: Quantum C/o Wagner Blecher LLP
20100005238 - Multi-serial interface stacked-die memory architecture: Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands,... Agent: Schwegman, Lundberg & Woessner/micron
20100005237 - Scheduling read operations during drive reconstruction in an array of redundant disk drives: Some embodiments of the present invention provide a system that schedules read operations for disk drives in a set of disk drives. During operation, the system monitors a write rate for write operations to a given disk drive in the set of disk drives, wherein vibrations generated by the read... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP
20100005239 - Methods and apparatus for copying data: In one embodiment, the method includes modifying data being copied such that portions of the data that include defects are replaced with dummy data. For example, a defective portion of the data is detected during a copy operation, and the data being copied is modified such that detected defective portions... Agent: Harness, Dickey & Pierce, P.L.C
20100005240 - Display apparatus and its method for displaying connections among a host, a logical unit and a storage system in a virtual storage system: This invention provides a user or an operator with a management apparatus or method for displaying logical connection information between an interface connected to a computer and a switch and a storage system or a logical unit in the storage system in a virtual storage system, wherein the switch receives... Agent: Brundidge & Stanger, P.C.
20100005241 - Detection of streaming data in cache: An apparatus to detect streaming data in memory is presented. In one embodiment the apparatus use reuse bits and S-bits status for cache lines wherein an S-bit status indicates the data in the cache line are potentially streaming data. To enhance the efficiency of a cache, different measures can be... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20100005242 - Efficient processing of data requests with the aid of a region cache: A method and system for configuring a cache memory system in order to efficiently process processor requests. A group of cache elements, which include a Region Cache, a Region Coherence Array, and a lowest level cache, is configured based on a tradeoff of latency and power consumption requirements. A selected... Agent: Dillon & Yudell LLP
20100005243 - Rendering apparatus which parallel-processes a plurality of pixels, and data transfer method: A rendering apparatus includes a memory device, a cache memory, a cache control unit and a rendering process. The memory device stores image data. The cache memory executes transmission/reception of the image data to/from the memory device. The cache memory includes a plurality of entries, each of which is capable... Agent: SprinkleIPLaw Group
20100005244 - Device and method for storing data and/or instructions in a computer system having at least two processing units and at least one first memory or memory area for data and/or instructions: A device and method for storing data and/or instructions in a computer system having at least two processing units and at least one first memory or memory area for data and/or instructions, wherein a second memory or memory area is included in the device, the device being designed as a... Agent: Kenyon & Kenyon LLP
20100005245 - Satisfying memory ordering requirements between partial writes and non-snoop accesses: A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, when a conflict associated with a partial memory access, such as a partial write, is detected, a write-back phase is inserted... Agent: Intel Corporation C/o Cpa Global
20100005247 - Method and apparatus for global ordering to insure latency independent coherence: A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to apply global ordering to the requests. A bus... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20100005248 - Pseudo least recently used replacement/allocation scheme in request agent affinitive set-associative snoop filter: The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations.... Agent: Caven & Aghevli LLC C/o Cpa Global
20100005246 - Satisfying memory ordering requirements between partial reads and non-snoop accesses: A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer... Agent: Intel Corporation C/o Cpa Global
20100005249 - Finding the source statement of the definition of a storage location: In an embodiment, an identifier of a storage location that is accessed by a program is received. While execution of the program is halted at a halted statement, a first source statement is determined that must have stored to the storage location. The program comprises the halted statement and the... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20100005251 - Memory control circuit and integrated circuit: The memory unit is compatible with a plurality of operation modes. The plurality of operation modes include the normal mode allowing access and the standby mode consuming a lower power than the normal mode. The branch detection section detects a branch instruction from an instruction fetched from the memory unit... Agent: Mcginn Intellectual Property Law Group, PLLC
20100005250 - Size and retry programmable multi-synchronous fifo: A size and retry programmable multi-synchronous FIFO. In one embodiment, a multi-synchronous FIFO memory generally comprises a selectable number of addressable memory locations for storing information; read control means synchronized by a read clock for controlling pop transactions configured to read from one or more of the selected number of... Agent: Schneck & Schneck
20100005252 - Storage control system: A storage control system includes a storage device and a UPS electrically connected to and communicating with the storage device. The storage device has a write back process and a write through process for writing data into the storage device, and includes a monitoring module. The UPS includes a control... Agent: PCe Industry, Inc. Att. Steven Reiss
20100005253 - Memory controller, pcb, computer system and memory adjusting method: A memory controller, a PCB and a computer system employing the memory controller, and a memory adjusting method using the memory controller. The memory controller interfaces data reading from and writing to a memory and includes: a characteristic estimating part estimating a characteristic of a memory output signal outputted from... Agent: Stein Mcewen, LLP
20100005255 - Method for providing atomicity for host write input/outputs (i/os) in a continuous data protection (cdp)-enabled volume using intent log: The present invention is a method for providing atomicity for host write Input/Outputs (I/Os) in a Continuous Data Protection (CDP)-enabled volume. When a host overwrite Input/Output (I/O) is initiated by a host against a data block of the CDP-enabled volume, the method may include creating an in-flight write log entry... Agent: Lsi Corporation C/o Suiter Swantz PC Llo
20100005256 - Method of managing a memory including elements provided with identity information indicative of the ancestry of said elements: A method of managing a memory having stored elements that are organized in a hierarchy, each having a header containing individual identity information and a body containing data, the identity information of each element being encoded on a plurality of bits each of which can take a first value or... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100005254 - Nearest neighbor serial content addressable memory: A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted... Agent: Connolly Bove Lodge & Hutz LLP
20100005257 - Storage device, controlling method for storage device, and control program: A storage device includes a first storage unit that stores data read from a recording medium based on an instruction received from a processing device, and transmitting the data stored in the first storage unit to the processing device. The storage device also includes a second storage unit that stores... Agent: Greer, Burns & Crain
20100005258 - Backup system and method: Backup of a production instance of an application in a production machine environment is performed by creating a snapshot image that captures the state of the production machine, and then backing up the application from a backup machine created using the snapshot image. The backup of the application can be... Agent: Meyertons, Hood, Kivlin, Kowert, Goetzel/symantec
20100005259 - Continuous data protection over intermittent connections, such as continuous data backup for laptops or wireless devices: A portable data protection system is described for protecting, transferring or copying data using continuous data protection (CDP) over intermittent or occasional connections between a computer system or mobile device containing the data to be protected, transferred or copied, called a data source, and one or more computer systems that... Agent: Perkins Coie LLP Patent-sea
20100005263 - Information backup method, firewall and network system: An information backup method, a firewall, and a network system are provided in the embodiments of the present disclosure. The method of the present disclosure implements information backup between at least two firewalls. The method includes: receiving a packet; and backing up changed session information to the another firewall if... Agent: Darby & Darby P.C.
20100005262 - Information processing apparatus, data restoring method of information processing apparatus, and data restoring program of information processing apparatus: According to the present invention, an information processing apparatus includes: a first storage module; a second storage module; a first acquiring module configured to acquire data from the first storage module when a failure occurs; a determination module configured to determine whether the data acquired by the first acquiring module... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100005261 - Storage device and power control method: The storage device of the present invention has: a first recording unit that records a time zone history of access to each storage area assigned to a virtual volume; a second recording unit that executes a predetermined calculation based on the time zone history of access to a plurality of... Agent: Brundidge & Stanger, P.C.
20100005260 - Storage system and remote copy recovery method: Data written in the primary logical volume of the first storage device are transmitted to the third storage device via the second storage device, the data being written in the same location as the primary logical volume within the secondary logical volume in the third storage device; when transmission of... Agent: Mattingly & Malur, P.C.
20100005264 - Information processing device, integrated circuit, method, and program: To aim to provide an information processing device capable of improving a processing capability and securely handling programs and data to be protected. According to a system LSI 100 including a plurality of CPUs, when a CPU-1 102 switches to a protection mode, the CPU-1 102 and a CPU-2 103... Agent: Wenderoth, Lind & Ponack L.L.P.
20100005265 - Method for isolating objects in memory region: Method for isolating an object that has not been accessed for a certain period of time in a virtual memory space. When a garbage collection operates on a computer, the following steps are executed: detecting the object which has not been accessed for a certain period of time as a... Agent: Ibm Corporation, T.j. Watson Research Center
20100005266 - Technique for estimating the size of an in-memory cache: This Sampling Object Cache System (“SOCS”) estimates the size of an in-memory heap-based object cache without the need to serialize every object within the cache. SOCS samples objects at a user-determined rate and then computes a “sample size average” for each type of class-whether a top class, type of top... Agent: Ibm Corp. (raleigh Software Group) C/o Rudolf O Siegesmund Yee & Associates, P.C.
20100005267 - Memory management for hypervisor loading: Techniques related to personal computers and devices sharing similar architectures are disclosed. Particularly shown is a system and method for enabling improved performance and security in hypervisor programs and related applications programs achieved through the use of multiple non-volatile memories.... Agent: Phoenix Technologies Ltd.
20100005268 - Maintaining corresponding relationships between chat transcripts and related chat content: A method, apparatus, and system for maintaining corresponding relationships between at least one chat transcript and related chat content in an instant messaging system may include establishing a chat session in the instant messaging system. Corresponding chat content may be displayed synchronously according to a changed address of the chat... Agent: Holland & Knight
20100005269 - Translation of virtual to physical addresses: Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of... Agent: Nixon & Vanderhye P.C.
20100005270 - Storage unit management methods and systems: Storage unit management methods and systems are provided. The storage unit comprises a plurality of physical blocks, wherein each has one of a plurality of block type definitions. First, a sub-write command is obtained, wherein the sub-write command requests to write data to at least one logical page of a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100005271 - Memory controller: A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100005272 - Virtual memory window with dynamic prefetching support: Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of... Agent: Harness, Dickey & Pierce, P.L.CPrevious industry: Electrical computers and digital data processing systems: input/output
Next industry: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
RSS FEED for 20130516:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: memory patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: memory patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: memory patents we recommend signing up for free keyword monitoring by email.
FreshPatents.com Support - Terms & Conditions
Results in 0.90463 seconds