Electrical computers and digital processing systems: memory inventions 08/09

20090216936 - Data reading method for flash memory and controller and storage system using the same: A data reading method suitable for a flash memory storage system having a flash memory is provided, wherein the flash memory is substantially divided into a plurality of blocks and these blocks are grouped into at least a data area and a spare area. The data reading method includes: respectively... Agent: J C Patents, Inc.

20090216938 - Management of non-volatile memory systems having large erase blocks: A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20090216937 - Memory controller, memory system, and access control method of flash memory: A memory controller adds dummy data to write data by referring to instruction information about a descriptor transfer of the write data if a size of the write data to be written according to a data-write request information does not match a page size unit, thereby adjusting the size of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090216935 - Memory device for a user profile: A memory device for a user profile of a plurality of electronic devices or functional units in a motor vehicle is used for providing data corresponding to the user profile in the vehicle without a user having to make corresponding settings. As a result of being stored in the memory... Agent: Kenyon & Kenyon LLP

20090216939 - Emulation of abstracted dimms using abstracted drams: One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include... Agent: Michael J. S. Smith Suite 400

20090216940 - Method for accessing a first-in-first-out (fifo) buffer and a fifo controller therefor: A method of for accessing a first-in-first-out (FIFO) buffer is provided. The method comprises the following two steps. Firstly, issue a request to access a memory when the amount of the data buffered in the FIFO buffer is more than a threshold. Second, pop the data buffered in the FIFO... Agent: Rabin & Berdo, Pc

20090216941 - Method for saving computer data: The invention relates to a method for saving computer data which consist in transferring the data to be saved from a client computer to a buffer storage formed by the hard disc of a backup server, organised in a plurality of volumes of predetermined size, and in then transferring the... Agent: Muirhead And Saturnelli, Llc

20090216943 - Data storage device and data management method in data storage device: Embodiments of the present invention improve efficiency in saving log data in a hard disk drive (HDD) equipped with a magnetic disk and a flash memory,. In an aspect of one embodiment of the present invention, a HDD creates a segment table to associate an address of user data in... Agent: Townsend And Townsend And Crew LLP

20090216942 - Efficient memory management for hard disk drive (hdd) read channel: Efficient memory management for hard disk drive (HDD) read channel. The memory management presented herein can be broadly applied to any interface in which data is provided from a first location to a second location. A number of buffer units are employed, arranged into a number of slices, in which... Agent: Garlick Harrison & Markison

20090216944 - Efficient validation of writes for protection against dropped writes: A write cache provides for staging of data units written from a processor for recording in a disk. The order in which destages and validations occur is controlled to make validations more efficient. The data units are arranged in a circular queue according to their respective disk storage addresses. Each... Agent: Gregory Smith

20090216945 - Storage system which utilizes two kinds of memory devices as its cache memory and method of controlling the storage system: Provide is a storage system including one or more disk drives, and one or more cache memories for temporarily storing data read from the disk drives or data to be written to the disk drives, in which: the cache memories includes volatile first memories and non-volatile second memories; and the... Agent: Brundidge & Stanger, P.c.

20090216946 - Raid1 system and reading method for enhancing read performance: Concerning the operations of a redundant array of independent disks 1 system, a reading process is carried out by skipping the even-address storage units in a first storage device, sequentially fetching the data of the odd-address storage units in the first storage device for forming a first data stream, skipping... Agent: North America Intellectual Property Corporation

20090216948 - Method for substantially uninterrupted cache readout: A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring operations. The memory device outputs cached data from a first page while data from a second page is fetched into sense amplifier circuitry. When the outputting of the... Agent: Dickstein Shapiro LLP

20090216947 - System, method and processor for accessing data after a translation lookaside buffer miss: Data is accessed in a multi-level hierarchical memory system. A request for data is received, including a virtual address for accessing the data. A translation buffer is queried to obtain an absolute address corresponding to the virtual address. Responsive to the translation buffer not containing an absolute address corresponding to... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216949 - Method and system for a multi-level virtual/real cache system with synonym resolution: Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216950 - Push for sharing instruction: In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a first instruction, including forming an address... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090216951 - System, method and computer program product for handling shared cache lines in a multi-processor environment: A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216952 - Method, system, and computer program product for managing cache memory: A method for managing cache memory including receiving an instruction fetch for an instruction stream in a cache memory, wherein the instruction fetch includes an instruction fetch reference tag for the instruction stream and the instruction stream is at least partially included within a cache line, comparing the instruction fetch... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216953 - Methods and systems for dynamic cache partitioning for distributed applications operating on multiprocessor architectures: Software, systems and methods are described which provide cache management capabilities. The number of cache sets to be used in each partition of the cache memory space is based on a number of cache pages in each partition and an associativity level associated with the set associative cache. The cache... Agent: Ericsson Canada Inc. Patent Department

20090216954 - Apparatus, system, and method for selecting a space efficient repository: An apparatus, system, and method are disclosed for selecting a space efficient repository. A cache receives write data. A destage module destages the data sequentially to a coarse grained repository such as a stride level repository and destages a directory entry for the data to a coarse grained directory such... Agent: Kunzler & Mckenzie

20090216955 - Method, system and computer program product for lru compartment capture: A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe pass by determining whether a fetch hit or... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216956 - System, method and computer program product for enhancing timeliness of cache prefetching: A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216957 - Managing the storage of data in coherent data stores: A data processing apparatus is disclosed that comprises: at least one processor; at least one data store for storing data processed by said at least one processor; a shared data store for storing data processed by said at least one processor and at least one further device; and coherency control... Agent: Nixon & Vanderhye P.c.

20090216958 - Hardware accelerator interface: A data processing system in the form of an integrated circuit 2 includes a general purpose programmable processor 4 and a hardware accelerator 6. A shared memory management unit 10 provides memory management operations on behalf of both of the processor core 4 and the hardware accelerator 6. The processor... Agent: Nixon & Vanderhye P.c.

20090216959 - Multi port memory controller queuing: The present invention is generally directed to a method, system, and program product wherein at least one command in a first queue is transferred to a second queue. When the first queue can no longer accept command(s) and a second queue is able to accept command(s), the second queue accepts... Agent: Matthew C. Zehrer Ibm Corporation

20090216960 - Multi port memory controller queuing: The present invention is generally directed to a method, system, and program product wherein at least two memory ports associated within a memory controller are capable of transferring commands between one another in unbalanced memory configurations. When the first memory port can no longer accept commands and a second memory... Agent: Matthew C. Zehrer Ibm Corporation

20090216961 - Multi-port semiconductor memory device for reducing data transfer event and access method therefor: A multiport semiconductor memory device includes at least three port units coupled respectively to corresponding processors, a shared memory area accessed in common by the processors through the port units, and a data path control unit for controlling a data path between the shared memory area and the port units... Agent: F. Chau & Associates, Llc

20090216962 - Prioritization of multiple concurrent threads for scheduling requests to shared memory: A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed... Agent: Microsoft Corporation

20090216963 - System, method and computer program product for providing a shared memory translation facility: A system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined if the memory address refers to a... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216965 - Storage device and access instruction sending method: A storage device for storing data sent from a host apparatus comprises a plurality of processors sending to a cache memory controller an access instruction relating to transmission of the data, based on an access request relating to the transmission of the data, the access request being sent from the... Agent: Stanley P. Fisher Reed Smith LLP

20090216964 - Virtual memory interface: The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory... Agent: Edouard Garcia Attorney At Law

20090216966 - Method, system and computer program product for storing external device result data: A method, system, and computer program product for storing result data from an external device. The method includes receiving the result data from the external device, the receiving at a system. The result data is stored into a store data buffer. The store data buffer is utilized by the system... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216967 - Computer, recording medium recording dump program, and dump method: A computer dumps information stored in a storage space used by a program, into a file when the program ends abnormally, by determining a priority representative of an order in which the information is dumped into the file, for storage areas which are predetermined areas into which the storage space... Agent: Greer, Burns & Crain

20090216968 - Method and apparatus for storing sequential sample data as memories for the purpose of rapid memory recognition using mathematic invariants: The invention described herein provides a method and apparatus for storing information in a memory structure and determining mathematical invariants in the memory structure. These invariants are then used to predict nested data patterns given only a few data elements or given incomplete data elements. The method uses a Memory... Agent: Buchanan, Ingersoll & Rooney Pc

20090216970 - Apparatus, system, and method for virtual machine backup: An apparatus, system, and method are disclosed for a virtual machine backup. A name module establishes an administrative machine name for a virtual machine. A space module associates at least one administrative name space with the administrative machine name. A backup module backs up files belonging to the virtual machine... Agent: Kunzler & Mckenzie

20090216976 - Computer system allowing any computer to copy any storage area within a storage system: A computer system having a plurality of host computers and a storage system is provided which allows any one host computer to perform a global copy operation on any arbitrary or all storage areas in the storage system. To this end, storage areas provided by the disk devices are grouped... Agent: Mattingly & Malur, P.c.

20090216973 - Computer system, storage subsystem, and data management method: To prevent, when data is erased from a storage system that stores differential of updated data, a large amount of differential data from being created, a storage subsystem provides a first storage area which stores data, and includes a second storage area which stores a replication of data stored in... Agent: Brundidge & Stanger, P.c.

20090216975 - Extending server-based desktop virtual machine architecture to client machines: A server-based desktop-virtual machines architecture may be extended to a client machine. In one embodiment, a user desktop is remotely accessed from a client system. The remote desktop is generated by a first virtual machine running on a server system, which may comprise one or more server computers. During execution... Agent: Vmware, Inc.

20090216978 - Method and apparatus for increasing an amount of memory on demand when monitoring remote mirroring performance: A method and storage system for increasing an amount of memory in a queuing area on. The storage system includes first and second storage subsystems connected to each other via a path. A primary volume in the first storage subsystem and a remote secondary volume in the second storage subsystem... Agent: Mattingly & Malur, P.c.

20090216974 - Microcomputer: A microcomputer includes a first CPU, a first bus, a first memory, a second CPU, a second bus, and a second memory. The first memory and the second memory are arranged in address spaces individually managed by the first CPU and the second CPU corresponding to the memories. An address... Agent: Miles & Stockbridge Pc

20090216969 - Remote data mirroring system: A method for data protection includes accepting data for storage from one or more data sources (24). The data is sent for storage in a primary storage device (28) and in a secondary storage device (32). While awaiting an indication of successful storage of the data in the secondary storage... Agent: D. Kligler I.p. Services Ltd

20090216971 - Storage system and copy method: In a storage system, one or more storage apparatuses provide a management computer with a first volume for storing data from the management computer, provide a host computer with a second volume for storing data from the host computer, and manage a volume address for the one or more storage... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090216977 - Storage system and snapshot data preparation method in storage system: The present invention is devised so that snapshot data preparation processing does not end abnormally as a result of the pool region becoming full with saved data from the primary logical volume during snapshot data preparation. When the CHA receives a snapshot data preparation request, the CHA checks whether or... Agent: Townsend And Townsend And Crew, LLP

20090216972 - Storage system, copy method, and primary storage apparatus: A storage system having a primary storage apparatus for storing data from a host computer in a primary logical volume, and a secondary storage apparatus connected to the primary storage apparatus, for providing a secondary logical volume for storing a copy of the data, the storage system comprising: a search... Agent: Brundidge & Stanger, P.c.

20090216980 - Information storage system: A storage media and a storage area of a storage apparatus are associated, and the storage media is used to manage the contents of the storage apparatus. A storage media for storing files is detachably mounted on an information processing apparatus, the information processing apparatus is connected to a storage... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090216979 - Method and system for secured drive level access for storage arrays: The present disclosure provides a methodology by which disk level access for storage drives of a storage array may be highly secured based on permission settings applied to the driver interface of the storage drives. Based on specific set of access rules, a security component applies security profiles to permit/deny... Agent: Lsi Corporation C/o Suiter Swantz Pc Llo

20090216981 - Power efficient flow control model for usb asynchronous transfers: Embodiments comprising a memory and a USB host controller coupled to the memory. The power efficiency of a USB during asynchronous transfers is increased by limiting usage of an asynchronous schedule stored in the memory when servicing a scheduled asynchronous transfer endpoint. Other embodiments may be described and claimed.... Agent: Schwegman, Lundberg & Woessner/intel

20090216982 - Self-locking mass storage system and method of operation thereof: A method of operation of a self-locking mass storage system includes: providing storage media and an inactivity timer; timing a period of read/write inactivity of the storage media using the inactivity timer; comparing the period of read/write inactivity against a preset maximum idle time; locking access to the storage media... Agent: Law Offices Of Mikio Ishimaru

20090216983 - Method and system for accessing memory using an auxiliary memory: A method and system for accessing memory using an auxiliary memory is presented. According to the invention store and following load instructions accessing same memory locations are identified and a temporal difference is determined. The store instructions comprise an indication for the time interval lapsing until a data element, which... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090216984 - Optimizations of a perform frame management function issued by pageable guests: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.... Agent: Heslin Rothenberg Farley & Mesiti P.c.

20090216986 - Apparatus and method for managing logical volume in distributed storage systems: A logical volume management apparatus includes a first storage unit that stores configuration information on a first stage logical volume, and a second storage unit that stores configuration information on a second stage logical volume. An access unit finds a storage area in the second stage logical volume that corresponds... Agent: Greer, Burns & Crain

20090216985 - Methods, systems, and computer program products for dynamic selective memory mirroring: Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216988 - Low overhead memory management system and method: A block of contiguous data storage locations of a memory is divided into pools of memory chunks. The memory chunks in same ones of the pools have equal chunk sizes. The memory chunks in different ones of the pools have different chunk sizes. In each of the pools, the memory... Agent: Edouard Garcia Attorney At Law

20090216987 - Method and apparatus for allocating host memory for a memory-less add-on devices: Methods and apparatus for allocating host memory for use by a host channel adapter (HCA) with insufficient on-board memory are disclosed. In one embodiment, a method includes determining when a host memory arrangement which has a host memory updates a system address map associated with the host memory, and obtaining... Agent: Patent Capital Group - Cisco

20090216989 - Storage apparatus and storage area allocation method: A storage apparatus is provided with a storage area for storing data sent from a host computer, and a virtual/logical volume to which a dynamically variable storage area is allocated from within the storage area, the volume being provided to the host computer, and this storage apparatus is configured to... Agent: Stanley P. Fisher Reed Smith LLP

20090216990 - Dynamic transactional instantiation of system configuration using a virtual file system layer: A virtual configuration system, comprising a virtualization engine and a configuration engine, for the dynamic instantiation of configuration files is disclosed. A mechanism is disclosed that allows for transactional updates to a repository of configuration settings comprising multiple files. Configuration entries are stored in a first memory location and a... Agent: Sun Microsystems, Inc C/o Marsh Fischmann & Breyfogle LLP

20090216991 - Method and apparatus to combine scattered buffer addresses into a contiguous virtual address space: A method of combining scattered buffer addresses into a contiguous virtual address space comprises; receiving a plurality of read completion data portions corresponding to a single read request, storing the plurality of read completion data portions in a memory device such that an individual read completion data portion is stored... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216992 - Dynamic address translation with translation exception qualifier: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090216993 - System and method of data forwarding within an execution unit: In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to be written to a register file from execution of a first instruction to a read identifier associated with a second instruction at an... Agent: Qualcomm Incorporated

20090216994 - Processor, method and computer program product for fast selective invalidation of translation lookaside buffer: A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216995 - System, method and computer program product for providing quiesce filtering for shared memory: A system, method and computer program product for providing quiesce filtering for shared memory. The method includes receiving a shared-memory quiesce request at a processor. The request includes a donor zone. The processor includes translation look aside buffer one (TLB1). It is determined that the shared-memory request can be filtered... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210612 - Memory controller, nonvolatile memory device, and nonvolatile memory system: In rewriting processing of logical sectors, data of the transferred logical sectors are temporarily stored in a memory buffer. When the buffer memory has been full filled with data, the data is written into a flash memory. In rewriting processing for the flash memory including a writing unit (page) having... Agent: Greenblum & Bernstein, P.L.C

20090210613 - Method for programming a controller in a motor vehicle: A method and apparatus are provided for programming of a control device of a motor vehicle, in which the control device includes at least one program-controlled processor and at least two individually addressable memory areas, in particular at least two physically separated memory components. In order to accelerate the inputting... Agent: Crowell & Moring LLP Intellectual Property Group

20090210614 - Non-volatile memories with versions of file data identified by identical file id and file offset stored in identical location within a memory page: In the file storage system, each portion belonging to a data file is identified by its file ID and an offset along the data file, where the offset is a constant for the file and every file data portion is always kept at the same position within a memory page... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20090210611 - Storage system and data write method: The size of a memory management unit in a low-performance non-volatile memory device is maintained, and the size of write data is compared with the size of the memory management unit. If the size of the write data is smaller than that of the memory management unit, the write data... Agent: Mattingly & Malur, P.C.

20090210615 - Overlay management in a flash memory storage device: The operating firmware of a portable flash memory storage device is stored in the relatively large file storage memory, which is non executable. It is logically parsed into overlays to fit into an executable memory. The overlays can be of differing sizes to organize function calls efficiently while minimizing dead... Agent: Weaver Austin Villeneuve Sampson LLP

20090210616 - Memory modules for two-dimensional main memory: In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more... Agent: Alford Law Group, Inc.

20090210617 - Multi-level volume table of contents: Methods, data structures and systems provide organize a table of contents for a volume (VTOC) stored in a storage system. The volume is divided into a plurality of ranges of tracks, including a first track range. For each track range, an associated sub-VTOC is created containing information about the contents... Agent: Law Firm Of Dan Shifrin

20090210618 - Apparatus and method to allocate resources in a data storage library: A method to allocate resources in a data storage library comprising a plurality of data storage devices configured as a RAID array, by establishing a normal operation resource allocation, a RAID failure resource allocation, and a multiple storage device failure resource allocation. The method receives host I/O requests, and enqueues... Agent: Dale F. Regelman Quarles & Brady, LLP

20090210619 - Method for handling more than a maximum number of supported drives in a raid configuration: The present invention is a method for handling disk drives in a Redundant Array of Inexpensive Disks (RAID) configuration. The method may include detecting a disk drive received via insertion of the disk drive in a disk drive slot of an enclosure of the RAID configuration. Prior to the disk... Agent: Lsi Corporation C/o Suiter Swantz PC Llo

20090210620 - Method to handle demand based dynamic cache allocation between ssd and raid cache: An apparatus and method to dynamically allocate cache in a SAN controller between a first fixed cache comprising traditional RAID cache comprised of RAM and a second, scalable RAID cache comprising of SSDs (Solid State Devices). The method is dynamic and switches between the first and second cache depending on... Agent: Lsi Corporation C/o Suiter Swantz PC Llo

20090210621 - Nonvolatile memory device, nonvolatile memory system, and access device: Power consumption required for making a nonvolatile storage device having a radio communication function operate as a file server for a radio host device is great for a host device which supplies the power. The present invention enables a user to operate a host device to which the nonvolatile storage... Agent: Greenblum & Bernstein, P.L.C

20090210622 - Compressed cache in a controller partition: A method of extending functionality of a data storage facility by adding to the primary storage system new functions using extension function subsystems is disclosed. One example of extending the functionality includes compressing and caching data in a data storage facility to improve storage and access performance of the data... Agent: Ibm - Arc Shimokaji & Associates, P.C.

20090210623 - System and article of manufacture for storing data: Provided are a system, and article of manufacture, wherein a first storage unit is coupled to a second storage unit. The first storage unit and the second storage unit are detected. A determination is made that the first storage unit is capable of responding to a write operation faster than... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20090210624 - 3-dimensional l2/l3 cache array to hide translation (tlb) delays: Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data from a cache. A subset of real address bits associated with an effective address may be retrieved relatively quickly from the... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090210625 - Self prefetching l3/l4 cache mechanism: Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data from a cache. A subset of real address bits associated with an effective address may be retrieved relatively quickly from the... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090210626 - Method, system and computer program product for cache coherency protocol with built in avoidance for conflicting responses: The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210627 - Method and system for handling cache coherency for self-modifying code: A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210628 - Computer cache system with stratified replacement: Methods for selecting a line to evict from a data storage system are provided. A computer system implementing a method for selecting a line to evict from a data storage system is also provided. The methods include selecting an uncached class line for eviction prior to selecting a cached class... Agent: Hewlett Packard Company

20090210629 - Method, system and computer program product for selectively purging cache entries: A method, system and computer program product for selectively purging entries in a cache of a computer system. The method includes determining a starting storage address and a length of the storage address range to be purged, determining preset values for a congruence class and a compartment of a cache... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210630 - Method and apparatus for prefetching data from a data structure: A method, apparatus, and computer instructions for providing hardware assistance to prefetch data during execution of code by a process or in the data processing system. In response to loading of an instruction in the code into a cache, a determination is made, by the processor unit, as to whether... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090210634 - Data transfer controller, data consistency determination method and storage controller: A data transfer controller of the present invention can determine whether or not data has been correctly stored in a cache memory even when the data is not transferred to the cache memory in sequential order. Data inputted from a host is transferred to and stored in a prescribed area... Agent: Stanley P. Fisher Reed Smith LLP

20090210633 - Method and apparatus for eliminating silent store invalidation propagation in shared memory cache coherency protocols: A method and circuit for eliminating silent store invalidation propagation in shared memory cache coherency protocols, and a design structure on which the subject circuit resides are provided. A received write data value is compared with a stored cache data value. When the received write data value matches the stored... Agent: Ibm Corporation RochesterIPLaw Dept 917

20090210632 - Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions: A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210631 - Mobile application cache system: Providing a framework for developing, deploying and managing sophisticated mobile solutions, with a simple Web-like programming model that integrates with existing enterprise components. Mobile applications may consist of a data model definition, user interface templates, a client side controller, which includes scripts that define actions, and, on the server side,... Agent: Fliesler Meyer LLP

20090210635 - Facilitating intra-node data transfer in collective communications, and methods therefor: Intra-node data transfer in collective communications is facilitated. A memory object of one task of a collective communication is concurrently attached to the address spaces of a plurality of other tasks of the communication. Those tasks that attach the memory object can access the memory object as if it was... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20090210636 - Methods and systems for two-dimensional main memory: In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more... Agent: Alford Law Group, Inc.

20090210638 - Address mapping of program code and data in memory: A system for mapping information addresses in a memory. The system includes a memory wherein each byte is mapped to a plurality of unique addresses and a microprocessor for assigning at least one of the unique addresses to the information. The information can be program code fragments and/or data. Also... Agent: Dickstein Shapiro LLP

20090210637 - Providing device parameters: A non-volatile storage device has first and second controllers that provide external access to non-volatile memory using different protocols. In response to a request from the first controller, the second controller retrieves parameters from the non-volatile memory and provides the retrieved parameters to the first controller. In one embodiment, the... Agent: Vierra Magen/sandisk Corporation

20090210639 - Apparatus and method for managing a plurality of kinds of storage devices: A storage system including a memory unit having a disk management program, plural disk controllers each having a SAS port which can be attached to either a SAS disk drive or a SATA disk drive, and a LAN port which communicates with a user interface program in a management console.... Agent: Mattingly & Malur, P.C.

20090210640 - Methods and systems for improving read performance in data de-duplication storage: The present invention is directed toward methods and systems for data de-duplication. More particularly, in various embodiments, the present invention provides systems and methods for data de-duplication that may utilize a data de-duplication system that retrieves data from a data storage device in an order based on the location of... Agent: Sheppard, Mullin, Richter & Hampton LLP

20090210642 - Point in time remote copy for multiple sites: A method for copying data to multiple remote sites includes transmitting data from a first volume in a primary storage system to a back-up volume provided in a secondary storage system. The primary storage system is located at a primary site, and the secondary storage system is located at a... Agent: Mattingly & Malur, P.C.

20090210641 - Pre-caching files from removable device to expedite perceived download performance: A method and a processing device may be provided for detecting a device newly connected to the processing device. The processing device may copy files from the device to a cache of the processing device. In some embodiments, the files may include a digital image files and associated files, such... Agent: Microsoft Corporation

20090210643 - System, method and computer program product for generating a consistent point in time copy of data: Generating a consistent point in time copy of data in a source volume and a target volume is achieved responsively to a first data modification request by writing a first altered version of the data onto a single source volume, asynchronously transferring the first altered version from the first storage... Agent: Ibm Corporation, T.j. Watson Research Center

20090210644 - Access rights on a memory map: A microcontroller system, such as a system-on-a-chip integrated circuit, including a processor (e.g., a Von Neumann processor), memory, and a memory protection unit (MPU), where the MPU provides execute-only access rights for one or more protected areas of the memory. The MPU can allow instructions fetched from within a protected... Agent: Fish & Richardson P.C.

20090210645 - Recording control apparatus, one-time recording medium, recording system, and recording medium control method and program: A recording control apparatus includes an attribute information reader, a medium determining unit, and a command transmitter. When a recording medium is removably loaded into a loading unit, the attribute information reader reads attribute information therefrom. On the basis of the attribute information, the medium determining unit determines whether or... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20090210646 - Cross adapter shared address translation tables: A method, computer program product and computer system for allocating shared address translation tables for memory regions of multiple I/O adaptors, which includes allocating an address translation table to be shared between the memory regions, creating a hardware context for each memory region, and sharing the address translation table across... Agent: Ibm Corporation

20090210647 - Method for dynamically resizing file systems: Methods (100), systems (300) and computer program products are disclosed for uninterrupted execution of an application program (110). The method (100) comprises: receiving a write operation call to a native file system from an application program (110) being executed on an operating system; and dynamically allocating (120, 122) free data... Agent: Ibm Corporation Intellectual Property Law

20090210649 - Multiprocessor computing system with multi-mode memory consistency protection: Disclosed are a method and apparatus for protecting memory consistency in a multiprocessor computing system, relating to program code conversion such as dynamic binary translation. The exemplary multiprocessor computing system provides memory and multiple processors, and a set of controller/translator units TX1, TX2, TX3 arranged to convert respective application programs... Agent: Wilmerhale/boston

20090210648 - System and computer program product for dynamically resizing file systems: Methods (100), systems (300) and computer program products are disclosed for uninterrupted execution of an application program (110). The method (100) comprises: receiving a write operation call to a native file system from an application program (110) being executed on an operating system; and dynamically allocating (120, 122) free data... Agent: Ibm Corporation Intellectual Property Law

20090210650 - Method for serializing translation lookaside buffer access around address translation parameter modification: Embodiments of the invention include a method of synchronizing translation changes in a processor including a translation lookaside buffer, the method including setting a control bit to enable blocking of all fetch requests that miss the translation lookaside buffer without changing a translation state of the current process; if there... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204743 - Storage subsystem and control method therefof: Provided is a storage subsystem capable of inhibiting the deterioration in system performance to a minimum while improving reliability and availability. This storage subsystem includes a first controller for controlling multiple drive units connected via multiple first switch devices, and a second controller for controlling the multiple drive units connected... Agent: Mattingly & Malur, P.C.

20090204750 - Direct logical block addressing flash memory mass storage architecture: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block... Agent: Leffert Jay & Polglaze, P.A.

20090204746 - Flash memory storage device for adjusting efficiency in accessing flash memory: A flash memory storage device for boosting efficiency in accessing flash memory is disclosed. The flash memory storage device provides a Multi-level cell (MLC) flash memory for storing data, a single-level cell (SLC) flash memory for storing data, and a control unit for determining whether to store a file into... Agent: Kirton And Mcconkie

20090204744 - Methods and systems for reconfiguring data memory of embedded controller managed flash memory devices: Methods and systems for reconfiguring data memory of an embedded controller managed flash memory device are disclosed. According to one method, using a controller managed flash memory device reconfiguration module configured to execute on a general purpose computing platform separate from a computing platform in which an embedded controller managed... Agent: Sandisk Corporation Jenkins, Wilson, Taylor & Hunt, P.A.

20090204748 - Multi-channel flash memory system and access method: Disclosed is a multi-channel flash memory system formed by flash memories having pages divided into sectors and accessed by corresponding channels. An interface device is configured to access the flash memories via the channels by a unit of at least one sector, wherein the interface device divides an address into... Agent: Volentine & Whitt PLLC

20090204747 - Non binary flash array architecture and method of operation: A Flash memory array comprises a plurality of Erase Sectors (Esecs) arranged in a plurality of Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs), and there is a non-binary number of at least one of the Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs).... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.

20090204745 - Programming device for non-volatile memory and programming method thereof: The invention presents a programming method for a non-volatile memory with a bit signal to be programmed unidirectionally. The method includes the steps of a) providing first data each having a first number of sequential bits of first status in a data page in a non-volatile memory, b) decoding the... Agent: Bacon & Thomas, PLLC

20090204749 - Redimdamt purge for flash storage device: A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects... Agent: Stec, Inc. C/oIPDept.

20090204751 - Multiprocessor system and portable terminal using the same: [PROBLEMS] To provide a portable terminal designated for speeding up the startup time of a multiprocessor system which is configured to be started up by a program being transferred from a specific processor to another processor. [MEANS OF SOLVING PROBLEMS] As a storing pattern of a program to a memory... Agent: Nec Corporation Of America

20090204752 - Memory device and refresh adjusting method: R

20090204753 - System for refreshing cache results: A system and method for refreshing a cache based on query responses provided by a searching system in response to queries, includes providing a cache entry for each unique query, if space is available in the cache, and assigning a temperature value to each cache entry based on a frequency... Agent: Brinks Hofer Gilson & Lione / Yahoo! Overture

20090204754 - Microprocessor and method for register addressing therein: A microprocessor architecture comprising a microprocessor operably coupled to a plurality of registers and arranged to execute at least one instruction. The microprocessor is arranged to determine a class of data operand. The at least one instruction comprises one or more codes in a register specifier that indicates whether relative... Agent: Freescale Semiconductor, Inc. Law Department

20090204755 - Multi-reader, multi-writer lock-free ring buffer: A method for accessing cells of a ring buffer by one or more writers, comprising: storing a current writer cell position value in each of a done writer index and a reserved writer index; storing a current reader cell position value in a done reader index; copying the current writer... Agent: Mccarthy Tetrault LLP

20090204756 - Method for protecting exposed data during read/modify/write operations on a sata disk drive: A method and system for saving and retrieving data includes saving data in data storage fields of a data storage device in a computer. A back-up data storage field is selected in the data storage device. A data changing operation including new data is initiated on specified data saved in... Agent: Scully, Scott, Murphy & Presser, P.C.

20090204759 - On-line volume coalesce operation to enable on-line storage subsystem volume consolidation: A mechanism to permit consolidation of storage subsystem volumes into larger, more easily managed volumes and an operating system device driver which includes a trap mechanism for intercepting calls from a host into logical unit devices that were previously consolidated into a single physical volume. A map converts such calls... Agent: Gregory Smith

20090204760 - Storage apparatus, relay device, and method of controlling operating state: Each time any one of HDDs is accessed, a corresponding relationship between the disk address of the accessed HDD and the time information indicating a time at which the HDD is accessed is added to a first operating-state management table. When a corresponding relationship with the same disk address already... Agent: Fujitsu Patent Center C/o Cpa Global

20090204758 - Systems and methods for asymmetric raid devices: An information handling system can include an asymmetric RAID device. The information handling system comprises a RAID controller and a RAID volume. The RAID volume includes a first disk and a second disk attached to the RAID controller, wherein the first disk provides faster access than the second disk. In... Agent: Larson Newman Abel & Polansky, LLP

20090204757 - Systems and methods for automatically generating a mirrored storage configuration for a storage array: An information handling system includes a plurality of storage enclosures, a plurality of logical storage units located in each storage enclosure, a controller connected to each of the plurality of logical storage units. The controller is configured to receive data regarding the plurality of logical storage units, and automatically execute... Agent: Baker Botts, LLP

20090204761 - Pseudo-lru cache line replacement for a high-speed cache: Embodiments of the present invention provide a system that replaces an entry in a least-recently-used way in a skewed-associative cache. The system starts by receiving a cache line address. The system then generates two or more indices using the cache line address. Next, the system generates two or more intermediate... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090204762 - Self test apparatus for identifying partially defective memory: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the... Agent: International Business Machines Corporation Richard Lau

20090204763 - System and method for avoiding deadlocks when performing storage updates in a multi-processor environment: A system and method for avoiding deadlocks when performing storage updates in a multi-processor environment. The system includes a processor having a local cache, a store queue having a temporary buffer with capability to reject exclusive cross-interrogates (XI) while an interrogated cache line is owned exclusive and is to be... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204764 - Cache pooling for computing systems: In a computing system a method and apparatus for cache pooling is introduced. Threads are assigned priorities based on the criticality of their tasks. The most critical threads are assigned to main memory locations such that they are subject to limited or no cache contention. Less critical threads are assigned... Agent: Honeywell International Inc. Patent Services

20090204765 - Data block frequency map dependent caching: A method for increasing the performance and utilization of cache memory by combining the data block frequency map generated by data de-duplication mechanism and page prefetching and eviction algorithms like Least Recently Used (LRU) policy. The data block frequency map provides weight directly proportional to the frequency count of the... Agent: Gregory Smith

20090204766 - Method, system, and computer program product for handling errors in a cache without processor core recovery: A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204768 - Adaptive cache sizing: A runtime code manipulation system is provided that supports code transformations on a program while it executes. The runtime code manipulation system uses code caching technology to provide efficient and comprehensive manipulation of an application running on an operating system and hardware. The code cache includes a system for automatically... Agent: Vmware, Inc.

20090204767 - Method, system and computer program product for generalized lru in cache and memory performance analysis and modeling: The exemplary embodiment of the present invention relates to a generalized LRU algorithm is provided that is associated with a specified cache associativity line set value that is determined by a system user. As configured, the LRU algorithm as presented can comprise n-levels for an LRU tree, each specified tree... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204769 - Method to bypass cache levels in a cache coherent system: Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090204770 - Device having shared memory and method for controlling shared memory: A device having a shared memory and a shared memory controlling method are disclosed. A digital processing device can include a shared memory, having a storage area including at least one common section, coupled to each of the processors through separate buses and outputting access information to whether a processor... Agent: Birch Stewart Kolasch & Birch

20090204771 - Device for controlling access from a plurality of masters to shared memory composed of a plurality of banks each having a plurality of pages: The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a... Agent: Mcdermott Will & Emery LLP

20090204772 - Memory depth optimization in communications systems with ensemble phy layer requirements: Memory depth optimization in communications systems with ensemble PHY layer requirements. Memory depth, for one or more modules in a communication device, is managed based on a limited amount of provisioned hardware. For example, each of a number of various modules within a communication device is configurable to operate at... Agent: Garlick Harrison & Markison

20090204775 - Data copying method: A method for controlling a switch apparatus connectable to a host and a storage device including first and second areas, the method includes: establishing schedule of copying data stored in the first area of the storage device into the second area of the storage device; monitoring a state of access... Agent: Staas & Halsey LLP

20090204773 - Method of writing device data in dual controller network storage environment: A method of writing device data in a dual controller network storage environment is described. According to the method, functions of a virtual data router (VD router) and a mirror technology are integrated, so as to efficiently transmit internal network data and write data into disk devices on different controllers... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090204774 - Remote copy system and method of deciding recovery point objective in remote copy system: A remote copy system comprises a primary storage system having a primary volume, and a secondary storage system having a secondary volume forming a pair relationship with the primary volume. When the primary storage system receives a write command from a primary host computer, it stores the command in the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090204777 - Integated circuits and methods to control access to multiple layers of memory: Circuits and methods to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC... Agent: Unity Semiconductor Corporation

20090204778 - Simple non-autonomous peering environment, watermarking and authentication: A Secure Non-autonomous Peering (SNAP) system includes a hierarchical digital watermarking scheme, a central licensing authority, licensed fabricators and assemblers.... Agent: Marger Johnson & Mccollom, P.C.

20090204776 - System for securing an access to flash memory device and method for the same: A system for securing an access to a flash memory is provided. The system includes a first flash memory storage device having a plurality of storage elements for storing data, and a host for accessing the first flash memory storage device. The host includes a control unit, a storing unit,... Agent: Kirton And Mcconkie

20090204779 - Controlling embedded memory access: A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090204780 - Data storage unit, data storage controlling apparatus and method, and data storage controlling program: A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware. It includes a memory controlling means including a data storage controller (20), data read... Agent: Frommer Lawrence & Haug

20090204781 - System for limiting the size of a local storage of a processor: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090204782 - System and method for safely automating the generation of multiple data definition language statements: A system and method includes steps or acts of: organizing table partitions in logical order; presenting the partition table numbers and their current ending values in logical order to a user; receiving an alter command from the user, the alter command specifying at least one logical partition number and its... Agent: Michael J. Buchenhorner

20090204783 - Systems and methods for handling addresses within a database application: A system and method store addresses within a database. An address and an address usage type that define an intended use of the address for an entity are captured. Address elements of the address are determined using an address template based upon the address usage type. If the address is... Agent: Lathrop & Gage LLP

20090204784 - Method and system for geometry-based virtual memory management: Methods, digital systems, and computer readable media are provided for managing a tiled virtual memory by maintaining a region quadtree representing a current allocation state of tiled virtual memory pages in the tiled virtual memory.... Agent: Texas Instruments Incorporated

20090204785 - Computer with two execution modes: A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a... Agent: The Law Office Of Donna L. Angotti

20090204786 - Storage system, release method, and secondary storage apparatus: The storage system includes page area association information that associates a page area that partitions a storage area in a real volume into predetermined storage areas with a page area that partitions a storage area in a virtual volume into predetermined storage areas; a pair setting unit for pairing a... Agent: Stanley P. Fisher Reed Smith LLP

20090204743 - Storage subsystem and control method therefof: Provided is a storage subsystem capable of inhibiting the deterioration in system performance to a minimum while improving reliability and availability. This storage subsystem includes a first controller for controlling multiple drive units connected via multiple first switch devices, and a second controller for controlling the multiple drive units connected... Agent: Mattingly & Malur, P.C.

20090204750 - Direct logical block addressing flash memory mass storage architecture: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block... Agent: Leffert Jay & Polglaze, P.A.

20090204746 - Flash memory storage device for adjusting efficiency in accessing flash memory: A flash memory storage device for boosting efficiency in accessing flash memory is disclosed. The flash memory storage device provides a Multi-level cell (MLC) flash memory for storing data, a single-level cell (SLC) flash memory for storing data, and a control unit for determining whether to store a file into... Agent: Kirton And Mcconkie

20090204744 - Methods and systems for reconfiguring data memory of embedded controller managed flash memory devices: Methods and systems for reconfiguring data memory of an embedded controller managed flash memory device are disclosed. According to one method, using a controller managed flash memory device reconfiguration module configured to execute on a general purpose computing platform separate from a computing platform in which an embedded controller managed... Agent: Sandisk Corporation Jenkins, Wilson, Taylor & Hunt, P.A.

20090204748 - Multi-channel flash memory system and access method: Disclosed is a multi-channel flash memory system formed by flash memories having pages divided into sectors and accessed by corresponding channels. An interface device is configured to access the flash memories via the channels by a unit of at least one sector, wherein the interface device divides an address into... Agent: Volentine & Whitt PLLC

20090204747 - Non binary flash array architecture and method of operation: A Flash memory array comprises a plurality of Erase Sectors (Esecs) arranged in a plurality of Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs), and there is a non-binary number of at least one of the Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs).... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.

20090204745 - Programming device for non-volatile memory and programming method thereof: The invention presents a programming method for a non-volatile memory with a bit signal to be programmed unidirectionally. The method includes the steps of a) providing first data each having a first number of sequential bits of first status in a data page in a non-volatile memory, b) decoding the... Agent: Bacon & Thomas, PLLC

20090204749 - Redimdamt purge for flash storage device: A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects... Agent: Stec, Inc. C/oIPDept.

20090204751 - Multiprocessor system and portable terminal using the same: [PROBLEMS] To provide a portable terminal designated for speeding up the startup time of a multiprocessor system which is configured to be started up by a program being transferred from a specific processor to another processor. [MEANS OF SOLVING PROBLEMS] As a storing pattern of a program to a memory... Agent: Nec Corporation Of America

20090204752 - Memory device and refresh adjusting method: R

20090204753 - System for refreshing cache results: A system and method for refreshing a cache based on query responses provided by a searching system in response to queries, includes providing a cache entry for each unique query, if space is available in the cache, and assigning a temperature value to each cache entry based on a frequency... Agent: Brinks Hofer Gilson & Lione / Yahoo! Overture

20090204754 - Microprocessor and method for register addressing therein: A microprocessor architecture comprising a microprocessor operably coupled to a plurality of registers and arranged to execute at least one instruction. The microprocessor is arranged to determine a class of data operand. The at least one instruction comprises one or more codes in a register specifier that indicates whether relative... Agent: Freescale Semiconductor, Inc. Law Department

20090204755 - Multi-reader, multi-writer lock-free ring buffer: A method for accessing cells of a ring buffer by one or more writers, comprising: storing a current writer cell position value in each of a done writer index and a reserved writer index; storing a current reader cell position value in a done reader index; copying the current writer... Agent: Mccarthy Tetrault LLP

20090204756 - Method for protecting exposed data during read/modify/write operations on a sata disk drive: A method and system for saving and retrieving data includes saving data in data storage fields of a data storage device in a computer. A back-up data storage field is selected in the data storage device. A data changing operation including new data is initiated on specified data saved in... Agent: Scully, Scott, Murphy & Presser, P.C.

20090204759 - On-line volume coalesce operation to enable on-line storage subsystem volume consolidation: A mechanism to permit consolidation of storage subsystem volumes into larger, more easily managed volumes and an operating system device driver which includes a trap mechanism for intercepting calls from a host into logical unit devices that were previously consolidated into a single physical volume. A map converts such calls... Agent: Gregory Smith

20090204760 - Storage apparatus, relay device, and method of controlling operating state: Each time any one of HDDs is accessed, a corresponding relationship between the disk address of the accessed HDD and the time information indicating a time at which the HDD is accessed is added to a first operating-state management table. When a corresponding relationship with the same disk address already... Agent: Fujitsu Patent Center C/o Cpa Global

20090204758 - Systems and methods for asymmetric raid devices: An information handling system can include an asymmetric RAID device. The information handling system comprises a RAID controller and a RAID volume. The RAID volume includes a first disk and a second disk attached to the RAID controller, wherein the first disk provides faster access than the second disk. In... Agent: Larson Newman Abel & Polansky, LLP

20090204757 - Systems and methods for automatically generating a mirrored storage configuration for a storage array: An information handling system includes a plurality of storage enclosures, a plurality of logical storage units located in each storage enclosure, a controller connected to each of the plurality of logical storage units. The controller is configured to receive data regarding the plurality of logical storage units, and automatically execute... Agent: Baker Botts, LLP

20090204761 - Pseudo-lru cache line replacement for a high-speed cache: Embodiments of the present invention provide a system that replaces an entry in a least-recently-used way in a skewed-associative cache. The system starts by receiving a cache line address. The system then generates two or more indices using the cache line address. Next, the system generates two or more intermediate... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090204762 - Self test apparatus for identifying partially defective memory: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the... Agent: International Business Machines Corporation Richard Lau

20090204763 - System and method for avoiding deadlocks when performing storage updates in a multi-processor environment: A system and method for avoiding deadlocks when performing storage updates in a multi-processor environment. The system includes a processor having a local cache, a store queue having a temporary buffer with capability to reject exclusive cross-interrogates (XI) while an interrogated cache line is owned exclusive and is to be... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204764 - Cache pooling for computing systems: In a computing system a method and apparatus for cache pooling is introduced. Threads are assigned priorities based on the criticality of their tasks. The most critical threads are assigned to main memory locations such that they are subject to limited or no cache contention. Less critical threads are assigned... Agent: Honeywell International Inc. Patent Services

20090204765 - Data block frequency map dependent caching: A method for increasing the performance and utilization of cache memory by combining the data block frequency map generated by data de-duplication mechanism and page prefetching and eviction algorithms like Least Recently Used (LRU) policy. The data block frequency map provides weight directly proportional to the frequency count of the... Agent: Gregory Smith

20090204766 - Method, system, and computer program product for handling errors in a cache without processor core recovery: A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204768 - Adaptive cache sizing: A runtime code manipulation system is provided that supports code transformations on a program while it executes. The runtime code manipulation system uses code caching technology to provide efficient and comprehensive manipulation of an application running on an operating system and hardware. The code cache includes a system for automatically... Agent: Vmware, Inc.

20090204767 - Method, system and computer program product for generalized lru in cache and memory performance analysis and modeling: The exemplary embodiment of the present invention relates to a generalized LRU algorithm is provided that is associated with a specified cache associativity line set value that is determined by a system user. As configured, the LRU algorithm as presented can comprise n-levels for an LRU tree, each specified tree... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204769 - Method to bypass cache levels in a cache coherent system: Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090204770 - Device having shared memory and method for controlling shared memory: A device having a shared memory and a shared memory controlling method are disclosed. A digital processing device can include a shared memory, having a storage area including at least one common section, coupled to each of the processors through separate buses and outputting access information to whether a processor... Agent: Birch Stewart Kolasch & Birch

20090204771 - Device for controlling access from a plurality of masters to shared memory composed of a plurality of banks each having a plurality of pages: The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a... Agent: Mcdermott Will & Emery LLP

20090204772 - Memory depth optimization in communications systems with ensemble phy layer requirements: Memory depth optimization in communications systems with ensemble PHY layer requirements. Memory depth, for one or more modules in a communication device, is managed based on a limited amount of provisioned hardware. For example, each of a number of various modules within a communication device is configurable to operate at... Agent: Garlick Harrison & Markison

20090204775 - Data copying method: A method for controlling a switch apparatus connectable to a host and a storage device including first and second areas, the method includes: establishing schedule of copying data stored in the first area of the storage device into the second area of the storage device; monitoring a state of access... Agent: Staas & Halsey LLP

20090204773 - Method of writing device data in dual controller network storage environment: A method of writing device data in a dual controller network storage environment is described. According to the method, functions of a virtual data router (VD router) and a mirror technology are integrated, so as to efficiently transmit internal network data and write data into disk devices on different controllers... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090204774 - Remote copy system and method of deciding recovery point objective in remote copy system: A remote copy system comprises a primary storage system having a primary volume, and a secondary storage system having a secondary volume forming a pair relationship with the primary volume. When the primary storage system receives a write command from a primary host computer, it stores the command in the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090204777 - Integated circuits and methods to control access to multiple layers of memory: Circuits and methods to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC... Agent: Unity Semiconductor Corporation

20090204778 - Simple non-autonomous peering environment, watermarking and authentication: A Secure Non-autonomous Peering (SNAP) system includes a hierarchical digital watermarking scheme, a central licensing authority, licensed fabricators and assemblers.... Agent: Marger Johnson & Mccollom, P.C.

20090204776 - System for securing an access to flash memory device and method for the same: A system for securing an access to a flash memory is provided. The system includes a first flash memory storage device having a plurality of storage elements for storing data, and a host for accessing the first flash memory storage device. The host includes a control unit, a storing unit,... Agent: Kirton And Mcconkie

20090204779 - Controlling embedded memory access: A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090204780 - Data storage unit, data storage controlling apparatus and method, and data storage controlling program: A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware. It includes a memory controlling means including a data storage controller (20), data read... Agent: Frommer Lawrence & Haug

20090204781 - System for limiting the size of a local storage of a processor: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090204782 - System and method for safely automating the generation of multiple data definition language statements: A system and method includes steps or acts of: organizing table partitions in logical order; presenting the partition table numbers and their current ending values in logical order to a user; receiving an alter command from the user, the alter command specifying at least one logical partition number and its... Agent: Michael J. Buchenhorner

20090204783 - Systems and methods for handling addresses within a database application: A system and method store addresses within a database. An address and an address usage type that define an intended use of the address for an entity are captured. Address elements of the address are determined using an address template based upon the address usage type. If the address is... Agent: Lathrop & Gage LLP

20090204784 - Method and system for geometry-based virtual memory management: Methods, digital systems, and computer readable media are provided for managing a tiled virtual memory by maintaining a region quadtree representing a current allocation state of tiled virtual memory pages in the tiled virtual memory.... Agent: Texas Instruments Incorporated

20090204785 - Computer with two execution modes: A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a... Agent: The Law Office Of Donna L. Angotti

20090204786 - Storage system, release method, and secondary storage apparatus: The storage system includes page area association information that associates a page area that partitions a storage area in a real volume into predetermined storage areas with a page area that partitions a storage area in a virtual volume into predetermined storage areas; a pair setting unit for pairing a... Agent: Stanley P. Fisher Reed Smith LLP

20090198865 - Data processing system, processor and method that perform a partial cache line storage-modifying operation based upon a hint: In at least one embodiment, a method of data processing in a data processing system having a memory hierarchy includes a processor core executing a storage-modifying memory access instruction to determine a memory address. The processor core transmits to a cache memory within the memory hierarchy a storage-modifying memory access... Agent: Dillon & Yudell LLP

20090198866 - Code memory capable of code provision for a plurality of physical channels: The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090198867 - Method for chaining multiple smaller store queue entries for more efficient store queue usage: A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090198868 - Method of accessing virtual storage device through virtual data router: A method of accessing a virtual storage device through a virtual data router (VD router) is described. A virtual disk device on a controller may be accessed from various controllers through different paths based on asynchrony of data sending/receiving of a VD router. Moreover, the method is advantageous in having... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090198875 - Data writing method for flash memory, and controller and system using the same: A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for... Agent: J C Patents, Inc.

20090198869 - Erase count recovery: An erase count of a flash memory block which is lost, e.g., due to power failure is updated or replaced by using known erase counts of other blocks of the flash memory. A flash management algorithm assigns a new erase count value instead of the lost one based on either... Agent: Mark M. Friedman

20090198871 - Expansion slots for flash memory based memory subsystem: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or... Agent: Turocy & Watson, LLP

20090198872 - Hardware based wear leveling mechanism: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or... Agent: Turocy & Watson, LLP

20090198878 - Information processing system and information processing method: The information processing system is comprised of: a first nonvolatile storage device in which a plurality of first programs for initiating the information processing system, and duplications of the plural first programs have been stored in blocks different from each other; a second volatile storage device to which the plurality... Agent: Mcdermott Will & Emery LLP

20090198879 - Memory system and method of controlling the same: A memory system has a memory unit composed of a plurality of memory cells, a memory controller for controlling to read out and write data from and to the memory unit, and a host processor connected to the memory controller for reading out and writing data from and to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090198870 - Methods and media for writing data to flash memory: A method for writing bytes to flash memory is disclosed herein whereby the method comprising includes counting bytes from a data source, the bytes associated with a first value and a second value and comparing a number of bytes associated with the first value with a number of bytes associated... Agent: Andrea E. Tran Pramudji Wendt & Tran, LLP

20090198874 - Mitigate flash write latency and bandwidth limitation: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or... Agent: Turocy & Watson, LLP

20090198873 - Partial allocate paging mechanism: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or... Agent: Turocy & Watson, LLP

20090198876 - Programmable command sequencer: An embedded subsystem IC which provides simple procedures for an external CPU IC to invoke one or more functions provided by modules of the subsystem is disclosed. The embedded subsystem comprises at least one module to perform at least one function, a first memory, and a sequence controller. Each module... Agent: Epson Research And Development Inc Intellectual Property Dept

20090198880 - Read strobe feedback in a memory system: A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed... Agent: Attn: Kenneth W. Bolvin Leffert Jay & Polglaze, P.A.

20090198877 - System, controller, and method for data storage: A system, a controller, and a method for data storage are provided. The system includes a first storage unit, a second storage unit, and a controller. The first storage unit comprises a single-layer structure for storing data, and the second storage unit comprises a multi-layer structure for storing data. The... Agent: J C Patents, Inc.

20090198881 - Memory system: A memory system including: a memory device; an ECC system installed in the memory device so as to generate a warning signal in case there are uncorrectable errors; an address generating circuit for generating internal addresses in place of bad area addresses in accordance with the waning signal, the progressing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090198882 - Method of wear leveling for non-volatile memory and apparatus using the same: A method of wear leveling for a non-volatile memory is disclosed. A non-volatile memory is divided into windows and gaps, with each gap between two adjacent windows. The windows comprise physical blocks mapped to logical addresses, and the gaps comprise physical blocks not mapped to logical addresses. The windows are... Agent: Wpat, PC Intellectual Property Attorneys

20090198883 - Data copy management for faster reads: Multiple copy sets of data are maintained on one or more storage devices. Each copy set includes at least some of the same data units as other sets. Different sets optionally have data units stored in different orders on the storage device(s). A particular one of the sets of data... Agent: Microsoft Corporation

20090198884 - Reduced hard-drive-capacity detection device: The present disclosure relates to a device for detecting accessible capacity in an external hard drive. The disclosed device may detect reduced accessible capacity in an external hard drive due to an modification or deletion of either the Host-Protected Area or the Device Configuration Overlay table.... Agent: Kolisch Hartwell, P.C.

20090198888 - Disk array system: Provided is a disk array system which is connected to a computer and which data is transmitted by the computer, including: a plurality of disk drives for storing user data transmitted by the computer; a cache memory for temporarily storing data sent/received among the computer and the plurality of disk... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090198886 - Power conservation in a composite array of data storage devices: Operating a composite array of data storage devices, such as hard disk drives, to conserve power includes storing data in block-level stripes with parity on a composite array including a controller and at least three data storage devices. The composite array includes a hot spare distributed across the data storage... Agent: Ibm Corporation (ss/nc) C/o Streets & Steele

20090198887 - Storage system: A storage group configured by a plurality of storage devices is configured by a plurality of storage sub-groups, and the respective storage sub-groups are configured from two or more storage devices. A sub-group storage area, which is the storage area of the respective storage sub-groups, is configured by a plurality... Agent: Brundidge & Stanger, P.C.

20090198885 - System and methods for host software stripe management in a striped storage subsystem: Systems and methods for coalescing host generated write requests in a RAID software driver module to generate full stripe write I/O operations to storage devices. Where RAID management is implemented exclusively in software features and aspects hereof improve performance by using full stripe write operations instead of slower read-modify-write operations.... Agent: Duft Bornsen & Fishman LLP

20090198889 - Recording apparatus, recording method, program for recording method, and storage medium that stores program for recording method: A recording apparatus includes: a type detecting section that detects a type of storage medium; an erase-block size detecting section that detects an erase-block size of the storage medium; a recording section that records desired data to a data area in the storage medium and records management information of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090198890 - Method of searching neighboring cell address in same resolution octree structure: Disclosed is a method of searing an address in the octree structure having the same resolution. The method of searching address values of the neighboring cells in the octree structure having the same resolution can include performing address encoding of octree cells by giving an inherent address value that is... Agent: Neal, Gerber, & Eisenberg

20090198891 - Issuing global shared memory operations via direct cache injection to a host fabric interface: A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel... Agent: Dillon & Yudell LLP

20090198894 - Method of updating ic instruction and data cache: A method of updating a cache in an integrated circuit is provided. The integrated circuit incorporates the cache, memory and a memory interface connected to the cache and memory. Following a cache miss, the method fetches, using the memory interface, first data associated with the cache miss and second data... Agent: Silverbrook Research Pty Ltd

20090198893 - Microprocessor systems: m

20090198892 - Rapid caching and data delivery system and method: The initial systems analysis of a new data source fully defines each data element and also designs, tests and encodes complete data integration instructions for each data element. A metadata cache stores the data element definition and data element integration instructions. The metadata cache enables a comprehensive view of data... Agent: Snell & Wilmer L.L.P. (amex)

20090198895 - Control method, memory, and processing system utilizing the same: A control method for a memory is provided. The memory includes a plurality of storage units, each storing a plurality of bits. In a read mode, a read command is provided to the memory. The value of a most significant bit (MSB) of each storage unit is obtained and recorded.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090198896 - Dual writing device and its control method: A first storage system sets a storage area of a first disk drive as a first volume, and misrepresents an identifier of the storage system and an identifier of the first volume. A second storage system sets a storage area of a second disk drive as a second volume, and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090198897 - Cache management during asynchronous memory move operations: A data processing system includes a mechanism for completing an asynchronous memory move (AMM) operation in which the processor receives an AMM ST instruction and processes a processor-level move of data in virtual address space and an asynchronous memory mover then completes a physical move of the data within the... Agent: Dillon & Yudell LLP

20090198898 - Parallel data processing apparatus: A controller for controlling a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, comprises a retrieval unit operable to retrieve a plurality of incoming instructions streams in parallel with one another, and a distribution unit operable to supply such incoming instruction... Agent: Glenn Patent Group

20090198900 - Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme: Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way predictor, a policy counter, and a cache refill circuit. The policy counter provides a signal to the way predictor that determines whether the way predictor... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090198899 - System and method for transactional cache: A computer-implemented method and system to support transactional caching service comprises configuring a transactional cache that are associated with one or more transactions and one or more work spaces; maintaining an internal mapping between the one or more transactions and the one or more work spaces in a transactional decorator;... Agent: Fliesler Meyer LLP

20090198901 - Computer system and method for controlling the same: A computer system includes a main memory for storing a large amount of data, a cache memory that can be accessed at a higher speed than the main memory, a memory replacement controller for controlling the replacement of data between the main memory and the cache memory, and a memory... Agent: Mcdermott Will & Emery LLP

20090198902 - Memory mapping techniques: Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the... Agent: Fish & Richardson P.C.

20090198903 - Data processing system, processor and method that vary an amount of data retrieved from memory based upon a hint: In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from... Agent: Dillon & Yudell LLP

20090198907 - Dynamic adjustment of prefetch stream priority: A method, processor, and data processing system for dynamically adjusting a prefetch stream priority based on the consumption rate of the data by the processor. The method includes a prefetch engine issuing a prefetch request of a first prefetch stream to fetch one or more data from the memory subsystem.... Agent: Dillon & Yudell LLP

20090198909 - Jump starting prefetch streams across page boundaries: A method, processor, and data processing system for enabling utilization of a single prefetch stream to access data across a memory page boundary. A prefetch engine includes an active streams table in which information for one or more scheduled prefetch streams are stored. The prefetch engine also includes a victim... Agent: Dillon & Yudell LLP

20090198908 - Method for enabling direct prefetching of data during asychronous memory move operation: While an AMM operation is ongoing, a prefetch request for data from the source effective address or the destination effective address triggers a cache injection by the AMM mover (or memory controller) of relevant data from the stream of data being moved in the physical memory. The memory controller forwards... Agent: Dillon & Yudell LLP

20090198904 - Techniques for data prefetching using indirect addressing with offset: A technique for performing data prefetching using indirect addressing includes determining a first memory address of a pointer associated with a data prefetch instruction. Content, that is included in a first data block (e.g., a first cache line) of a memory, at the first memory address is then fetched. An... Agent: Dillon & Yudell LLP

20090198906 - Techniques for multi-level indirect data prefetching: A technique for performing data prefetching using multi-level indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content that is included in a first data block (e.g., a first cache line of a memory) at the first memory address is then... Agent: Dillon & Yudell LLP

20090198905 - Techniques for prediction-based indirect data prefetching: A technique for data prefetching using indirect addressing includes monitoring data pointer values, associated with an array, in an access stream to a memory. The technique determines whether a pattern exists in the data pointer values. A prefetch table is then populated with respective entries that correspond to respective array... Agent: Dillon & Yudell LLP

20090198911 - Data processing system, processor and method for claiming coherency ownership of a partial cache line of data: According to method of data processing in a multiprocessor data processing system, in response to a processor request to modify a target granule of a target cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a data-claim-partial request that... Agent: Dillon & Yudell LLP

20090198912 - Data processing system, processor and method for implementing cache management for partial cache line operations: A method of data processing in a cache memory includes caching a plurality of cache lines of data in a corresponding plurality of entries in a cache array, where each of the plurality of cache lines includes multiple data granules. For each of the plurality of cache entries, a plurality... Agent: Dillon & Yudell LLP

20090198910 - Data processing system, processor and method that support a touch of a partial cache line of data: According to method of data processing in a multiprocessor data processing system, in response to a processor touch request targeting a target granule of a cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial touch request that... Agent: Dillon & Yudell LLP

20090198913 - Two-hop source snoop based messaging protocol: A messaging protocol that facilitates a distributed cache coherency conflict resolution in a multi-node system that resolves conflicts at a home node. The protocol may perform a method including supporting at least three protocol classes for the messaging protocol, via at least three virtual channels provided by a link layer... Agent: Trop, Pruner & Hu, P.C.

20090198914 - Data processing system, processor and method in which an interconnect operation indicates acceptability of partial data delivery: According to at least one embodiment, a method of data processing in a multiprocessor data processing system includes a requesting processing unit initiating an interconnect operation including a memory access request that indicates an acceptability of a variable amount of data to service the interconnect request for data. In response... Agent: Dillon & Yudell LLP

20090198915 - Data processing system, processor and method that dynamically select a memory access size: A method of data processing in a processing unit supported by a memory hierarchy includes the processing unit performing a plurality of memory accesses to the memory hierarchy. The plurality of memory accesses includes one or more memory accesses targeting a full cache line of data. The processing unit monitors... Agent: Dillon & Yudell LLP

20090198916 - Method and apparatus for supporting low-overhead memory locks within a multiprocessor system: A method for supporting low-overhead memory locks within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system,... Agent: Dillon & Yudell LLP

20090198917 - Specialized memory move barrier operations: An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM... Agent: Dillon & Yudell LLP

20090198918 - Host fabric interface (hfi) to perform global shared memory (gsm) operations: A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel... Agent: Dillon & Yudell LLP

20090198919 - A non-volatile memory device, and method of accessing a non-volatile memory device: A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20090198923 - Apparatus for predicting memory access and method thereof: A method for predicting memory access, where each data processing procedure is performed in a plurality of stages with segment processing, and the plurality of stages include at least a first stage and a second stage, includes: dividing a memory into a plurality of memory blocks, generating a predicting value... Agent: North America Intellectual Property Corporation

20090198921 - Data processing system, processor and method of data processing having reduced aliasing in branch logic: In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where... Agent: Dillon & Yudell LLP

20090198922 - File-copying apparatus of portable storage media: The present invention provides a portable file-copying apparatus which includes a first connecting unit, a second connecting unit, and a control unit. The first connecting unit can receive a first portable storage media which includes an original file. The second connecting unit can receive a second portable storage media. Furthermore,... Agent: Birch Stewart Kolasch & Birch

20090198924 - Memory system topologies including a buffer device and an integrated circuit memory device: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices... Agent: Deniro/rambus

20090198920 - Processing units within a multiprocessor system adapted to support memory locks: A processing unit within a multiprocessor system adapted to support memory locks is disclosed. In response to a request for accessing a data block being denied when a lock control section of the data block has been set by a memory controller, a timer countdown is started within a processing... Agent: Dillon & Yudell LLP

20090198925 - Apparatus and method for memory migration in a distributed memory multiprocessor system: p

20090198926 - Method and device for switching data: A method, the method includes providing data; retrieving interleaving command information from a two dimensional array of interleaving command information; wherein the two dimensional array includes multiple interleaving command information rows, each row includes interleaving commands associated with multiple TDM time slots; and determining, in response to the retrieved interleaving... Agent: Freescale Semiconductor, Inc. Law Department

20090198927 - Methods for implementation of worm mode on a removable disk drive storage system: Embodiments provide systems and methods for maintaining immutable data in an archiving system using random access memory. To ensure data is immutable, novel pointers are maintained in the hardware/firmware of the drive ports and on the removable disk drives. For example, a hardware/firmware in a modular drive bay maintains a... Agent: Townsend And Townsend And Crew, LLP

20090198930 - Information backup system for handheld devices: An information backup system [700] is provided including receiving information from a memory in a handheld device [104]; writing the information into a removable non-volatile memory [106] in an information backup device [102]; and rewriting the information from the removable non-volatile memory [106] into a different handheld device [204].... Agent: Law Offices Of Mikio Ishimaru

20090198931 - Information processing apparatus and data backup method: An information processing apparatus includes a battery for providing the interior of the information processing apparatus with power; a volatile memory for storing data; a nonvolatile memory for backupping the data stored in the volatile memory; a controller for controlling backup of the data in accordance with a process comprising... Agent: Staas & Halsey LLP

20090198928 - Method and system for providing data backup to multiple storage media: A method and system for providing automatic data backup to multiple storage media is disclosed herein. An archive pack is used as a data backup and the archive pack comprises: plurality of storage media arranged as pairs, the storage media in the pair are configured to function independently and only... Agent: Peter Vogel Ge Healthcare

20090198929 - Storage control device and method for managing snapshot: An erasure declaration-related write request is received. In cases where, in response to the erasure declaration-related write request, erasure-corresponding data elements which are data elements corresponding to an erasure target and which are stored in a storage area A in the first logical volume are overwritten with erasure data elements... Agent: Brundidge & Stanger, P.C.

20090198934 - Fully asynchronous memory mover: A data processing system has a processor and a memory coupled to the processor and an asynchronous memory mover coupled to the processor. The asynchronous memory mover has registers for receiving a set of parameters from the processor, which parameters are associated with an asynchronous memory move (AMM) operation initiated... Agent: Dillon & Yudell LLP

20090198933 - Method and apparatus for handling multiple memory requests within a multiprocessor system: A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the... Agent: Dillon & Yudell LLP

20090198932 - Secure direct platter access: Bulk data transfers by directly accessing a persistent and secured area on the data storage device, e.g., a disk drive having a magnetic storage medium, without relying on the system operating system to execute its read/write operations. For a disk drive, the Protected Area Run Time Interface Extension (PARTIES) technology... Agent: Seagate Technology LLC C/o Westman, Champlin & Kelly, P.A.

20090198940 - Apparatus, system, and method for relocating logical array hot spots: An apparatus, system, and method are disclosed for relocating logical array hot spots. An organization module organizes a plurality of logical arrays. Each logical array comprises a plurality of logical segments from a plurality of storage devices and configured to store data. An identification module identifies a hot spot on... Agent: Kunzler & Mckenzie

20090198938 - Handling of address conflicts during asynchronous memory move operations: A method within a data processing system in which a processor handles conflicts, which occur during performance by an asynchronous memory mover of an asynchronous memory move (AMM) operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation by which the actual data is moved from a source... Agent: Dillon & Yudell LLP

20090198939 - Launching multiple concurrent memory moves via a fully asynchronoous memory mover: A data processing system has an asynchronous memory mover, which includes multiple sets of registers for storing addressing and control parameters utilized to generate one or more asynchronous memory move (AMM) operations. The memory mover detects a receipt of a first set of parameters in a first set of registers... Agent: Dillon & Yudell LLP

20090198937 - Mechanisms for communicating with an asynchronous memory mover to perform amm operations: A data processing system includes a set of architected registers within which the processor places state and other information to communicate with the asynchronous memory mover in order to initiate and control an AMM operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation in response to receiving... Agent: Dillon & Yudell LLP

20090198935 - Method and system for performing an asynchronous memory move (amm) via execution of amm store instruction within instruction set architecture: A data processing system with a processor and memory includes an instruction set architecture (ISA) that provides an asynchronous memory move (AMM) store (ST) instruction. When the processor executes the AMM ST instruction, the processor performs a series of functions, which initiates an asynchronous memory move (AMM) operation. The AMM... Agent: Dillon & Yudell LLP

20090198936 - Reporting of partially performed memory move: A method performed in a data processing system initiates an asynchronous memory move (AMM) operation, whereby a processor performs a move of data in virtual address space from a first effective address to a second effective address and forwards parameters of the AMM operation to asynchronous memory mover logic for... Agent: Dillon & Yudell LLP

20090198941 - Computer system with addressable storage medium: A computer system with an addressable medium is disclosed. The computer system comprises an addressable medium subsystem, a microprocessor and at least one input/output device. The addressable medium subsystem includes: a control logic which has a control circuit with an address table for storing a plurality of addresses, and an... Agent: Wpat, PC

20090198943 - Semiconductor exposure apparatus, control method, and computer-readable storage medium: A semiconductor exposure apparatus which executes a plurality of jobs each including at least one application program is provided. The apparatus includes a memory configured to be used to execute the application program, an application program execution management unit configured to manage execution of the application program included in the... Agent: Fitzpatrick Cella Harper & Scinto

20090198942 - Storage system provided with a plurality of controller modules: A plurality of global LDEV managed by a plurality of controller modules are provided above local LDEV under the control of each controller module. Each global LDEV is correlated to any of the plurality of local LDEV. The controller modules judge whether or not a local LDEV correlated to a... Agent: Brundidge & Stanger, P.C.

20090198946 - Computer system and garbage collection method of disk space: A processor of a management computer acquires the free disk space amount of a disk pool, acquires the invalid disk space amount from a plurality of host computers, determines a host computer to which the instruction for the physical disk space collection is issued on the basis of the invalid... Agent: Stanley P. Fisher Reed Smith LLP

20090198944 - Semiconductor memory device: An adaptive semiconductor memory device is used for being inserted into a host for storage. The semiconductor memory device comprises a non-volatile memory and a switch. The switch can be a logical switch or a physical switch that controls the semiconductor memory device to be in compliance with either a... Agent: Wpat, PC Intellectual Property Attorneys

20090198945 - System and method for configuring storage resources for database storage: A system and method for configuring storage resources for database storage are disclosed. A method may include mapping at least one first tablespace having a first block size to at least one first logical unit. The method may also include mapping the at least one first tablespace and the at... Agent: Baker Botts, LLP

20090198947 - Memory mapping restore and garbage collection operations: Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the... Agent: Fish & Richardson P.C.

20090198949 - Hypervolume data storage object and method of data storage: The present disclosure relates to a data storage device having a hypervolume accessible by a plurality of servers operating on two or more data storage systems, a first physical volume, associated with the hypervolume, located at a first data storage system, and a second physical volume, associated with the hypervolume,... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090198948 - Techniques for data prefetching using indirect addressing: A technique for performing indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content of a memory at the first memory address is then fetched. A second memory address is determined from the content of the memory at the first memory... Agent: Dillon & Yudell LLP

20090198950 - Techniques for indirect data prefetching: A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The prefetch engine is coupled to the first translation engine and... Agent: Dillon & Yudell LLP

20090198951 - Full virtualization of resources across an ip interconnect: An addressing model is provided where all resources, including memory and devices, are addressed with internet protocol (IP) addresses. A task, such as an application, may be assigned a range of IP addresses rather than an effective address range. Thus, a processing element, such as an I/O adapter or even... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090198952 - Memory mapping architecture: Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the... Agent: Fish & Richardson P.C.

20090198953 - Full virtualization of resources across an ip interconnect using page frame table: An addressing model is provided where devices, including I/O devices, are addressed with internet protocol (IP) addresses, which are considered part of the virtual address space. A task, such as an application, may be assigned an effective address range, which corresponds to addresses in the virtual address space. The virtual... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090198954 - Method and system for generating location codes: The present disclosure provides a method for generating a standardized location code is provided that comprises extracting an address component from an input location data record, parsing the address component into one or more address words, and processing the address words by validating the address words one by one using... Agent: Docket Clerk, Dm/eds

20090198955 - Asynchronous memory move across physical nodes (dual-sided communication for memory move): A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the... Agent: Dillon & Yudell LLP