Electrical computers and digital processing systems: memory inventions 07/09

20090193173 - Secure virtual environment for providing tests: Aspects of the subject matter described herein relate to a secure virtual environment for providing tests to test takers. In aspects, a testing environment is set up that includes one or more virtual machines. A view to the virtual machines is provided to a test taking station on which a... Agent: Microsoft Corporation

20090193174 - Read disturbance management in a non-volatile memory system: An invention is provided for read disturbance management in a non-volatile memory. The invention includes storing a read count data for a memory location in non-volatile memory. The read count data indicating an amount of read operations accessing the memory location since data was last written to the memory location.... Agent: Patent Venture Group

20090193175 - Identification of an onboard memory buffer device from a system address: Disclosed herein are techniques and methods for identifying a target onboard memory buffer device from a system address of a computer system. The techniques and methods can be employed in a computer system having a system controller, main memory having memory devices, and onboard memory buffer devices between the system... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090193181 - Control unit, image processing apparatus and computer-readable storage medium: A memory information storage control method is executed by a control unit which carries out a memory information storage process to generate memory information related to a program being executed by the control unit and to store the memory information. The memory information storage control method includes an interface process... Agent: Ipusa, P.l.l.c

20090193176 - Data storage device having a built-in display: A data storage device for an electronic device includes a hard disk for storing a plurality of pieces of data, a nonvolatile memory for storing a plurality of file names corresponding to the pieces of data, a display, and a controller connected electrically to the hard disk, the nonvolatile memory... Agent: Paul D. Greeley Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20090193184 - Hybrid 2-level mapping tables for hybrid block- and page-mode flash-memory system: A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but... Agent: Stuart T Auvinen

20090193179 - Information processing apparatus: A main memory and a hard disk include predetermined serial numbers. A flash memory registers the main memory and hard disk together with their serial numbers. A BIOS reads the serial numbers from the main memory and hard disk. When a read-out serial number is not registered in the flash... Agent: Staas & Halsey LLP

20090193182 - Information storage device and control method thereof: According to one embodiment, an information storage device includes a non-volatile storage medium, a non-volatile memory configured to store specific data blocks to be read for a host device and write data to be written to the non-volatile storage medium, a buffer configured to temporarily store write data transmitted from... Agent: Knobbe Martens Olson & Bear LLP

20090193183 - Nonvolatile memory system, and data read/write method for nonvolatile memory system: A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090193180 - Semiconductor memory device and control method for semiconductor memory device: A memory card capable of connecting to a host device includes a flash memory, a host interface unit which transfers data between a host device and the memory card, and a transfer mode control unit which changes a data transfer mode based on a command from the host device. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090193178 - Systems and methods for power management in relation to a wireless storage device: Various embodiments of the present invention provide systems and methods for reducing power consumption in a device including a memory system. As one example, a system may include a memory system with a hard disk drive and a flash memory. The flash memory maintains a menu file that includes a... Agent: Hamilton,desanctis & Cha (lsi)

20090193177 - Virtual processor based security for on-chip memory, and applications thereof: A processor-based method, system and apparatus to comprise a method, system and apparatus to access a memory location in an on-chip memory based on a virtual processing element identification associated with an instruction. The system comprises multiple virtual processing elements, an access list and a comparator coupled to the memory... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090193185 - Method for accessing the physical memory of an operating system: A method for accessing the physical memory with an operating system, providing for mapping the physical address to the linear address of the memory in the operating system. Thus to access the user-space of the memory with an operating system is practically to read and write data in the kernel-space... Agent: Ckc & Partners Co. Lts 12th Fl., Ruttonjee House

20090193187 - Design structure for an embedded dram having multi-use refresh cycles: A design structure for an embedded DRAM (eDRAM) having multi-use refresh cycles is described. In one embodiment, there is a multi-level cache memory system that comprises a pending write queue configured to receive pending prefetch operations from at least one of the levels of cache. A prefetch queue is configured... Agent: Hoffman Warnick LLC

20090193186 - Embedded dram having multi-use refresh cycles: An embedded DRAM (eDRAM) having multi-use refresh cycles is described. In one embodiment, there is a multi-level cache memory system that comprises a pending write queue configured to receive pending prefetch operations from at least one of the levels of cache. A prefetch queue is configured to receive prefetch operations... Agent: Hoffman Warnick LLC

20090193188 - Optimizing execution of i/o requests for a disk drive in a computing system: Methods, apparatus, and products are disclosed for optimizing execution of Input/Output (‘I/O’) requests for a disk drive in a computing system that include: receiving I/O requests specifying disk blocks of the disk drive for access, each disk block specified by a disk drive head, a cylinder, and a sector of... Agent: International Corp (blf)

20090193189 - Block-based storage system having recovery memory to prevent loss of data from volatile write cache: A block-based storage system that maximizes data throughput while minimizing data loss has a non-volatile mass storage media for receiving and non-volatilly storing WRITE data and a volatile write cache for receiving and caching WRITE data until the WRITE data has been written to the non-volatile mass storage media. A... Agent: Panitch Schwarze Belisario & Nadel LLP

20090193190 - Memory card and accessing method and accessing system for the same: In a memory card and accessing method and accessing system for the memory card, the accessing method and accessing system are adapted to data access between a memory card and a machine using a first operation system. The accessing method firstly checks whether the data in the memory card is... Agent: Hdls Patent & Trademark Services

20090193191 - Write and merge methods in memory card systems for reducing the number of page copies: A memory card system and related write method are disclosed. The method includes receiving a write request for a predetermined page; performing a write operation on a first log block that corresponds to a first data block including the page; receiving an update request for the page; and performing a... Agent: Volentine & Whitt PLLC

20090193192 - Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications: Cache coherency latency is reduced through a method and apparatus that expedites the return of line exclusivity to a given processor in a multi-node data handling system through enhanced inter-node communications.... Agent: International Business Machines Corporation Richard Lau

20090193193 - Translation table coherency mecahanism using cache way and set index write buffers: Systems and/or methods are presented that provide for recording transactions that occur during a write process in an organized, self-aggregated manner for the purpose of recovering the transactions in the event of a power loss. By implementing an organization that reflects the cache architecture that is organized according to the... Agent: Turocy & Watson, LLP

20090193194 - Method for expediting return of line exclusivity to a given processor in a symmetric multiprocessing data processing system: A method and apparatus for eliminating, in a multi-nodes data handling system, contention for exclusivity of lines in cache memory through improved management of system buses, processor cross-invalidate stacks, and the system operations that can lead to these requested cache operations being rejected.... Agent: International Business Machines Corporation Richard Lau

20090193195 - Cache that stores data items associated with sticky indicators: Data items are stored in a cache of the storage system, where the data items are for a snapshot volume. Sticky indicators are associated with the data items in the cache, where the sticky indicators delay removal of corresponding data items from the cache. Data items of the cache are... Agent: Hewlett Packard Company

20090193196 - Method and system for cache eviction: The proposed system and associated algorithm when implemented improves the processor cache miss rates and overall cache efficiency in multi-core environments in which multiple CPU's share a single cache structure (as an example). The cache efficiency will be improved by tracking CPU core loading patterns such as miss rate and... Agent: Maxvalueip Consulting LLC

20090193198 - Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetching: A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090193197 - Selective coherency control: A data processing system 2 is provided with a general purpose programmable processor 4 and an accelerator processor 6. Coherency control circuitry 20 manages data coherence between data items which may be stored within a cache memory 16 and/or a further memory 18. Memory access requests from the accelerator processor... Agent: Nixon & Vanderhye, PC

20090193199 - Method for increasing cache directory associativity classes via efficient tag bit reclaimation: In a method of generating a cache directory to include a plurality of associativity classes, each associativity class includes an address tag including a plurality of address bits. Each address tag is configured to store a unique address to a specific location in an memory space. An amount of memory... Agent: Robert R. Williams IBM Corporation, Dept. 917

20090193202 - Multi-column addressing mode memory system including an integrated circuit memory device: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a... Agent: Shemwell Mahamedi LLP

20090193201 - System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency: A memory system is provided that increases the overall bandwidth of a memory channel by operating the memory channel at a independent frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090193200 - System to support a full asynchronous interface within a memory hub device: A memory system is provided that implements an asynchronous boundary in a memory module. The memory system comprises a memory hub device integrated in a memory module. The memory system also comprises a set of memory devices coupled to the memory hub device. The memory hub device comprises a command... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090193204 - System and method of accessing memory within an information handling system: A system and method of accessing memory within an information handling system are disclosed. In one form, a method of accessing memory can include detecting a first operating value of a first memory access node accessible to a first processor, and initiating operation of the first memory access node to... Agent: Larson Newman Abel & Polansky, LLP

20090193203 - System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency: A memory system is provided that reduces latency by running a memory channel fully asynchronous from a memory device frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an external... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090193205 - Data network and a method of regeneration of the recording state of digital data in a data network: A method of regeneration of a recording state of digital data stored in a node of a data network, the method including the steps of classifying files stored in the node, periodically writing a digital file from the node to a temporary memory, the temporary memory being a component of... Agent: Seed Intellectual Property Law Group PLLC

20090193207 - Computer system, remote copy method and first computer: In a computer system of the present invention, the logical volume of a network storage device can be exclusively shared by a plurality of computers. A first computer, upon receiving a remote copy request, writes a remote copy target file to a logical volume inside a shared storage device, and... Agent: Stanley P.fisher Reed Smith LLP

20090193208 - Storage control system: A storage control system is provided where a first host system connected to a first storage controller can issue a control command to a second storage controller connected another host system. The first storage controller is connected to the second storage controller and the command is issued without providing the... Agent: Sughrue Mion, PLLC

20090193206 - Storage system and snapshot configuration migration method: A migration controller 4C creates, inside a migration-destination storage controller 2, a migration-destination volume 7A, a migration-destination snapshot volume 7B and a pool 7C corresponding to a migration-source volume 5A, a migration-source snapshot volume 5B, and a pool 5C, respectively. The migration controller 4C reproduces an update history of a... Agent: Stanley P. Fisher Reed Smith LLP

20090193212 - Fixed length memory block management apparatus and control method thereof: A fixed length memory block management apparatus has a plurality of processors which execute applications, a memory which is shared by the plurality of processors, an application program, an initialization program, and an access right allocation program being stored in the memory. The apparatus has an application execution unit which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090193209 - Method for protecting data in the hard disk: A method for protecting data in the hard disk is provided. The method is suitable for a computer system and includes the following steps. First, a plurality of specification parameters conforming to the computer system is read. Next, a part of the specification parameters are encoded for obtaining a recognition... Agent: J C Patents, Inc.

20090193211 - Software authentication for computer systems: A technique for authenticating software in a computer system is provided that can be used to prevent unauthorized users from accessing or using certain features or resources of the computer system. In accordance with the technique, a relatively small hash table is authenticated at system boot up and then used... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090193210 - System for automatic legal discovery management and data collection: Provided is a system and method for the collection and production of documents in a judicial setting. The disclosed technology provides a rapid, cost-efficient system for document production that requires no local workstation or laptop software installation. Both a web-based solution and a hard drive based solution are provided. Collected... Agent: Greg Goshorn, P.C.

20090193213 - Method and apparatus for data transform: In an apparatus and method of transforming a block of data elements, the order of the data elements is transformed. The data elements are stored in an initial order in respective ones of first and second memory elements, each first memory element corresponding to a respective second memory element. The... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20090193214 - Dynamic address translation with frame management: What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained containing an opcode for a frame management instruction identifying a first and second general register. Clear frame information is obtained from the first general register... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090193215 - Erasing and restoring factory settings in computer systems: In one embodiment, a computer system comprising a system restoration control module within which resides a erasure module. In one embodiment, the computer system allows a user to erase personally identified information from a computer system without concern that the information will be subsequently retrieved and restore the computer system... Agent: Hewlett Packard Company

20090193216 - Method and apparatus for hardware enforced virtual sequentiality: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing engine and a memory system such that write data is buffered and information based upon reads and writes is recorded.... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20090193217 - Occupancy analysis: The disclosed embodiments relate to transparent and/or non-disruptive systems and methods for monitoring and analyzing actual space utilization, and in particular, analyzing space utilization over time and/or in real time to accurately understand and report the utilization of the space. In particular, the disclosed embodiments analyze data representative of occupancy... Agent: Brinks Hofer Gilson & Lione

20090193218 - Storage apparatus and data writing method: A storage apparatus includes: a management unit for managing mapping, to a logical volume, of a second dynamically allocated storage area volume in an external storage apparatus, and also managing a management unit for a storage area in the second dynamically allocated storage area volume for storing data sent from... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090193219 - Storage subsystem: There is provided a storage subsystem having a virtual volume and a page volume which has a page physical area allocated to the virtual volume. The storage subsystem divides an address space of the virtual volume into a plurality of pages, classifies each of the pages into one of a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090193220 - Memory management device applied to shared-memory multiprocessor: A plurality of processors are capable of parallel operation. A memory is shared by the plurality of processors. The memory has an allocated memory size indicating the size of an area allocated to an allocatable area in the memory at the request of one of the plurality of processors and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090193221 - Method and apparatus for memory management in a non-volatile memory system using a block table: An invention is provided for memory management in a non-volatile memory which includes a plurality of memory blocks. The invention includes loading a block table from a memory block of the non-volatile memory into system memory, where the block table includes, inter alia, a plurality of entries mapping a physical... Agent: Patent Venture Group

20090193222 - Maintaining processor resources during architectural events: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In... Agent: Trop, Pruner & Hu, P.C.

20090193223 - Methods and systems for vectored data de-duplication: The present invention is directed toward methods and systems for data de-duplication. More particularly, in various embodiments, the present invention provides systems and methods for data de-duplication that may utilize a vectoring method for data de-duplication wherein a stream of data is divided into “data sets” or blocks. For each... Agent: Sheppard, Mullin, Richter & Hampton LLP

20090193224 - Techniques for reducing storage space and detecting corruption in hash-based application: Techniques for reducing storage space and detecting corruption in hash-based applications are presented. Data strings are hashed or transformed into numerically represented strings. Groupings of the numeric strings form a set. Each numeric string of a particular set is associated with a unique co-prime number. All the numeric strings and... Agent: Schwegman, Lundberg & Woessner/novell

20090187695 - Handling concurrent address translation cache misses and hits under those misses while maintaining command order: Apparatus handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit... Agent: Ibm Corporation RochesterIPLaw Dept 917

20090187696 - Method for data storage means and a system with data storage means: A system and a method for data storage means includes a set of data storage sub-assemblies and connectable to storage control means adapted to retrieve, for a plurality of simultaneous user applications, data stored in the data storage means. The method divides a data composition into a plurality of payload... Agent: Drinker Biddle & Reath (dc)

20090187697 - Execute-only memory and mechanism enabling execution from execute-only memory for minivisor: In one embodiment, a processor comprises an execution core configured to execute instructions; and a register configured to store an execute-only valid indication indicative of whether or not execution of instructions is permitted in pages that are indicated as execute-only in a set of page tables used by the processor... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090187698 - Minivisor entry point in virtual machine monitor address space: In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access,... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090187699 - Non-volatile memory storage system and method for reading an expansion read only memory image thereof: A non-volatile memory storage system including a connecting interface, a non-volatile memory, a buffer memory, a microcontroller, and a virtual host module is provided. The connecting interface is used for connecting to a host. The non-volatile memory is used for storing user data, wherein the non-volatile memory further stores an... Agent: J C Patents, Inc.

20090187703 - Memory card and its initial setting method: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is... Agent: Miles & Stockbridge PC

20090187701 - Nand flash memory access with relaxed timing constraints: Timing constraints on data transfers during access of a NAND flash memory can be relaxed by providing a plurality of data paths that couple the NAND flash memory to a buffer that provides external access to the memory. The buffer defines a bit width associated with the external access, and... Agent: Daniel A. Hammond Mosaid Technologies Incorporated

20090187702 - Nonvolatile memory: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address... Agent: Miles & Stockbridge PC

20090187700 - Retargeting of a write operation retry in the event of a write operation failure: Methods and systems are herein disclosed for write operation retry using the data stored and retained in an internal buffer within the non-volatile memory device. By using the data stored in the internal buffer, the systems and method of the present invention eliminate the need to include a dedicated retry... Agent: Turocy & Watson, LLP

20090187704 - Method and system for secure code encryption for pc-slave devices: A PC-slave device may securely load and decrypt an execution code and/or data, which may be stored, encrypted, in a PC hard-drive. The PC-slave device may utilize a dedicated memory, which may be partitioned into an accessible region and a restricted region that may only be accessible by the PC-slave... Agent: Mcandrews Held & Malloy, Ltd

20090187705 - Fair and dynamic disk input/output bandwidth distribution: Embodiments that facilitate the fair and dynamic distribution of disk input/output (IO) bandwidth are disclosed. In accordance with one embodiment, the method includes organizing one or more disk IO time intervals into one or more queues. The method further includes allocating a disk IO time interval to each queue. The... Agent: Lee & Hayes, PLLC

20090187706 - Input/output control unit, disk array apparatus, input/output control method, and program: An input/output controller, including: a first/a second input/output units that sends and receives data to and from a first and a second external apparatus, a third input/output unit operating in one of a plurality of working modes including a first/a second working mode for sending and receiving data to and... Agent: Nec Corporation Of America

20090187708 - Program, method, and device for communication processing: A path controller controls a plurality of paths, including switching between those paths in response to an error notice. Upon detection of a path connection timeout at the path controller, a target driver submits an I/O abort request to a disk array device. The target driver also forwards an error... Agent: Greer, Burns & Crain

20090187707 - System and method of maximization of storage capacity in a configuration limited system: A method, system and computer-usable medium are disclosed for providing management of serial attached small computer system interface (SAS) storage devices. A host computer comprises a storage controller connected to a SAS port expander comprising a plurality of ports that are logically assigned to target storage devices. The device ports... Agent: Hamilton & Terrile, LLP IBM Tucson

20090187710 - Apparatus and methods of using card based programmable controllers: The present invention is generally directed to an apparatus and a method for controlling an environment control system. In one aspect, a programmable controller for operating an environmental control system is provided. The programmable controller includes a body and a controller member. The programmable controller also includes a sensor member... Agent: Patterson & Sheridan, L.L.P.

20090187709 - Method, system and controller for transmitting and dispatching data stream: A method for transmitting and dispatching data stream, which is used for transmitting data stream to a storage device having a non-volatile memory and a smart card chip from a host, is provided. The method includes: setting a key between the host and the storage device; creating a temporary file... Agent: J C Patents, Inc.

20090187711 - System and method for performing auxiliary storage operations: Systems and methods for protecting data in a tiered storage system are provided. The storage system comprises a management server, a media management component connected to the management server, a plurality of storage media connected to the media management component, and a data source connected to the media management component.... Agent: Knobbe Martens Olson & Bear LLP

20090187712 - Operation frame filtering, building, and execution: The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead of operations identified by the frame signature.... Agent: Schwegman, Lundberg & Woessner, P.A.

20090187713 - Utilizing cache information to manage memory access and cache utilization: A method and system of managing data access in a shared memory cache of a processor are disclosed. The method includes probing one or more memory addresses that map to a subset of the shared memory cache and sensing a plurality of events in the one or more memory addresses.... Agent: Vmware, Inc.

20090187714 - Memory hub and access method having internal prefetch buffers: A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20090187715 - Prefetch termination at powered down memory bank boundary in shared memory controller: A prefetch scheme in a shared memory multiprocessor disables the prefetch when an address falls within a powered down memory bank. A register stores a bit corresponding to each independently powered memory bank to determine whether that memory bank is prefetchable. When a memory bank is powered down, all bits... Agent: Texas Instruments Incorporated

20090187717 - Apparatus, circuit and method of controlling memory initialization: An apparatus includes a first memory which includes a plurality of memory regions, a second memory which stores initializing information indicating whether each of the memory regions is initialized, the second memory controlling a coherency between the first memory and a cache memory, and a control circuit which initializes a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090187716 - Network on chip that maintains cache coherency with invalidate commands: A network on chip (‘NOC’) that maintains cache coherency, the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, at least one memory communications controller further comprising a... Agent: Ibm (roc-blf)

20090187718 - Information processing system and information processing method: An ascending ordered list without duplication is generated based on a value list divided and held by multiple memory modules. An information processing system has multiple PMMs, and the PMMs are interconnected via a data transmission path. The memory in the PMM has a list of values, which are ordered... Agent: Griffin & Szipl, PC

20090187720 - Automatic backup method and computer system with automatic backup function: An automatic backup method to deal with at least a backup data is provided. First, offering a data-sync program and a wireless transmission module driven by the data-sync program; transmitting a first data stream to a first storage unit as a first file; transmitting the first file to a second... Agent: Jianq Chyun Intellectual Property Office

20090187722 - Computer system storing data on multiple storage systems: During the normal operation state of a computer system 1000, the data stored in a primary storage system 200P is copied to an intermediate storage system 200I via synchronous copying and the data stored in the intermediate storage system 200I is copied to a secondary storage system 200R via asynchronous... Agent: Townsend And Townsend And Crew, LLP

20090187721 - Computer system, management computer, and volume allocation change method of management computer: A computer system to prevent intervention and falsification by setting encrypted transfer between a host computer and a first storage device that provides a virtual volume and between the first storage device and second and third storage devices that provide a real volume corresponding to the virtual volume. A management... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090187719 - Data backup method for logical volume manager: A data backup method for logical volume manager (LVM) is used for backup the original data in the LV when adding newly data into a logical volume of the LVM. Before adding a snapshot volume, a new storage space is created. The LVM writes the data to be altered in... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090187723 - Secure storage system and method for secure storing: According to an exemplary embodiment a method for securely storing a message comprises dividing a first message into a first plurality of shares, and storing the first plurality of shares on a storing host together with a second plurality of shares of at least a second message, wherein the storing... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090187724 - Dynamic address translation with frame management: What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090187725 - Method and data processing system for generating and applying patches to a computer program code concurrently with its execution: A method and data processing system are disclosed for concurrently loading a plurality of new modules while code of a plurality of modules of an original (i.e., currently running) computer program is loaded and executed on a computer system. The method may comprise allocating a module TLS block for each... Agent: Ibm Corporation

20090187726 - Alternate address space to permit virtual machine monitor access to guest virtual address space: In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access,... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090187727 - Index generation for cache memories: Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090187728 - Dynamic address translation with change recording override: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. A segment table entry obtained from a segment table contains a format control field.... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090187729 - Separate page table base address for minivisor: In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access,... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090187730 - Mainframe storage controller and mainframe volume virtualization method: A storage controller of the present invention is capable of providing a plurality of external volumes to a mainframe as a single virtual volume without lowering write performance. A virtual volume inside a main storage apparatus is associated with a plurality of external volumes inside an external storage apparatus. When... Agent: Mattingly & Malur, P.C.

20090187731 - Method for address translation in virtual machines: The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit... Agent: International Business Machines Corporation Richard Lau

20090187732 - Dynamic address translation with dat protection: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained. Based on the obtained... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090182927 - Direct memory move of multiple buffers between logical partitions: A method, apparatus and program product are provided for moving data from a source memory zone to a target memory zone of a computer. A source host operating system invokes a synchronous multiple move command for SBAL output buffers with a common target zone. The machine firmware identifies and validates... Agent: Steven E. Bach Attorney At Law

20090182929 - Method and apparatus for storing and restoring state of virtual machine: Provided is a method and apparatus for storing and restoring a state of a virtual machine on a virtual machine monitor. The method of storing a state of a second virtual machine in a predetermined storage device by a first virtual machine on a virtual machine monitor includes determining whether... Agent: Sughrue Mion, PLLC

20090182928 - Method and system for tracking a virtual machine: A method and system provide tracking of a virtual machine by compiling information on the virtual machines in a network and sending the information to an administrative console. The administrative console can then determine the status of the virtual machines in the network. The administrative console can also establish a... Agent: Sonnenschein Nath & Rosenthal LLP

20090182930 - Data management method for erasing data in computer system: There is provided a computer system comprising a first storage system and a second storage system coupled to the first storage system. The first storage system provides a first storage area. The second storage system provides a second storage area. The second storage system reads and writes the requested data... Agent: Mattingly & Malur, P.C.

20090182933 - Durable data storage system and method: A method of operating a storage system, comprising: issuing a first command to write a first data to a first nonvolatile storage device; writing the first data to a second nonvolatile storage device if write condition is unstable; retrieving the first data from the second nonvolatile storage device; and writing... Agent: F. Chau & Associates, LLC

20090182935 - Mass storage device, in particular of the usb type, and related method for transferring data: A mass storage device of the present invention includes one or more memory elements and a logic module adapted to interface the one or more memory elements for exchanging data according to a data exchange protocol, in particular of the USB type, through a first port. The mass storage device... Agent: Egbert Law Offices

20090182934 - Memory device and method of multi-bit programming: Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of... Agent: Harness, Dickey & Pierce, P.L.C

20090182932 - Method for managing flash memory blocks and controller using the same: A method for managing blocks is provided. In the method, a plurality of flash memories is divided into a plurality of block program units, and blocks mapped to each of the block program units are recorded, wherein each of the block program units maps to at least two blocks. Next,... Agent: J C Patents, Inc.

20090182937 - Semiconductor memory card, and program for controlling the same: A semiconductor memory card that has a sufficient storage capacity when an EC application writes data to a storage is provided. A usage area for the EC application in an EEPROM 3 in a TRM 1 is expanded. The expansion is such that a partition generated in a flash memory... Agent: Wenderoth, Lind & Ponack L.L.P.

20090182936 - Semiconductor memory device and wear leveling method: Disclosed is a semiconductor memory device and wear leveling method thereof. The semiconductor memory device including: a nonvolatile memory having pluralities of memory blocks, at least one of the memory blocks storing erasing counts of the memory blocks; and a memory controller managing wear leveling of the nonvolatile memory. The... Agent: Volentine & Whitt PLLC

20090182931 - System including a portable storage device equipped with a user proximity detector and method of preventing the loss thereof: A portable storage system. The portable storage system comprises a portable storage device having a flash memory element and a loss-prevention unit. The portable storage system further comprises Master and Slave proximity elements. One of the proximity elements is physically connected with the portable storage device, while the other is... Agent: Martin D. Moynihan D/b/a Prtsi, Inc.

20090182938 - Content addressable memory augmented memory: Embodiments of the present disclosure provide methods, apparatuses, and systems including a memory device including content addressable memory configured to store an address associated with one or more memory cells while an access operation is performed on the one or more memory cells. Other embodiments may be described.... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20090182939 - Asynchronous and distributed storage of data: In one example, multimedia content is requested from a plurality of storage modules. Each storage module retrieves the requested parts, which are typically stored on a plurality of storage devices at each storage module. Each storage module determines independently when to retrieve the requested parts of the data file from... Agent: Proskauer Rose LLP

20090182940 - Storage control system and control method: A storage control system in which a first storage controller is connected to a storage device in a second storage controller and the first storage controller is configured to be able to read and write data from/to the storage device in the second storage controller in response to a request... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090182941 - Web server cache pre-fetching: A method and apparatus for a server that includes a file processor that interprets each requested data file, such as a web page, requested by a client in a process analogous to that of a browser application or other requesting application. The file processor initiates the loading of each referenced... Agent: Red Hat/bstz Blakely Sokoloff Taylor & Zafman LLP

20090182943 - Data processor: The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a... Agent: Miles & Stockbridge PC

20090182942 - Extract cache attribute facility and instruction therefore: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.... Agent: International Business Machines Corporation Richard Lau

20090182945 - Clustered cache appliance system and methodology: A method, system and program are disclosed for accelerating data storage by providing non-disruptive storage caching using clustered cache appliances with packet inspection intelligence. A cache appliance cluster that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files using dynamically adjustable cache policies provides low-latency... Agent: Hamilton & Terrile, LLP

20090182944 - Processing unit incorporating l1 cache bypass: A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20090182946 - Method and system for employing a multiple layer cache mechanism to enhance performance of a multi-user information retrieval system: A method and system for optimizing resource usage in an information retrieval system. Meta information in query results describes data items identified by identifiers. A chunk of the identifiers and a set of meta information are loaded into a first cache and a second cache, respectively. A portion of the... Agent: Schmeiser, Olsen & Watts

20090182947 - Method of tuning a cache: Embodiments of the present invention provide methods and systems for tuning the size of the cache. In particular, when a page fault occurs, non-resident page data is checked to determine if that page was previously accessed. If the page is found in the non-resident page data, an inter-reference distance for... Agent: Mh2 Technology Law Group (cust. No. W/red Hat)

20090182949 - Cache eviction: A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and... Agent: Nixon & Vanderhye, PC

20090182948 - Caching method and apparatus for a vertex shader and geometry shader: Systems and methods for sharing a physical cache among one or more clients in a stream data processing pipeline are described. One embodiment, among others, is directed to a system for sharing caches between two or more clients. The system comprises a physical cache memory having a memory portion accessed... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090182950 - Method for tuning a cache: Embodiments of the present invention provide methods and systems for tuning the size of the cache. In particular, when a page fault occurs, non-resident page data is checked to determine if that page was previously accessed. If the page is found in the non-resident page data, an inter-reference distance for... Agent: Mh2 Technology Law Group (cust. No. W/red Hat)

20090182951 - Cache line replacement techniques allowing choice of lfu or mfu cache line replacement: Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based... Agent: Ryan, Mason & Lewis, LLP

20090182952 - Cache using pseudo least recently used (plru) cache replacement with locking: A cache stores information in each of a plurality of cache lines. Addressing circuitry receives memory addresses for comparison with multiple ways of stored addresses to determine a hit condition representing a match of a stored address and a received address. A pseudo least recently used (PLRU) tree circuit stores... Agent: Freescale Semiconductor, Inc. Law Department

20090182953 - Method and apparatus for network packet capture distributed storage system: This is invention comprises a method and apparatus for Infinite Network Packet Capture System (INPCS). The INPCS is a high performance data capture recorder capable of capturing and archiving all network traffic present on a single network or multiple networks. This device can be attached to Ethernet networks via copper... Agent: Intellevate

20090182955 - Application configuration across client devices of a local system: A method and a system to application configuration across client devices of a local system are disclosed. An exemplary embodiment provides a method for sharing of an application configuration data across client devices. A local storage device of a local system is updated to comprise an application from a remote... Agent: Intellevate

20090182954 - Network on chip that maintains cache coherency with invalidation messages: A network on chip (‘NOC’), and methods of operation of a NOC, that maintains cache coherency with invalidation messages, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface... Agent: Ibm (roc-blf)

20090182956 - Method and apparatus for improving transactional memory commit latency: Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a store buffer. In addition, the system sets a stores_encountered indicator when... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090182958 - Data access method and data access device: A recording medium has a real data area built from a plurality of clusters and a fat (File Allocation Table) built from a plurality of entries showing usage conditions of the corresponding clusters. A control unit previously divides the fat into a plurality of blocks and creates, in RAM, a... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20090182957 - Data storage apparatus: A storage apparatus includes: storage modules for storing data, each of the data including meta data for identifying an attribute of the data, each of the storage modules having a characteristic different from one another; a memory for storing information of the characteristic of each of the storage modules; and... Agent: Staas & Halsey LLP

20090182959 - Optimizing reclamation of data space: An amount of storage to reclaim is determined based at least in part on a write size of new previous version data written most recently to a data region. The determined amount of storage is reclaimed.... Agent: Van Pelt, Yi & James LLP And Emc Corporation

20090182962 - Memory subsystem hibernation: In a managed memory subsystem, information associated with the memory subsystem is copied from volatile memory in the memory subsystem to host system memory. The copying can be over a standard interface. Responsive to memory subsystem power up from a powered down state or power loss, the information is copied... Agent: Fish & Richardson P.C.

20090182961 - Methods, apparatuses, and computer program products for protecting pre-staged provisioned data in a storage system: A method, apparatus, and computer program product for protecting pre-staged provisioned data in a storage system are provided. The method includes identifying a storage area in the storage system for access control. The method also includes assigning a switching criterion to modify allowable access to the identified storage area, where... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090182963 - System and method for performing a snapshot and for restoring data: The present invention relates to a method for tracking a plurality of snapshots of an information store. The present invention comprises performing a first snapshot of an information store that indexes the contents of the information store, copying the contents of the information store to a first storage device, using... Agent: Perkins Coie LLP Patent-sea

20090182960 - Using multiple sidefiles to buffer writes to primary storage volumes to transfer to corresponding secondary storage volumes in a mirror relationship: Provided are an article of manufacture, method, and system for using multiple sidefiles to buffer writes to primary storage volumes to transfer to corresponding secondary storage volumes in a mirror relationship. Information is provided on a mirror relationship for primary storage volumes and corresponding secondary storage volumes, wherein writes to... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20090182964 - Dynamic address translation with format control: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090182965 - Securing data in memory device: The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension... Agent: Unity Semiconductor Corporation

20090182966 - Dynamic address translation with frame management: What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090182967 - Packet transfer in a virtual partitioned environment: A computer implemented method, computer product code, and data processing system are provided for transferring data between virtual partitions. A request is received to transfer a packet from a first partition to a second partition. A free buffer is identified from a buffer pool of the second partition, and a... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090182968 - Validity of address ranges used in semi-synchronous memory copy operations: A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090182969 - Dynamic allocation of dma buffers in input/output adaptors: A method and apparatus for dynamic allocation of DMA buffers in the DRAM banks of an I/O adaptor. The method and apparatus determine the functional status of the adaptor, allocate critical, volatile DMA buffers in non-critical DRAM banks if the adaptor is fully functional, and allocate critical, volatile DMA buffers... Agent: Ibm Corporation

20090182970 - Data transmission for partition migration: A method, apparatus, and program product manage data during a logical partition migration. Data from a source logical partition is transformed into partition state records by a source migration services partition. The records are transmitted to a target migration services partition that processes the records and loads the data into... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20090182971 - Dynamic address translation with fetch protection: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090182972 - Dynamic address translation with format control: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090182973 - Dynamic address translation with load real address: What is provided is a load real address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction containing an opcode is obtained indicating that a load real address is to be performed. The instruction further identifies a first general register. Based on the... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090182974 - Dynamic address translation with access control: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090182975 - Dynamic address translation with load page table entry address: What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090182976 - Large-page optimization in virtual memory paging systems: A computer system that is programmed with virtual memory accesses to physical memory employs multi-bit counters associated with its page table entries. When a page walker visits a page table entry, the multi-bit counter associated with that page table entry is incremented by one. The computer operating system uses the... Agent: Vmware, Inc.

20090182977 - Cascaded memory arrangement: Embodiments of the present disclosure provide methods, apparatuses, and systems including a memory arrangement including a first memory, and a second memory operatively coupled to the first memory to serve as an external interface of the memory arrangement to one or more components external to the memory arrangement to access... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20090177833 - Buffering systems methods for accessing multiple layers of memory in integrated circuits: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to... Agent: Unity Semiconductor Corporation

20090177835 - Flash drive with spring-loaded retractable connector: A pen-type computer peripheral device includes an elongated housing containing a PCBA having a plug connector. The PCBA is secured to a positioning member that is actuated by way of a press-push button that is exposed through a slot defined in a wall of the housing. A spring-loaded mechanism includes... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way

20090177834 - Method for managing data intended to be written to and read from a memory: p

20090177836 - Methods and apparatuses for managing data in a computer storage system: Data stored on disk drives in a storage system is automatically migrated to tape after a first predetermined time period according to a migration policy specified for the data. When the data stored to tape is to be accessed and has been deleted from the disk drives, the data is... Agent: Mattingly & Malur, P.C.

20090177837 - Methods and apparatus for managing hdd's spin-down and spin-up in tiered storage systems: A storage system is configured as tiered storage (composed of top tier storage apparatuses and second tier storage apparatus at least). The top tire storage apparatus gathers the volume-to-volume map information and power boundary information from second tier storage apparatuses, which are connected to the top tier storage apparatus. The... Agent: Sughrue Mion, PLLC

20090177838 - Apparatus and method to access data in a raid array: A method to access a data in a RAID array comprising a plurality of data storage media, wherein information is written to said plurality of data storage media using a RAID configuration, wherein the method receives from a requester a command comprising a data access priority indicator. If a RAID... Agent: Dale F. Regelman Quarles & Brady, LLP

20090177839 - Method for analyzing performance information: A performance information display method using a computer, includes the steps, in the computer, of reading out information data of a storage device previously stored in a storage device and information data of a plurality of devices utilizing the storage device, displaying an identifier of the storage device and identifiers... Agent: Mattingly & Malur, P.C.

20090177840 - System and method for servicing inquiry commands about target devices in storage area network: Inquiry data received from sequential target devices is stored in a cache memory. In one embodiment, the cache memory is coupled to a router. In one embodiment, when the router receives from a host an inquiry command about a target, the router first checks to see if the inquiry command... Agent: SprinkleIPLaw Group

20090177841 - Methods and systems for consistently replicating data: Techniques for maintaining consistent replicas of data are disclosed. By way of example, a method for managing copies of objects within caches, in a system including multiple caches, includes the following steps. Consistent copies of objects are maintained within the caches. A home cache for each object is maintained, wherein... Agent: Ryan, Mason & Lewis, LLP

20090177842 - Data processing system and method for prefetching data and/or instructions: A data processing system for processing at least one application is provided. The data processing system comprises a processor (100) for executing the application. The system furthermore comprises a cache memory (200) being associated to the processor (100) for caching data and/or instructions for the processor (100). The system furthermore... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090177843 - Microprocessor architecture having alternative memory access paths: The present invention is directed to a system and method which employ two memory access paths: 1) a cache-access path in which block data is fetched from main memory for loading to a cache, and 2) a direct-access path in which individually-addressed data is fetched from main memory. The system... Agent: Fulbright & Jaworski L.l.p

20090177844 - Method of efficiently choosing a cache entry for castout: The present invention relates generally to a method and system for efficiently identifying a cache entry for cast out in relation to scanning a predetermined sampling subset of pseudo-randomly sampled cached entries and determining a least recently used (LRU) entry from the scanned cached entries subset, thereby avoiding a comprehensive... Agent: Ibm St-svl Sawyer Law Group LLP

20090177846 - Retry mechanism: An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first... Agent: Lawrence J. Merkel Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20090177845 - Snoop request management in a data processing system: Snoop requests are managed in a data processing system having a cache coupled to a processor that provides access addresses to the cache. Snoop queue circuitry provides snoop addresses to the cache via an arbiter. The snoop queue circuitry has a snoop request queue for storing a plurality of entries.... Agent: Freescale Semiconductor, Inc. Law Department

20090177847 - System and method for handling overflow in hardware transactional memory with locks: A system, method and computer program product for processing overflow transactions in a transactional memory system. The transactional memory system is provided in a multiprocessing system having one or more processor devices and a shared memory storage system, and implements a best effort hardware transactional memory system. The method includes... Agent: Scully, Scott, Murphy & Presser, P.C.

20090177848 - Methods and systems for classifying storage systems using fixed static-ip addresses: A storage system for exchanging data with a host system, the storage system including a plurality of storage devices, each of the storage devices including: a non-volatile memory, wherein a fixed static-IP address resides in the non-volatile memory, the fixed static-IP address being common to two or more of the... Agent: Mark M. Friedman

20090177849 - System and methods for memory expansion: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the... Agent: Schwegman, Lundberg & Woessner, P.A.

20090177850 - Apparatus, system, and method for a read-before-write storage controller instruction: An apparatus, system, and method are disclosed for a read-before-write storage controller instruction. A sequencer receives an atomic read-before-write instruction comprising new data, a target address for the new data, and an undo log address. An I/O unit reads old data from the target address, writes the old data and... Agent: Kunzler & Mckenzie

20090177851 - Memory device and data reading method: A memory device is provided. The memory device includes a memory array formed by a plurality of multi level cells, a determining circuit and a data reading circuit. The memory array includes a plurality of page units, each including a main data and an auxiliary data corresponding to the main... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090177852 - Data block receiver and method for decoding data block: A data block receiver for decoding a data block. The data block has a block sequence number (BSN). The data block receiver includes two de-interleavers, a memory circuitry, a combiner, a decoder, and an error detector. A first de-interleaver interleaves the data block to obtain a first de-interleaved data block.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090177853 - System and methods for memory expansion: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the... Agent: Schwegman, Lundberg & Woessner, P.A.

20090177854 - Methods, systems, and computer program products for preemptive page eviction: A method, system, and computer program product for preemptive page eviction in a computer system are provided. The method includes identifying a region in an input file for preemptive page eviction, where the identified region is infrequently accessed relative to other regions of the input file. The method also includes... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090177857 - Apparatus and method for managing data storage: An apparatus for controlling a log-structured data storage system, operable with a first log-structured data storage area for storing data, comprises a metadata storage component for controlling the first log-structured data storage area and comprising a second log-structured data storage area for storing metadata; and means for nesting the second... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20090177855 - Backing up a de-duplicated computer file-system of a computer system: The present invention provides a method and system of backing up a de-duplicated computer file-system of a computer system. In an exemplary embodiment, the method and system include (1) dividing the file-system into partitions and (2) storing each of the partitions on a separate storage medium.... Agent: Leonard T. Guzman IBM Corp., Law Dept., C4ta/j2b

20090177856 - Method and apparatus for automated backup process: A computer implemented method, apparatus, and computer usable program code for backing up data. In response to a request to backup the data from a data processing system, a unique identifier is identified for the data processing system. Also responsive to the request, the data is backed up to a... Agent: Duke W. Yee

20090177858 - Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system: An information handling system includes a processor with an array power management controller. The array power management controller gates off a memory array, such as a cache, to conserve power whenever a group of instructions in a branch instruction queue together as a group exhibits a confidence in the accuracy... Agent: Mark P. Kahler

20090177859 - Method, system, and program for write process management: Provided are a method, system, and program for managing write processes in which a list of destination location identifiers for pending write operations is maintained in an array having an array pointer which identifies the next available entry of the array. In one embodiment, the array includes a stack of... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20090177860 - Data management method for network storage system and the network storage system built thereof: A data management method for network storage system that said network storage system includes a storage network, a cluster of storage servers that provide data storage services for application servers connecting to the storage network and storage space corresponding to each storage server, setting a core manager in storage server,... Agent: Michael N. Lau Lau & Associates, LLC

20090177861 - System and methods for memory expansion: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The... Agent: Schwegman, Lundberg & Woessner, P.A.

20090172243 - Providing metadata in a translation lookaside buffer (tlb): In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes... Agent: Trop, Pruner & Hu, P.C.

20090172244 - Hierarchical secondary raid stripe mapping: Methods and apparatus of the present invention include new data and parity mapping for a two-level or hierarchical secondary RAID architecture. The hierarchical secondary RAID architecture achieves a reduced mean time to data loss compared with a single-level RAID architecture. The new data and parity mapping technique provides load-balancing between... Agent: Patterson & Sheridan, L.L.P.

20090172245 - Delivering secured media using a portable memory device: In some embodiments an interface of a portable memory device is used to store content information in a hidden memory region of the portable memory device. The interface is also used to store information in a visible memory region of the portable memory device. The information stored in the visible... Agent: Intel Corporation C/o Cpa Global

20090172247 - Controller for one type of nand flash memory for emulating another type of nand flash memory: A controller for one type of NAND flash memory device that emulates another type of NAND flash memory device. The controller may include a host NAND interface to receive host data from a NAND host device, and a data aggregator for aggregating the host data with complementary data, to thereby... Agent: Mark M. Friedman

20090172256 - Data writing method for flash memory, and flash memory controller and storage device thereof: A data writing method for a block of a multi level cell NAND flash memory including upper page addresses and lower page addresses is provided, wherein a writing speed at the lower page addresses is higher than that at the upper page addresses. The data writing method includes receiving a... Agent: J C Patents, Inc.

20090172246 - Device and method for managing initialization thereof: A host may initialize itself faster by enabling an associated storage device to respond to host access commands under specified conditions before the storage device has completed its own initialization. Embodiments of the invention include a storage device, a controller, a method of servicing commands, and a method of using... Agent: Mark M. Friedman

20090172249 - Dynamically adjusting cache policy based on device load in a mass storage system: A dynamic cache policy manager for a mass memory may be used to decide whether a data request is to be routed to the cache or directly to the mass memory, based on estimated delays in processing the request. The choice may be based, at least partially, on the size... Agent: Intel Corporation C/o Cpa Global

20090172260 - Flash memory controller and system including data pipelines incorporating multiple buffers: A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is moved between the storage module and one or more hosts.... Agent: Haynes And Boone, LLPIPSection

20090172258 - Flash memory controller garbage collection operations performed independently in multiple flash memory groups: A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold.... Agent: Haynes And Boone, LLPIPSection

20090172265 - Flash memory device having secure file deletion function and method for securely deleting flash file: Disclosed is a flash memory device having a secure flash file deletion function and a method for securely deleting a flash file. Data and object headers as actual contents of the flash file are separately stored in data blocks and header blocks. At this time, the data is encrypted and... Agent: Ampacc Law Group

20090172263 - Flash storage controller execute loop: In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required... Agent: Haynes And Boone, LLPIPSection

20090172248 - Management of a flash memory device: Methods, computing devices and machine readable medium to manage sector based file system accesses to block erasable flash memory devices are disclosed. One disclosed method includes allocating erasable blocks of a flash memory device to a volume and formatting the volume of a flash memory device with a file system... Agent: Barnes & Thornburg, LLP

20090172259 - Mass storage controller volatile memory containing metadata related to flash memory storage: A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage, including a table storing physical flash memory addresses and a plurality of tables containing metadata.... Agent: Haynes And Boone, LLPIPSection

20090172252 - Memory device and method for performing a write-abort-safe firmware update: A memory device and method for performing a write-abort-safe firmware update are disclosed. In one embodiment, a location in a memory of a memory device for a firmware update is allocated. The firmware update is written into the allocated location in the memory. A pointer is written to the firmware... Agent: Brinks Hofer Gilson & Lione/sandisk

20090172251 - Memory sanitization: Apparatus and method for memory sanitization is disclosed, including a memory, the memory including—in whole or in part—multiple layers of memory, and control logic configured to perform a sanitize operation on a portion of the memory. In one example, a third dimensional memory array can constitute at least a portion... Agent: Unity Semiconductor Corporation

20090172266 - Memory system: A memory system includes a NAND flash memory including a memory block containing a plurality of pages, and a controller which controls write of data to the flash memory, and includes a scrambling circuit which converts the data into a pseudo random number, wherein the scrambling circuit includes an initial... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090172262 - Metadata rebuild in a flash memory controller following a loss of power: A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area is valid.... Agent: Haynes And Boone, LLPIPSection

20090172254 - Method for preventing read-disturb happened in non-volatile memory and controller thereof: A method for preventing read-disturb happened in non-volatile memory and a controller thereof are disclosed. The non-volatile memory includes a plurality of blocks, and the blocks are grouped into at least a data group and a spare group, each block includes a plurality of pages. The method includes recording read... Agent: J C Patents, Inc.

20090172268 - Method for securing a microprocessor, corresponding computer program and device: A method is provided for securing a microprocessor containing at least one main program, which operates with at least one memory. The method includes implementing counter-measures, during which additional operations, that are not required for the main program, are implemented so as to modify the consumption of current and/or the... Agent: Westman Champlin & Kelly, P.A.

20090172253 - Methods and apparatuses for nonvolatile memory wear leveling: Apparatuses, systems, and computer program products that enable wear leveling of nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments an apparatus that has a receiver and a wear leveling module. The receiver may receive low-level write requests to update direct-mapped values of nonvolatile memory.... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Cpa Global

20090172261 - Multiprocessor storage controller: A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host... Agent: Haynes And Boone, LLPIPSection

20090172269 - Nonvolatile memory device and associated data merge method: A memory system is disclosed with a nonvolatile memory adapted to store a file system containing file system information, and a controller adapted to read the file system information and perform a merge operation.... Agent: Volentine & Whitt PLLC

20090172267 - Refresh method of a flash memory: A flash memory device includes a flash memory that stores many physical data blocks, a refresh management table that stores indications of the number of times each individual physical data block has been read, and a controller responsive to read and erase control signals from a source external to the... Agent: Lowe Hauptman Ham & Berner, LLP

20090172250 - Relocating data in a memory device: Systems and methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be... Agent: Turocy & Watson, LLP

20090172257 - System and method for performing host initiated mass storage commands using a hierarchy of data structures: Disclosed is a mass storage system and method for breaking a host command into a hierarchy of data structures. Different types of data structures are designed to handle different phases of tasks required by the host command, and multiple data structures may be used to handle portions of the host... Agent: Haynes And Boone, LLPIPSection

20090172264 - System and method of integrating data accessing commands: A data accessing command integration method includes the following steps. Firstly, M data accessing commands are sequentially received through a bus, wherein N data accessing commands contained in the M data accessing commands have the same command type and comply with a sequential address relationship. Next, the N data accessing... Agent: Kirton And Mcconkie

20090172255 - Wear leveling method and controller using the same: A wear leveling method for a multi level cell (MLC) NAND flash memory is provided. The flash memory includes a first zone and a second zone respectively having a plurality of blocks, wherein each of the blocks includes an upper page and a lower page. The wear leveling method includes:... Agent: J C Patents, Inc.

20090172270 - Device, system, and method of memory allocation: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks;... Agent: Shiloh Et Al.

20090172271 - System and method for executing full and partial writes to dram in a dimm configuration: In an embodiment of the invention, a host or other controller writing to multiple DRAMs in a DIMM configuration determines whether there is full write request to at least one of the multiple DRAM's and a partial write request to at least another one of the multiple DRAM's. If so,... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Intellevate

20090172272 - Method and a computer for storage area management: A method for storage management is provided which displays the materials on which it is determined which of the thin provisioning volume or the logical unit (LU) is to be used for storage promotion. The method is executed in a computer system having one or more host computers, one or... Agent: Stanley P. Fisher Reed Smith LLP

20090172275 - Data usage profiling by local storage device: A local storage device (LSD) is provided configured to have a host device (HD) in communication with the LSD. The LSD includes a memory array. The LSD is configured to characterize data access usage of the LSD by at least one program executing on the HD. The LSD is configured... Agent: Beyer Law Group LLP/ Sandisk

20090172278 - Method and system for backing up and restoring online system information: A method and system for copying operating system information to said at least two storage devices, selectively hiding at least one, but not all, of the storage devices from being accessed by the operating system, and selectively revealing one or more of said hidden storage devices as needed to permit... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090172273 - Method and system for disk storage devices rebuild in a data storage system: In a data storage system, failed disk drives are switched temporarily off-line to be quickly rebuilt by executing a journaling/rebuild algorithm which tracks the updates to the failed disk drive into a journal structure created in a non-volatile memory. The journal information is used to update those data sections of... Agent: Rosenberg, Klein & Lee

20090172277 - Raid level migration method for performing online raid level migration and adding disk to destination raid, and associated system: A Redundant Array of Independent Disks (RAID) level migration method for performing an online RAID level migration and adding a disk to a destination RAID is provided. First, the required information for migration is specified, and then a degraded mode is used to establish the destination RAID, and file system... Agent: North America Intellectual Property Corporation

20090172274 - Storage device having direct user access: Various methods, devices and systems are described for providing distributed storage services. A data storage device is capable of initiating a communication session with an external entity such as a local host computer (and vice versa) coupled directly to the data storage device, a remote server computer, or directly with... Agent: Beyer Law Group LLP/ Sandisk

20090172276 - Storage device having remote storage access: A method of servicing a command sent from a host device file system (HDFS) within a host device (HD) by a local storage device (LSD) in communication with the HD is described. The method includes receiving a first command at the LSD instructing the LSD to execute an operation on... Agent: Beyer Law Group LLP/ Sandisk

20090172281 - Memory device and method for content virtualization: A memory device and method for content virtualization are disclosed. In one embodiment, a plurality of directories are created in the memory of the memory device, wherein each of the plurality of directories points to a same storage location of the digital content. In another embodiment, a first header for... Agent: Brinks Hofer Gilson & Lione/sandisk

20090172279 - System for accessing a removable non-volatile memory card: A non-volatile memory interface device contains first, second, and third communication interfaces configured for first, second, and third protocols, respectively. The device also contains a memory controller that selectively communicates between the first and second communication interfaces, and between the first and third communication interfaces. The device also contains a... Agent: Brinks Hofer Gilson & Lione/sandisk

20090172280 - Systems and methods for fast state modification of at least a portion of non-volatile memory: A method is provided for reducing the number of writes in a non-volatile memory (122). The method involves writing data in the non-volatile memory and determining a set of data from the data in the non-volatile memory to be written to a removable memory (126) that is operatively coupled to... Agent: Client 21058 C/o Darby & Darby P.C.

20090172282 - Digital circuits and methods for testing a digital circuit: Digital circuits and methods for testing a digital circuit are disclosed. One embodiment provides a digital circuit having a first plurality of storage elements, and a second plurality of storage elements. The digital circuit is operable in a first operation mode and in a second operation mode. In the first... Agent: Dicke, Billig & Czaja

20090172283 - Reducing minimum operating voltage through hybrid cache design: Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a... Agent: Caven & Aghevli LLC C/o Cpa Global

20090172284 - Method and apparatus for monitor and mwait in a distributed cache architecture: A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR... Agent: Larry Mennemeier Intel Corporation

20090172285 - Tracking temporal use associated with cache evictions: A method and apparatus for tracking temporal use associated with cache evictions to reduce allocations in a victim cache is disclosed. Access data for a number of sets of instructions in an instruction cache is tracked at least until the data for one or more of the sets reach a... Agent: Larry Mennemeier Intel Corporation

20090172286 - Method and system for balancing host write operations and cache flushing: A method and system for balancing host write operations and cache flushing is disclosed. The method may include steps of determining an available capacity in a cache storage portion of a self-caching storage device, determining a ratio of cache flushing steps to host write commands if the available capacity is... Agent: Brinks Hofer Gilson & Lione/sandisk

20090172289 - Cache memory having sector function: A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information... Agent: Staas & Halsey LLP

20090172287 - Data bus efficiency via cache line usurpation: Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some... Agent: Emulex Design & Manufacturing Corporation C/o Morrison & Foerster LLP

20090172288 - Processor having a cache memory which is comprised of a plurality of large scale integration: To provide an easy way to constitute a processor from a plurality of LSIs, the processor includes: a first LSI containing a processor; a second LSI having a cache memory; and information transmission paths connecting the first LSI to a plurality of the second LSIs, in which the first LSI... Agent: Stanley P. Fisher Reed Smith LLP

20090172290 - Replacing stored content to make room for additional content: The storage of items, such as media items, in a playback device may be managed automatically without user intervention in some embodiments. An algorithm, based on heuristics, may predict which items are most likely to be used or played in the future and, based on that determination, may select the... Agent: Trop, Pruner & Hu, P.C.

20090172291 - Mechanism for effectively caching streaming and non-streaming data patterns: A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access... Agent: Intel Corporation C/o Cpa Global

20090172292 - Accelerating software lookups by using buffered or ephemeral stores: A method and apparatus for accelerating lookups in an address based table is herein described. When an address and value pair is added to an address based table, the value is privately stored in the address to allow for quick and efficient local access to the value. In response to... Agent: Intel Corporation C/o Cpa Global

20090172293 - Methods for prefetching data in a memory storage structure: A method includes detecting a cache miss. The method further includes, in response to detecting the cache miss, traversing a plurality of linked memory nodes in a memory storage structure being used to store data to determine if the memory storage structure is a binary tree. The method further includes,... Agent: Barnes & Thornburg, LLP

20090172295 - In-memory, in-page directory cache coherency scheme: In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090172294 - Method and apparatus for supporting scalable coherence on many-core products through restricted exposure: In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache... Agent: Trop, Pruner & Hu, P.C.

20090172296 - Cache memory system and cache memory control method: A cache memory system including a processing unit and a cache memory which is connected to the processing unit, wherein when a store instruction of storing write data into a certain address is executed, the cache memory system executes selectively one of, a first operation mode of allocating an area... Agent: Arent Fox LLP

20090172297 - Cache memory system and cache memory control method: A cache memory system that is connected to a computation device and a memory device includes: a data array that includes a plurality of blocks composed of a plurality of words; a storage unit that, with respect to a block, which stores data in at least one of said words,... Agent: Sughrue Mion, PLLC

20090172298 - Cached dirty bits for context switch consistency checks: Embodiments of an invention using cached dirty bits for context switch consistency checks are disclosed. In one embodiment, a processor includes control logic and a cache. The control logic is to cause a consistency check to be performed on a subset of a plurality of state components during a first... Agent: Intel Corporation C/o Cpa Global

20090172300 - Device and method for creating a distributed virtual hard disk on networked workstations: During writing of the data, checking the table to find a suitable entry in the table, sending the data to one of the other workstation PCs and entering a reference in the table on the other workstation PC which has acquired the data.... Agent: Nixon Peabody LLP

20090172299 - System and method for implementing hybrid single-compare-single-store operations: A hybrid Single-Compare-Single-Store (SCSS) operation may exploit best-effort hardware transactional memory (HTM) for good performance in the case that it succeeds, and may transparently resort to software-mediated transactions if the hardware transactional mechanisms fail. The SCSS operation may compare a value in a control location to a specified expected value,... Agent: Mhkkg/sun

20090172310 - Apparatus and method for controlling memory overrun: A memory address filter is configurable to emulate memory overrun performance of a legacy memory using an electronic memory of equal or greater capacity. The address filter includes a comparator configured to determine whether a target address is greater than a maximum legacy-address. Memory emulation at target address values greater... Agent: Teradyne, Inc. C/o Foley & Larder, LLP

20090172309 - Apparatus and method for controlling queue: An apparatus includes a queue element which stores a plurality of memory access requests to be issued to a memory device, the memory access requests including a store request and a load request, and a controller which changes an order of the store and load requests so that the order... Agent: Mcginn Intellectual Property Law Group, PLLC

20090172311 - Apparatus for testing memory device: Embodiments relate to an apparatus that may test a memory device. According to embodiments, a period of memory development may be reduced in a manner of testing a delay of a major part in a memory by adding a simple circuit without using expensive equipment and by which a memory... Agent: Sherr & Vaughn, PLLC

20090172305 - Efficient non-transactional write barriers for strong atomicity: A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between... Agent: Intel Corporation C/o Cpa Global

20090172312 - Electronic device with serial ata interface and power saving method for serial ata buses: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be... Agent: Foley And Lardner LLP Suite 500

20090172313 - Electronic device with serial ata interface and power saving method for serial ata buses: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be... Agent: Foley And Lardner LLP Suite 500

20090172303 - Hybrid transactions for low-overhead speculative parallelization: A method and apparatus for a hybrid transactional memory system is herein described. A first transaction is executed utilizing a first style of a transactional memory system and a second transaction is executed in parallel utilizing a second style of a transactional memory system. For example, a main thread is... Agent: Intel Corporation C/o Cpa Global

20090172302 - Information processing apparatus, information processing method, and program: The present invention relates to an information processing apparatus, an information processing method, and a program capable of simplifying an interrupt processing and reducing a time necessary to the interrupt processing. An interrupt generation unit 140 generates an interrupt signal. An interrupt status holding unit 142 stores an interrupt status... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090172301 - Intelligent network interface card (nic) optimizations: Intelligent NIC optimizations includes system and methods for Token Table Posting, use of a Master Completion Queue, Notification Request Area (NRA) associated with completion queues, preferably in the Network Interface Card (NIC) for providing notification of request completions, and what we call Lazy Memory Deregistration which allows non-critical memory deregistration... Agent: Unisys Corporation

20090172304 - Obscuring memory access patterns in conjunction with deadlock detection or avoidance: Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090172308 - Storage controller for flash memory including a crossbar switch connecting a plurality of processors with a plurality of internal memories: A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a plurality of internal memories. The memories contain work lists for the processors. In one embodiment, the processors communicate by using the... Agent: Haynes And Boone, LLPIPSection

20090172307 - Storage device with transaction indexing capability: In one aspect, a system for indexing transactions over a plurality of communication lines is described. In various embodiments, the system includes a host controller and a plurality of storage devices in communication with one another. Each of the storage devices is configured to store data. The communication lines facilitate... Agent: Beyer Law Group LLP/ Sandisk

20090172306 - System and method for supporting phased transactional memory modes: A phased transactional memory (PhTM) may support a plurality of transactional memory implementations, including software, hardware, and hybrid implementations, and may provide mechanisms for dynamically transitioning between transactional memory modes in response to changing workload characteristics; upon discovering that the current mode does not perform well, is not suitable, or... Agent: Mhkkg/sun

20090172314 - Code reuse and locality hinting: A method and apparatus for handling reusable and non-reusable code is herein described. Page table entries include code reuse and locality fields to hold hints for associated pages. If a code reuse and locality field holds a non-reusable value to indicate an associated page holds non-reusable code, then an instruction... Agent: Intel Corporation C/o Cpa Global

20090172316 - Multi-level page-walk apparatus for out-of-order memory controllers supporting virtualization technology: The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level page-walks with an out-of-order memory controller. In embodiments of the invention, the multi-level page-walk apparatus includes a demotion-based priority grant arbiter, a page-walk tracking... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Cpa Global

20090172315 - Priority aware selective cache allocation: A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation probabilities for each priority level are updated based on... Agent: Intel Corporation C/o Cpa Global

20090172317 - Mechanisms for strong atomicity in a transactional memory system: A method and apparatus for providing efficient strong atomicity is herein described. Optimized strong operations may be inserted at non-transactional read accesses to provide efficient strong atomicity. A global transaction value is copied at a beginning of a non-transational function to a local transaction value; essentially creating a local timestamp... Agent: Intel Corporation C/o Cpa Global

20090172318 - Memory control device: A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the... Agent: Staas & Halsey LLP

20090172319 - Systems and methods for recovering electronic information from a storage medium: In one embodiment of the invention, a method is provided for retrieving certain electronic information previously stored on certain storage media after a threshold set in the storage retention criteria has been exceeded in an electronic information storage system that stores electronic information on storage media in accordance with a... Agent: Perkins Coie LLP Patent-sea

20090172320 - Keystroke monitoring apparatus and method: Keystrokes input by a user are stored in non-volatile memory together with time stamps, creating a record of keystrokes and associated time stamps. At least some of the time stamps are generated and recorded in response to receipt of specific keystroke events, such as a specific keystroke, a specific sequence... Agent: Nixon & Vanderhye, PC

20090172321 - Storage sub-system for a computer comprising write-once memory devices and write-many memory devices and related method: Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-once storage sub-system memory device and a write-many storage sub-system memory device. Numerous other aspects are provided.... Agent: Dugan & Dugan, PC

20090172322 - Automatically adjusting a number of backup data sources concurrently backed up to a storage device on a server computer: Various embodiments of a system and method for backing up data to a backup server computer are disclosed. According to one embodiment of the method, a group of backup data sources may be associated with a writer module on the backup server computer. Each backup data source may comprise data... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20090172326 - Emulated storage system supporting instant volume restore: In a back-up storage system, an apparatus and methods for mounting a data volume corresponding to a back-up data set to a host computer. In one example, a method includes mounting a data volume on a host computer, the data volume comprising at least one data file, the data file... Agent: Lowrie, Lando & Anastasi, LLP

20090172325 - Information processing apparatus and data recovering method: In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090172323 - Methods and appratus for demand-based memory mirroring: A method includes determining an amount of memory space in a memory device available for memory mirroring. The method further includes presenting the available memory space to an operating system. The method further includes selecting at least a portion of the amount of memory space to be used for memory... Agent: Barnes & Thornburg, LLP

20090172324 - Storage system and method for opportunistic write-verify: A storage system that stores verify commands for all the write commands requiring verification in a verify-list that will be processed as a background task is described. The verify-list can include coded data fields that flexibly designate selected alternative states or possibilities for how and where the user data is... Agent: Marlin Knight

20090172332 - Information processing apparatus and method of updating stack pointer: A instruction execution part of an information processing device outputs an access request including a first address information to specify an access destination based on an execution of an access command of an address space in a memory. The instruction execution part also outputs a check request including a second... Agent: Mcginn Intellectual Property Law Group, PLLC

20090172327 - Optimistic semi-static transactional memory implementations: A lock-based software transactional memory (STM) implementation may determine whether a transaction's write-set is static (e.g., known in advance not to change). If so, and if the read-set is not static, the STM implementation may execute, or attempt to execute, the transaction as a semi-static transaction. A semi-static transaction may... Agent: Mhkkg/sun

20090172330 - Protection of user-level applications based on page table information: In one embodiment, the present invention includes a virtual machine monitor (VMM) to access a protection indicator of a page table entry (PTE) of a page of a set of memory buffers and determine a state of the protection indicator, and if the protection indicator indicates that the page is... Agent: Trop, Pruner & Hu, P.C.

20090172329 - Providing secure services to a non-secure application: A data processing apparatus comprising a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor processing data in said non-secure mode; and a further processing... Agent: Nixon & Vanderhye, PC

20090172331 - Securing content for playback: A graphics engine may include a decryption device, a renderer, and a sprite or overlay engine, all connected to a display. A memory may have a protected and non-protected portions in one embodiment. An application may store encrypted content on the non-protected portion of said memory. The decryption device may... Agent: Trop, Pruner & Hu, P.C.

20090172328 - System and method for high performance secure access to a trusted platform module on a hardware virtualization platform: A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. The virtualization platform including Virtual Machine Monitor (VMM) managed components coupled to the VMM. One of the VMM managed components is a TPM (Trusted Platform Module). The virtualization platform also includes... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090172333 - Storage device coordinator and a host device that includes the same: A storage device coordinator intercepts a memory command issued by a host device and intended for a target storage device which is one of a plurality of storage devices, and, if the memory command is not optimal, transforms the memory command into one or more storage commands, each being associated... Agent: Mark M. Friedman

20090172334 - Data sorting device and method thereof: A data sorting device and a method thereof are disclosed, wherein the data sorting device includes plural storage modules and an enabling controller. Moreover, each storage module has a falling edge-triggered register and a rising edge-triggered register, and each storage module receives a serial data in response to the rising... Agent: Rosenberg, Klein & Lee

20090172336 - Allocating memory in a broker system: Memory allocation in a Broker system for managing the communication between a plurality of clients and a plurality of servers. The method may include allocating memory for a plurality of memory pools; and dividing each memory pool into memory blocks of a size which is specific to the type of... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20090172337 - Cooperative mechanism for efficient application memory allocation: System, method and computer program product for allocating physical memory to processes. The method includes enabling a kernel to free memory in a physical memory space corresponding to arbitrarily sized memory allocations released by processes or applications in a virtual memory space. After freeing the memory, the system determines whether... Agent: Mh2 Technology Law Group (cust. No. W/red Hat)

20090172335 - Flash devices with raid: Methods and apparatus of the present invention include multiple flash storage devices that are configured to form a single storage device that is flexible and scalable. Reliability and performance are improved while keeping the power consumption benefits compared to conventional hard disk drives.... Agent: Patterson & Sheridan, L.L.P.

20090172338 - Feedback linker for increased delta performance: A method, system and program for generating an updated memory image including updated program code to be loaded into a storage medium that has stored thereon a current memory image including a current program code version. The method comprises receiving an updated input code comprising a number of segments, wherein... Agent: Ericsson Inc.

20090172339 - Apparatus and method for controlling queue: An apparatus includes a queue element which stores a plurality of memory access requests to be issued to a memory device, the memory access requests including a store request and a load request, and a controller which controls the queue element. The controller includes an address decision element which decides... Agent: Mcginn Intellectual Property Law Group, PLLC

20090172340 - Methods and arrangements to remap non-volatile storage: Methods and arrangements for remapping the map between logical space and physical space in non-volatile storage are described. Embodiments include transformations, code, state machines or other logic to divide the non-volatile storage of the computing device into two portions, a fixed portion and a floating portion. The embodiments may also... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Cpa Global

20090172342 - Robust index storage for non-volatile memory: A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth

20090172341 - Using a memory address translation structure to manage protected micro-contexts: Embodiments of an invention for using a memory address translation structure to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an... Agent: Intel Corporation C/o Cpa Global

20090172344 - Method, system, and apparatus for page sizing extension: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned.... Agent: Pearl Cohen Zedek Latzer, LLP

20090172343 - Using a translation lookaside buffer to manage protected micro-contexts: Embodiments of an invention for using a translation lookaside buffer to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated... Agent: Intel Corporation C/o Cpa Global

20090172346 - Transitioning between software component partitions using a page table pointer target list: Embodiments of apparatuses, articles, methods, and systems for intra-partitioning components within an execution environment, and transitioning between partitions using a page table pointer target list are generally described herein. Other embodiments may be described and claimed.... Agent: Intel Corporation C/o Cpa Global

20090172345 - Translation management of logical block addresses and physical block addresses: Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control... Agent: Turocy & Watson, LLP

20090172347 - Data storage device: A storage device includes a memory for storing data in a plurality of logical volumes; a controlling unit for controlling an access to data in accordance with a process comprising the steps of: generating mapping information indicative of a correspondence between logical volume information and recognition information; generating a pseudo... Agent: Staas & Halsey LLP