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Electrical computers and digital processing systems: memory inventions 05/09

Recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing format for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
05/28/2009 > patent applications in patent subcategories.

20090138648 - Data processing device, recording medium, and data processing method: A first updating unit updates the state of access control of the data to be edited set up in the memory to an exclusive state in response to an exclusion request to the data to be edited. A second updating unit updates the state of access control of the data... Agent: Gauthier & Connors, LLP

20090138649 - Nonvolatile memory system and method of decentralizing the peak current in a nonvolatile memory system: A nonvolatile memory system has a controller chip connected to a memory medium and several nonvolatile memory chips. The memory medium stores program codes for the controller chip to distribute an operation of the nonvolatile memory chips upon an instruction over time, so as to decentralize the peak current caused... Agent: Rosenberg, Klein & Lee

20090138653 - Electronic apparatus and method of controlling a memory unit connected to the same: An electronic apparatus in which a memory unit containing a memory and a controller to access the memory in response to an externally input command can be installed. The electronic apparatus comprises a first acquiring section which acquires identification information from the memory unit, a second acquiring section which, on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090138651 - Encoding method for flash memories: A encoding method for a flash memory is provided, which can be used for reducing the memory wear and extend the endurance of the memory. The encoding method includes the steps as follows: (A) receiving a set of information bits; (B) counting an amount of the information bits needed to... Agent: Volpe And Koenig, P.C.

20090138654 - Fatigue management system and method for hybrid nonvolatile solid state memory system: A solid state memory system comprises a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses, and a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses. The first write cycle lifetime is greater... Agent: Harness, Dickey & Pierce P.L.C

20090138650 - Method and apparatus for managing firmware of an optical storage apparatus: A method of managing a firmware includes configuring the firmware to include at least a first firmware portion with a plurality of program codes, and a second firmware portion with a plurality of parameters separately; and storing the first firmware portion and the second firmware portion in a first storage... Agent: North America Intellectual Property Corporation

20090138652 - Non-volatile memory generating different read voltages: In one aspect, a non-volatile memory is provided which includes a plurality of m-bit non-volatile memory cells and a plurality of n-bit non-volatile memory cells, where 1≦m<n, and a voltage generator which generates a first read voltage applied to non-selected m-bit non-volatile memory cells and a second read voltage applied... Agent: Volentine & Whitt PLLC

20090138655 - Method and terminal for demand paging at least one of code and data requiring real-time response: A method and terminal for demand paging at least one of code and data requiring a real-time response is provided. The method includes splitting and compressing at least one of code and data requiring a real-time response to a size of a paging buffer and storing the compressed at least... Agent: JeffersonIPLaw, LLP

20090138656 - Method of skipping synchronization process for initialization of raid1 device: A method for skipping an initialization process of synchronization of an RAID 1 device skips synchronization process of the RAID1 device through a bitmap technique. First, an RAID1 device is established, a space of the same size is divided from each member disk of the RAID1 device for storing a... Agent: Rabin & Berdo, PC

20090138658 - Cache memory system for a data processing apparatus: A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it... Agent: Nixon & Vanderhye P.C.

20090138657 - Data backup system for logical volume manager and method thereof: A data backup system for a logical volume manager (LVM) and a method thereof, capable of realizing data backup in the LVM having a battery backed cache memory (BBCM). The data backup system includes a physical storage device, a BBCM, an LVM, and a data backup function. The physical storage... Agent: Morris Manning Martin LLP

20090138659 - Mechanism to accelerate removal of store operations from a queue: A processor includes at least one processing core. The processing core includes a memory cache, a store queue, and a post-retirement store queue. The processing core retires a store in the store queue and conveys the store to the memory cache and the post-retirement store queue, in response to retiring... Agent: Rory D. Rankin Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20090138660 - Power-aware line intervention for a multiprocessor snoop coherency protocol: A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each... Agent: Hamilton & Terrile, LLP IBM Austin

20090138661 - Prefetch instruction extensions: A computer system and method. In one embodiment, a computer system comprises a processor and a cache memory. The processor executes a prefetch instruction to prefetch a block of data words into the cache memory. In one embodiment, the cache memory comprises a plurality of cache levels. The processor selects... Agent: Rory D. Rankin Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20090138662 - Floating point bypass retry: A system and method for increasing the throughput of a processor during cache misses. During the retrieval of the cache miss data, subsequent memory requests are generated and allowed to proceed to the cache. The data for the subsequent cache hits are stored in a bypass retry device. Also, the... Agent: Rory D. Rankin Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20090138663 - Cache memory capable of adjusting burst length of write-back data in write-back operation: A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the... Agent: Mills & Onello LLP

20090138664 - Cache injection using semi-synchronous memory copy operation: A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.

20090138665 - Memory controller: To provide a memory controller capable of flexibly dealing with the change in the form of use or operation state of a system, a memory controller (1100) includes bus interfaces (1200, 1210, 1220), a memory controller core unit (1300), and a memory interface (1400). The memory controller core unit (1300)... Agent: Fitzpatrick Cella Harper & Scinto

20090138666 - Write set boundary management in support of asynchronous update of secondary storage: A color control node includes an interface for communicating with multiple storage controllers, wherein the storage controllers maintain a primary storage system at a primary site and a secondary storage system at a secondary site; and wherein the storage controllers maintain a current color and associate all writes with the... Agent: Michael Buchenhorner, P.A.

20090138667 - Method and apparatus for configuration management of computer system: A management computer collects, from a storage subsystem via a management network, path definition information including the contents of a security setting made to a path accessible to a volume in the storage subsystem, and when the volume in the storage subsystem is an original volume having a replica volume,... Agent: Mattingly & Malur, P.C.

20090138668 - Data interleaving circuit and method for vectorized turbo decoder: A data interleaving circuit and method for interleaving a data block comprising M windows of W values include an index generator for generating an intra-window index w and an inter-window permutation vector m having M elements and an inter-window permutation circuit operable to receive M data values having intra-window index... Agent: Motorola, Inc.

20090138669 - Frequency converter: The present invention relates to a frequency converter (1) comprising a memory (M1) for storing data; a controller (8) for controlling the operation of the frequency converter by utilizing data (DATA1) stored in the memory (M1); and an interface (10) for connecting the frequency converter to other frequency converters. For... Agent: Buchanan, Ingersoll & Rooney PC

20090138670 - software-configurable and stall-time fair memory access scheduling mechanism for shared memory systems: Systems and methodologies for stall-time fair memory access scheduling for shared memory systems are provided herein. A stall-time fairness policy can be applied in accordance with various aspects described herein to schedule memory requests from threads sharing a memory system. To this end, a Stall-Time Fair Memory scheduler (STFM) algorithm... Agent: Amin, Turocy & Calvin, LLP

20090138671 - System, method, and computer program product for increasing spare space in memory to extend a lifetime of the memory: A system, method, and computer program product are provided for extending a lifetime of memory. In operation, spare space in memory is increased. Additionally, a lifetime of the memory is extended, as a result of increasing the spare space in the memory.... Agent: Zilka-kotab, PC

20090138672 - Storage controller and storage controller control method: A storage controller of the present invention can input and output data even when the track size, which is the host management unit, is not consistent with the block size of the storage device. A boundary correction unit adds gap data corresponding to a gap size to data in a... Agent: Stanley P. Fisher Reed Smith LLP

20090138673 - Internal memory mapped external memory interface: This is directed to allowing a processor of a device to use ordinary internal memory read and write instructions that read and write to external memory. Thus, the complexities associated with the existing methods of accessing external memory can be avoided. More specifically, an address space portion that does not... Agent: Apple C/o Morrison And Foerster ,llp Los Angeles

  
05/21/2009 > patent applications in patent subcategories.

20090132749 - Cache memory system: Systems and methods are disclosed for pre-fetching data into a cache memory system. These systems and methods comprise retrieving a portion of data from a system memory and storing a copy of the retrieved portion of data in a cache memory. These systems and methods further comprise monitoring data that... Agent: Docket Clerk

20090132750 - Cache memory system: The present disclosure provides systems and methods for a cache memory and a cache load circuit. The cache load circuit is capable of retrieving a portion of data from the system memory and of storing a copy of the retrieved portion of data in the cache memory. In addition, the... Agent: Docket Clerk

20090132751 - Ethernet controller: A controller, in particular an Ethernet controller has a control unit operable to receive commands and data through an I/O interface; a plurality of registers arranged in a register block which is divided into a plurality of register banks, wherein at least one register controls a function of the controller;... Agent: Baker Botts, LLP

20090132754 - Data storage device with histogram of idle time and scheduling of background and foreground jobs: A data storage device includes a cumulative data histogram of lengths of idle times between foreground user service requests. The cumulative data histogram is updated with measured lengths of current idle times between successive user service requests. Background service request are scheduled following a user service request after a time... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.

20090132755 - Fault-tolerant non-volatile integrated circuit memory: Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread... Agent: Knobbe Martens Olson & Bear LLP

20090132752 - Interface for non-volatile memories: A portable storage device for storage of data. The portable storage device comprises a first non-volatile memory of a first character; a second non-volatile memory of a second character, the second character being different to the first character; and a controller for determining to which of the first and second... Agent: Jacobson Holman PLLC

20090132756 - Portable flash memory storage device that may show its remaining lifetime: A portable flash memory storage device that may show its remaining lifetime according to this invention is provided, in which an average erase count that is stored may be read and, after being processed and converted, is formed into a piece of information on its remaining lifetime that is further... Agent: Rosenberg, Klein & Lee

20090132758 - Rank modulation for flash memories: We investigate a novel storage technology, Rank Modulation, for flash memories. In this scheme, a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, and overshoot errors when programming cells... Agent: Townsend And Townsend And Crew, LLP

20090132753 - Replication management system and method with undo and redo capabilities: A method for replicating a volume of data including UNDO and REDO data replication commands includes identifying a current state of the database through a point in time (PIT) copy of all volumes to be affected, ensuring that enough storage volume is identified to carry out the point in time... Agent: Kunzler & Mckenzie

20090132757 - Storage system for improving efficiency in accessing flash memory and method for the same: A storage system for improving efficiency in accessing flash memory and method for the same are disclosed. The present invention provides a cache unit for temporarily storing data prior to writing in the flash memory or reading from the flash memory. In reading process, after data stored in a flash... Agent: Kirton And Mcconkie

20090132759 - Information processing apparatus and method for controlling information processing apparatus: Disclosed herein is an information processing apparatus including: a dynamic random access memory; a memory controller that manages accesses to the dynamic random access memory on a bank basis; a cache memory that is connected to the memory controller via a bus and which caches data stored in the dynamic... Agent: Rader Fishman & Grauer PLLC

20090132760 - Apparatus, system, and method for solid-state storage as cache for high-capacity, non-volatile storage: An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request.... Agent: Kunzler & Mckenzie

20090132761 - Storage management method and system using the same: A storage management system and a storage management method are provided. The storage management system includes a host, a memory buffer, a plurality of storage blocks, and an input/output bus to perform an interface function among the host, the memory buffer, and the plurality of storage blocks, wherein each of... Agent: Mcneely Bodendorf LLP

20090132763 - Memory cards having two standard sets of contacts and a hinged contact covering mechanism: Enclosed re-programmable non-volatile memory cards include at least two sets of electrical contacts to which the internal memory is connected. The two sets of contacts have different patterns, preferably in accordance with two different contact standards such as a memory card standard and that of the Universal Serial Bus (USB).... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20090132762 - Removable nonvolatile memory system with functional inhibition: A removable nonvolatile memory system is provided including inserting a nonvolatile memory into an electronic system; storing timing information onto a passive device coupled with the nonvolatile memory; extracting the nonvolatile memory from the electronic system; and enabling a read function from the nonvolatile memory based on the timing information... Agent: Law Offices Of Mikio Ishimaru

20090132764 - Power conservation via dram access: Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific... Agent: Osha Liang L.L.P./sun

20090132765 - Dual controller storage apparatus and cache memory mirror method thereof: A dual controller storage apparatus and a cache memory mirror method thereof are described. The storage apparatus includes a imaging environment module, a storage device, a first controller, and a second controller. The first controller has a virtual disk and a first cache memory. The second controller has a second... Agent: Stevens & Showalter LLP

20090132766 - Systems and methods for lookahead instruction fetching for processors: Systems and methods may be provided for lookahead instruction fetching for processors. The systems and methods may include an L1 instruction cache, where the L1 instruction cache may include a plurality of lines of data, where each line of data may include one or more instructions. The systems and methods... Agent: Sutherland Asbill & Brennan LLP

20090132767 - Complier assisted victim cache bypassing: A method for compiler assisted victim cache bypassing including: identifying a cache line as a candidate for victim cache bypassing; conveying a bypassing-the-victim-cache information to a hardware; and checking a state of the cache line to determine a modified state of the cache line, wherein the cache line is identified... Agent: Cantor Colburn LLP - IBM Austin

20090132768 - Cache memory system: Systems and methods are disclosed that comprise a cache memory for storing a copy of a portion of data stored in a system memory and a cache load circuit capable of retrieving the portion of data from the system memory. The systems and methods further comprise a status memory for... Agent: Docket Clerk

20090132769 - Statistical counting for memory hierarchy optimization: Systems and methods that optimize memory allocation in hierarchical and/or distributed data storage. A memory management component facilitates a compact manner of identifying approximately how often the memory chunk is being used, to promote efficient operation of the system as a whole. Each memory location can be changed based on... Agent: Amin, Turocy & Calvin, LLP

20090132770 - Data cache architecture and cache algorithm used therein: The present invention provides a data cache architecture interposed between a host and a flash memory, the data cache architecture comprising: a buffer memory, receiving data from the host; a memory controller, deploying the data in the buffer memory; and a data cache memory, controlled by the memory controller according... Agent: Wpat, PC

20090132771 - Method and apparatus for accessing image data: The invention relates to data accessing method and apparatus, and more particularly to data accessing method and apparatus for accessing a first-in first-out (FIFO) buffer compatible with mini-low voltage differential signal (mini-LVDS) transmission interface. The image data accessing apparatus comprises a FIFO memory for storing the image data, and a... Agent: Rabin & Berdo, PC

20090132772 - System and method for performing data reading and writing on physical storage device: A system and a method for performing data reading and writing on a physical storage device. A plurality of controllers under a common storage environment is used to realize data read and write operation performed on the physical storage device by a remote client. Firstly, the client assigns a controller... Agent: Rabin & Berdo, PC

20090132773 - Apparatus and method to merge and align data from distributed memory controllers: We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory interface to manipulate data from at least two memory channels, each memory channel corresponding to a portion of... Agent: Caven & Aghevli LLC C/o Cpa Global

20090132774 - Methods for implementation of worm enforcement in a storage system: Embodiments of archival storage system are disclosed. The archival storage system includes one or more removable disk drives that provide random access and are readily expandable. In embodiments, some or all of the data within the removable disk drive(s) is immutable. The archiving system creates a designation for the data... Agent: Townsend And Townsend And Crew, LLP

20090132775 - Methods and apparatus for archiving digital data: Method and apparatus are disclosed to enable secure archiving and backup of data with reduced risk of data lost. Additionally, embodiments are provided which enable reduction of costs for CAS backup of archived files by use of low-cost tape storage devices rather than expensive hard drive devices.... Agent: Sughrue Mion, PLLC

20090132776 - Data processing device, data processing method, data processing program, recording medium containing the data processing program and intergrated circuit: A data processing device for processing stream data composed of a plurality of frames generated with encoded contents data, which includes a protected storage unit for storing data, being protected from external access, a non-protected storage unit for storing data, a receiving unit for receiving stream data, a separating unit... Agent: Ratnerprestia

20090132777 - Systems and methods for protecting customer secrets during vendor troubleshooting: Systems, methods, and computer products for protecting information during troubleshooting are provided. A dumping mechanism includes marking at least one of a plurality of memory regions in the computer-readable medium as non-dumpable, initiating a core dump, determining which memory regions of the plurality regions are non-dumpable, and dumping the contents... Agent: Sonnenschein Nath & Rosenthal LLP

20090132779 - Storage system and remote copy control method: A plurality of second groups respectively including one or more second volumes are configured in correspondence with each of the first groups of a remote copy source in a remote copy destination, journals are acquired from the first storage apparatus periodically and in the order the journals were created for... Agent: Sughrue Mion, PLLC

20090132778 - System, method and a computer program product for writing data to different storage devices based on write frequency: A system, method, and computer program product are provided for writing data to different storage devices based on write frequency. In operation, a frequency in which data is written is identified. Additionally, a plurality of storage devices of different types is selected from to write the data, based on the... Agent: Zilka-kotab, PC

20090132780 - Cache line reservations: Illustrative embodiments provide a computer implemented method, an apparatus in the form of a data processing system and a computer program product for cache line reservations. In one embodiment, the computer implemented method comprises, dividing a memory into an unreserved section and a set of reserved sections. The method performs... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090132781 - Memory hub with integrated non-volatile memory: A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for receiving memory access requests, a non-volatile memory having memory configuration information stored therein, and a memory controller coupled to the high-speed interface and the non-volatile memory. The memory... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090132782 - Compressing and decompressing image data without introducing artifacts: An apparatus may include a memory to store a first frame, a buffer to store at least one portion of a second frame previously stored in the memory, and first and second units to, respectfully, store and fetch data. The first unit may copy a datum of the second frame... Agent: Epson Research And Development Inc Intellectual Property Dept

20090132783 - System and method of determining an address of an element within a table: In a particular embodiment, a method is disclosed that includes executing a single instruction to identify a location within a table stored at a memory. The single instruction is executable by a processor to extract bit field data from a first register and insert the bit field data into an... Agent: Qualcomm Incorporated

20090132784 - Cache memory and method of operating the same: Provided are a cache memory using a linear hash function and a method of operating the same. The cache memory includes: a first hash function module for converting a main memory address received from a central processing unit (CPU) into a first index value using a first hash function; a... Agent: Ladas & Parry LLP

  
05/14/2009 > patent applications in patent subcategories.

20090125667 - Method of controlling power consumption of a memory according to mapping: There is provided a method of controlling power consumption of a memory, which is executed in a computer system including operation server and a management server. The operation server includes one or more memory chips which are units to control the power consumption of the memory, a power control module... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090125671 - Apparatus, system, and method for storage space recovery after reaching a read count limit: An apparatus, system, and method are disclosed for storage space recovery after reaching a read count limit. A read module reads data in a storage division of solid-state storage. A read counter module then increments a read counter corresponding to the storage division. A read counter limit module determines if... Agent: Kunzler & Mckenzie

20090125670 - Erase block management: An improved Flash memory device with a distributed erase block management (EBM) scheme is detailed that enhances operation and helps minimize write fatigue of the floating gate memory cells of the Flash memory device. The Flash memory device of the invention combines the EBM data in a user data erase... Agent: Fogg Slifer & Polglaze, P.A. Att: Andrew C. Walseth

20090125668 - Management of erased blocks in flash memories: The invention relates to a method for managing the erasure process in a memory system comprising individually erasable memory blocks (SB) that can be addressed with the aid of real memory block addresses (SBA). Said memory blocks are sub-divided into a plurality of writable sectors and can be addressed by... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20090125672 - Memory card and host device thereof: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090125673 - Memory card and host device thereof: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090125669 - Preventing data loss in a storage system: Storage servers use a fast, non-volatile or persistent memory to store data until it can be written to slower mass storage devices such as disk drives. If the server crashes before a write can complete, the data remains safely stored in non-volatile memory. If the data cannot be committed to... Agent: Network Appliance/bstz Blakely Sokoloff Taylor & Zafman LLP

20090125674 - Method for polymorphic and systemic structuring of associative memory via a third-party manager: The present invention relates to a method for polymorphic and systemic structuring of associative memory via a third-party manager that allows a human or electronic operator to manage various families of associative memory for various applications.... Agent: Touret

20090125675 - Storage apparatus and logical volume migration method: This storage apparatus includes a first logical volume migration unit for migrating the logical volume of a first storage area targeted for power source shutdown to a second storage area that is not targeted for power source shutdown based on an external command, and a second logical volume migration unit... Agent: Stanley P. Fisher Reed Smith LLP

20090125676 - Information handling system including a logical volume and a cache and a method of using the same: A system and method of recovering cached data can be used when a particular physical storage device becomes unsuitable for storing data. In one aspect, the method can include providing the information handling system including a logical volume and a cache. The cache includes data that is to be stored... Agent: Larson Newman Abel & Polansky, LLP

20090125677 - Intelligent caching of media files: A method of receiving and forwarding a multimedia message is provided. The multimedia message is adapted with a first adaptation profile into a first adapted message to be received in a first device. The multimedia message and the first adapted message are stored in a media cache. The message may... Agent: Victoria Donnelly

20090125679 - Computer and method for reflecting path redundancy configuration of first computer system in second computer system: Mapping management information denoting the mapping of a first host and first host volume and a second host and second host volume is prepared beforehand. First-path-redundancy information, which is related to the redundancy of a first path of the first host volume, is acquired, and a second host volume and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090125681 - Data recording apparatus, method for internal control of data recording apparatus, and data recording system: A data recording apparatus that writes data on/reads data from a hard disk drive in response to a data-write/read command received from an upper control device is provided. The data recording apparatus includes a command-aggregating device and a command-issuing device. The command-aggregating device is configured to generate an aggregate command... Agent: Wolf Greenfield & Sacks, P.C.

20090125678 - Method for reading data with storage system, data managing system for storage system and storage system: Provided is a database management system obtains storage mapping information which associates addresses in a plurality of physical disk drives within the storage system and addresses in logical disk drives including these physical disk drives, to create queues individually for each of the plurality of physical disk drives. The database... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090125680 - Storage system for restoring data stored in failed storage device: The present invention maintains mapping information denoting which real areas have been allocated to which virtual areas for a virtual volume, the capacity of which is dynamically expanded. The present invention also maintains real area management information denoting which real areas have been allocated to which virtual areas. The real... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090125682 - Memory card programmable timer device and method: A timing device, that may be used in connection with food preparation, holding or service equipment, is programmable via a portable, replaceable media. In particularly, the timing device may be adapted to receive or associate with a media containing a set of instructions to affect operation of the timing device.... Agent: Marshall, Gerstein & Borun LLP

20090125683 - Portable auxiliary storage device: Versatility of a memory card is improved by providing a memory card wherein data protection mode and normal mode can be selected at discretion.... Agent: Ratnerprestia

20090125684 - Timer device for monitoring expiration of products: A timer device adapted to monitor time periods associated with foods and other substances which may have a finite time during which they are suitable e for use, comprising a timer unit (8) capable of monitoring a plurality of time periods, each time period being associated with a tag (1)... Agent: Boyle Fredrickson S.c.

20090125685 - Shared memory system for a tightly-coupled multiprocessor: A shared memory system for a multicore computer system utilizing an interconnection network that furnishes tens of processing cores or more with the ability to refer concurrently to random addresses in a shared memory space with efficiency comparable to the typical efficiency achieved when referring to private memories. The network... Agent: Edward Langer C/o Shiboleth Yisraeli Roberts Zisman & Co.

20090125686 - Image forming apparatus and method of controlling the same: An image forming apparatus and method of controlling the same, the image forming apparatus including: an article of consumption including a memory; and a print controller to perform a memory access to read and/or to write data from/to the memory. Addresses for the memory of the article of consumption are... Agent: Stein, Mcewen & Bui, LLP

20090125688 - Memory hub with internal cache and/or memory access prediction: A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090125687 - Method of controlling internal voltage and multi-chip package memory prepared using the same: The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip,... Agent: Volentine & Whitt PLLC

20090125689 - System and article of manufacture for providing an address format compatible with different addressing formats used for addressing different sized address spaces: Provided are a system and article of manufacture for providing an address format compatible with different addressing formats used for addressing different sized address spaces. An address format is used in an operating system to address storage space in a storage device comprising a first region and a second region... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20090125690 - Systems and methods for performing storage operations in a computer network: Methods and systems are described for performing storage operations on electronic data in a network. In response to the initiation of a storage operation and according to a first set of selection logic, a media management component is selected to manage the storage operation. In response to the initiation of... Agent: Knobbe Martens Olson & Bear LLP

20090125691 - Apparatus for managing remote copying between storage systems: A resource status value, which shows the resource status of a resource to be utilized in a remote copy that conforms to a copy mode configured for a copy unit created from a first data volume and a second data volume, is acquired either regularly or irregularly. A determination is... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090125692 - Backup system and method: A storage system, upon receiving a marker from a host computer, executes a generation determination process for determining a generation of a first logical volume that is used by a host computer, and writes information related to the generation determined in this generation determination process to a physical storage device... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090125694 - Storage control apparatus, storage system, and virtual volume control method: The storage control apparatus of the present invention saves a table for managing a virtual volume in a pool and keeps the state of the table in the latest state. A first dynamic mapping table (DMT) that manages a first virtual volume is saved in a first pool. Upon receipt... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090125693 - Techniques for more efficient generation of xml events from xml data sources: One may increase the efficiency of an XML event-generating process by reducing the number of requests to allocate or deallocate system memory. Such reduction may occur as the result of pre-allocating a memory chunk of sufficient size to contain all of the memory buffers required by a particular event-generating process.... Agent: Hickman Palermo Truong & Becker/oracle

20090125695 - Thermal control of memory modules using proximity information: An information handling system includes a processor having access to a system memory. The system is operable to detect a thermal alert and identify an associated portion of system memory. The system may then modify memory allocation information used by an operating system to allocate system memory. When the thermal... Agent: Baker Botts, LLP

20090125698 - Memory controller including a hardware compression and decompression engine for managing system memory and graphical operations: An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high speed system peripheral bus such as the PCI bus and couples to system memory. The IMC preferably... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20090125697 - Method and apparatus for allocation of buffer: Provided are a method and apparatus for allocating a storage space that is to be used by a plurality of modules sequentially processing data. The method includes acquiring first capacity information regarding the capacity of a storage space needed for data processing of a first module and second capacity information... Agent: Sughrue Mion, PLLC

20090125696 - Method for processing a file, storage medium and processing arrangement: A method for processing a file, a storage medium, and a processing arrangement. The method includes processing a file, the file being stored in a plurality of memory clusters of a storage medium, a portion of the file being modified and stored in a modification memory cluster, and the modified... Agent: Dickstein Shapiro LLP

20090125699 - Adjustment of data storage capacity provided by a storage system: A storage system stores data in at least one partition of a physical storage media in accordance with file system information specifying a plurality of logical blocks having logical block addresses within the partition. The logical blocks include excess logical blocks that are not mapped to space in the physical... Agent: Harness, Dickey & Pierce, P.L.C

20090125700 - Processing system having memory partitioning: Memory resource partitioning code allocates a memory partition in response to a process requesting access to memory storage. Memory partition rules may define attributes of the memory partition. The attributes may include a minimum memory allocation and a maximum memory allocation for the memory partition.... Agent: Harman - Brinks Hofer Chicago Brinks Hofer Gilson & Lione

20090125701 - Aggregating data from different sources: A method and system that aggregates data associated with one or more entities from different data sources are provided. The data sources include documents, web pages, or images that have information about one or more entities. The information is extracted from the data sources based on criteria that define the... Agent: Shook, Hardy & Bacon L.L.P. (c/o Microsoft Corporation)

  
05/07/2009 > patent applications in patent subcategories.

20090119442 - Managing write-to-read turnarounds in an early read after write memory system: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20090119443 - Methods for program directed memory access patterns: Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information.... Agent: Cantor Colburn LLP-ibm Burlington

20090119449 - Apparatus and method for use of redundant array of independent disks on a muticore central processing unit: The invention is based on running the entire RAID stack on a dedicated core of one of the cores of the multi-core CPU. This makes it possible to eliminate the use of a conventional separate RAID controller and replace its function with a special flash memory chip that contains a... Agent: Kawaldeep Kaur Sodhi

20090119445 - Computer memory accessible in either power state of the computer: A system on a computer for providing access to data stored on the computer in either power state is provided. The system can include a memory module and an external data interface connector. The system can further include a data interface controller for managing a data interface to the memory... Agent: Carey, Rodriguez, Greenberg & Paul, LLP Steven M. Greenberg

20090119447 - Controlled bit line discharge for channel erases in nonvolatile memory: Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory.... Agent: Amin, Turocy & Calvin, LLP

20090119446 - Divided bitline flash memory array with local sense and signal transmission: A flash memory array and a method for performing read operation therein are disclosed. The flash memory array comprises a plurality of memory segment, a data cache and a plurality of data handlers coupled between a pair of memory segment and between a memory segment and the data cache. A... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Cpa Global

20090119448 - Memory apparatus, and method of averagely using blocks of a flash memory: A flash memory controller for averagely using blocks of a flash memory and the method thereof are provided. The flash memory controller is configured to process wear-leveling by allocating frequently updated data in less-erased blocks, and, allocating less-updated data in frequently erased blocks to achieve dynamic uniformity of times of... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20090119450 - Memory device, memory management method, and program: A memory device includes a non-volatile memory which allows data to be written, read, and erased electrically and in which writing and reading are done in units of a page and erasing is done in units of a block including a plurality of pages, and a control section that manages... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090119444 - Multiple write cycle memory using redundant addressing: The present invention produces a low-cost reliable non-volatile memory with multiple write cycles. The memory circuit trades full configurability for increased reliability and decreased cost by providing a limited number of write or rewrite cycles utilizing an indirectly accessible register set that writes data into fully configurable memory. The circuit... Agent: The Mueller Law Office, P.C.

20090119451 - Redriven/retimed registered dual inline memory module: A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data redriving/retiming circuits connected to the D/Q terminals of the plurality of DRAM chips. The data redriving/retiming circuits may... Agent: SocalIPLaw Group LLP

20090119452 - Method and system for a sharable storage device: Systems and methods for sharable tape devices are presented. More particularly, embodiments of a virtual tape server may automatically create a virtual tape device for an identified host such that hosts may interact with corresponding virtual tape devices. Thus, rather than having multiple hosts share a limited number of virtual... Agent: SprinkleIPLaw Group

20090119453 - Data reading method: According to an aspect of an embodiment, a method for controlling a controller connected to a plurality of storage units which are arranged in a redundant configuration, the controller reading data stored in the plurality of storage units in accordance with requests received from a host computer, the method comprising... Agent: Staas & Halsey LLP

20090119454 - Method and apparatus for video motion process optimization using a hierarchical cache: There are provided method and apparatus for video motion process optimization using a hierarchical cache. A storage method for a video motion process includes configuring a hierarchical cache to have one or more levels, each of the levels of the hierarchical cache corresponding to a respective one of a plurality... Agent: Robert D. Shedd Thomson Licensing LLC

20090119455 - Method for caching content data packages in caching nodes: e

20090119457 - Multithreaded clustered microarchitecture with dynamic back-end assignment: A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end... Agent: Kenyon & Kenyon LLP

20090119456 - Processor and memory control method: A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor... Agent: Mcneely Bodendorf LLP

20090119458 - Opportunistic block transmission with time constraints: A technique for determining a data window size allows a set of predicted blocks to be transmitted along with requested blocks. A stream enabled application executing in a virtual execution environment may use the blocks when needed.... Agent: Perkins Coie LLP

20090119459 - Late lock acquire mechanism for hardware lock elision (hle): A method and apparatus for a late lock acquire mechanism is herein described. In response to detecting a late-lock acquire event, such as expiration of a timer, a full cachet set, and an irrevocable event, a late-lock acquire may be initiated. Consecutive critical sections are stalled until a late-lock acquire... Agent: David P. Mcabee Intel Corporation

20090119460 - Storing portions of a data transfer descriptor in cached and uncached address space: Methods, apparatuses, and software for storing a first portion of a data transfer descriptor in cached address space, and storing a second portion of the data transfer descriptor in uncached address space. Also, methods, apparatuses, and software for reading at least a portion of a data transfer descriptor from cached... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20090119461 - Maintaining cache coherence using load-mark metadata: Embodiments of the present invention provide a system that maintains load-marks on cache lines. The system includes: (1) a cache which accommodates a set of cache lines, wherein each cache line includes metadata for load-marking the cache line, and (2) a local cache controller for the cache. Upon determining that... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090119462 - Repeated conflict acknowledgements in a cache coherency protocol: In a cache coherency protocol multiple conflict phases may be utilized to resolve a data request conflict condition. The multiple conflict phases may avoid buffering or stalling conflict resolution, which may reduce system inefficiencies.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090119463 - System and article of manufacture for dumping data in processing systems to a shared storage: Provided are a system and article of manufacture for dumping data in processing systems to a shared storage. A plurality of processing systems receive a signal indicating an event. Each of the processing systems write data used by the processing system to a shared storage device in response to receiving... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20090119465 - Dynamic loading of virtual volume data in a virtual tape server: Disclosed are a system, a method, and article of manufacture to provide for obtaining data storage device specific information from a data storage device using standard read/write commands. This method uses a host application to write a unique sequence of records to a logical volume of the data storage device.... Agent: International Business Machines Corporation

20090119464 - Memory chain: A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in... Agent: Tpl/interconnect Portfolio, LLC

20090119466 - Systems for providing performance monitoring in a memory system: Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090119467 - Storage system and storage subsystem: In the storage system, a storage apparatus includes a disk device for storing write data from a host computer as a primary volume and copied data of write data as a secondary volume, and a disk controller for collecting and managing status information of a plurality of copy pairs from... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090119469 - Procedure for time-limited storage of data on storage media: There is described a procedure for temporally limiting the storage of data on storage media, in which the data are provided with an expiry date when being stored on a storage medium. When access is made to these data by a read/write device, the expiry date is compared with a... Agent: Siemens Corporation Intellectual Property Department

20090119468 - Systems, methods, and apparatuses for erasing memory on wireless devices: A wireless device having a memory is provided. The memory or a protected portion of the memory is subject to a hard erasure of the memory vs. a soft erasure of the memory if a plurality of sensors indicate a threat to the device exists. The threat may be detected... Agent: Qualcomm Incorporated

20090119472 - Control circuit in a memory chip: Embodiments of the invention relate to a control circuit comprising a clock signal connection for receiving a system clock signal, a write signal connection for receiving a write signal, and a write control circuit for executing write commands, wherein the write control circuit is designed to start executing a write... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090119471 - Priority-based memory prefetcher: A method for preforming memory prefetching and scheduling prefetch commands inside the memory controller is disclosed. A set of prefetch commands is generated based on a stream of Read requests intended for a system memory, and the prefetch commands are stored in a low priority queue (LPQ). A set of... Agent: Dillon & Yudell LLP

20090119470 - Probabilistic method for performing memory prefetching: A method for preforming memory prefetching is disclosed. A stream length histogram (SLH) is initially generated based on a stream of Read and Write requests intended for a system memory. A determination is then made whether or not to issue a prefetch command after a Read request based on information... Agent: Dillon & Yudell LLP

20090119473 - Storage system: When a computer 10 receives a request from the client computer 30 to access snapshot files, the target device to be used is identified. The computer 10 makes a request to the identified target device TD for attachment of the logical device LDEV that stores the snapshot files for which... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090119474 - Partition redispatching using page tracking: Illustrated embodiments provide a computer implemented method and data processing system for redispatching a partition by tracking a set of memory pages, belonging to the dispatched partition. In one illustrative embodiment the computer implemented method comprises finding an effective page address to real page address mapping for a page address... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090119475 - Time based priority modulus for security challenges: Systems, methods, and computer readable media are disclosed for making dictionary based attacks difficult and/or time consuming for attackers. In one example embodiment, this can be accomplished by equipping a security service with software and/or circuitry operable to select security questions from different partitions of a question table.... Agent: Woodcock Washburn LLP (microsoft Corporation)

20090119476 - Data migration: Data is extracted from at least one data source. The data is translated according to a metadata model and is stored in a staging data store. A migration management user interface is provided that includes a mechanism for indicating at least some of the data to be included in a... Agent: Verizon Patent Management Group

20090119477 - Configurable translation lookaside buffer: The disclosure includes a method and system of configuring a translation lookaside buffer (TLB). In an embodiment, the TLB includes a first portion and a second portion. The first portion or the second portion may be selectively disabled in response to a value of a TLB configuration indicator.... Agent: Qualcomm Incorporated

20090119478 - Memory controller and method for multi-path address translation in non-uniform memory configurations: In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a first translated address. A full address translate of... Agent: Ibm Corporation

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