|Electrical computers and digital processing systems: memory patents - Monitor Patents|
USPTO Class 711 | Browse by Industry: Previous - Next | All
12/2008 | Recent | 08: Dec | Nov | Oct | Sp | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 07: D | N | O | S | A | J | J | M | A | M | F | J | | 06: 12 | 11 | 10 | 09 | 8 | 7 | 6 | 5 | 4 | Dec | Nov | | 2010 | 2009 |
Electrical computers and digital processing systems: memory December patents and inventions 12/08Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 12/25/2008 > patent applications in patent subcategories. patents and inventions
20080320203 - Memory management in a computing device: A computing device incorporating memory such as mobile SDRAM, which is capable of conserving energy by being operated in a low-power self-refresh mode, is enabled to identify those regions of memory which are allocated but inactive. These regions are collected into specific banks of memory so as to create banks... Agent: Fox Rothschild LLP
20080320204 - Memory system and method with flash memory device: A memory system is provided which includes a host, a flash memory device, and a dual port memory which exchanges data with the host and the flash memory device. The flash memory device utilizes a portion of the dual port memory as a working memory.... Agent: Volentine & Whitt PLLC
20080320205 - Long-term digital data storage: Embodiments are directed to recording digital data on an optically ablatable digital storage media. In one embodiment, a device configured to ablate portions of ablatable material on an optically ablatable digital storage media receives digital data that is to be recorded on a recording layer of an optically ablatable digital... Agent: Workman Nydegger 1000 Eagle Gate Tower
20080320212 - Control device and control method of nonvolatile memory and storage device: According to one embodiment, the control device according to an embodiment of the present invention, facilitates and speeds up averaging processing of the number of erases of a physical block (exchange processing of a physical block) of a nonvolatile memory. The device includes a file system control section that analyzes... Agent: Pillsbury Winthrop Shaw Pittman, LLP
20080320213 - Control device of nonvolatile memory and control method thereof, and storage device: According to one embodiment, the overall information processing time can be shortened. There are provided (1) a logical/physical block address conversion table information section that associates a logical block address of a logical address space with a physical block address of a nonvolatile memory device, (2) a physical block use... Agent: Pillsbury Winthrop Shaw Pittman, LLP
20080320210 - Data management systems, methods and computer program products using a phase-change random access memory for selective data maintenance: A data management system includes a data processor configured to provide a file system module configured to store first data in a flash memory in block units and a filter layer module configured to receive second data from the file system module and to store the second data in a... Agent: Myers Bigel Sibley & Sajovec
20080320209 - High performance and endurance non-volatile memory based storage systems: High performance and endurance non-volatile memory (NVM) based storage systems are disclosed. According to one aspect of the present invention, a NVM based storage system comprises at least one intelligent NVM device. Each intelligent NVM device includes a control interface logic and NVM. Logical-to-physical address conversion is performed within the... Agent: Roger H. Chu
20080320207 - Multi-level cell (mlc) dual personality extended fiber optic flash memory device: A multi-level cell (MLC) dual-personality extended fiber optic flash drive includes a MLC dual-personality extended fiber optic Universal Serial Bus (USB) plug connector connected to a dual-personality extended fiber optic flash drive and being removably connectable to a host. The connector is adaptable to receive electrical data and optical data.... Agent: Law Offices Of Imam
20080320214 - Multi-level controller with smart storage transfer manager for interleaving multiple single-chip flash memory devices: A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in... Agent: Stuart T Auvinen
20080320206 - Nonvolatile memory card and configuration conversion adapter: A nonvolatile memory card, including interface parts for plural kinds of memory cards; interface controllers corresponding to the interface parts for corresponding memory cards; and a switch configured to select a single one of the interface controllers.... Agent: Dickstein Shapiro LLP
20080320211 - Nonvolatile memory control device, nonvolatile memory control method, and storage device: According to an embodiment of the present invention is to increase the number of arbitrarily available physical blocks in a nonvolatile memory device. The device comprises a file system control section which analyzes a file allocation table (FAT) to identify an unused logical block, a logical/physical block address conversion table... Agent: Pillsbury Winthrop Shaw Pittman, LLP
20080320208 - Semiconductor device and method for controlling thereof: A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of... Agent: Ingrassia Fisher & Lorenz, P.C.
20080320215 - Semiconductor memory device and method for operating semiconductor memory device: A semiconductor memory device includes a memory array section configured to serve as an information storage area and an interface section configured to interface between an external memory controller and the memory array section, the memory array section and the interface section being sealed in a package. The interface section... Agent: Rader Fishman & Grauer PLLC
20080320216 - Translation lookaside buffer and related method and program product utilized for virtual addresses: A program product, a translation lookaside buffer and a related method for operating the TLB is provided. The method comprises the steps of: a) when adding an entry for a virtual address to said TLB testing whether the attribute data of said virtual address is already stored in said CAM... Agent: International Business Machines Corporation
20080320217 - Executing i/o requests for a disk drive: Executing I/O requests for a disk drive including receiving, by a device driver from a volume manager, a plurality of I/O requests; retrieving, from non-volatile memory by the device driver, information describing access times for storage locations on the disk drive; and executing, by the device driver, the I/O requests... Agent: International Corp (blf)
20080320219 - Computer and method for configuring data backup environment used by plurality of associatively operated applications: The present invention stores application management information indicating respective applications constituting a federated application environment, which is a group constituted by a plurality of associatively operated applications. By referencing this application management information, a plurality of applications constituting this federated application environment are specified. A plurality of first logical volumes... Agent: Antonelli, Terry, Stout & Kraus, LLP
20080320218 - Disk array apparatus and control method for disk array apparatus: Resources of a storage apparatus are utilized effectively by increasing and reducing a capacity of a differential LU used in a snapshot. In a disk array apparatus including a control processor which controls reading and writing of data with respect to a first logical volume which is generated using storage... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080320221 - Storage system and storage control method comprising router and switch communication with raid modules: A storage system comprises a router, which receives and transfers commands; a plurality of RAID modules; and a switch, which receives commands from the router and transmits the commands to any of the plurality of RAID modules. Each RAID module comprises a plurality of media drives, a RAID group is... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080320220 - Storage system, data transfer method, and program: The storage system includes: a first disk array apparatus for providing first volumes for storing data sent from a host system; a second disk array apparatus for providing second volumes for storing back-up data of the first volumes; and a console terminal for operating the first disk array apparatus. The... Agent: Stanley P. Fisher Reed Smith LLP
20080320222 - Adaptive caching in broadcast networks: Adaptive caching techniques are described. In an implementation, a head end defines a plurality of cache periods having associated criteria. Request data for content is obtained and utilized to associate the content with the defined cache periods based on a comparison of the request data with the associated criteria. Then,... Agent: Microsoft Corporation
20080320223 - Cache controller and cache control method: A cache controller that writes data to a cache memory, includes a first buffer unit that retains data flowing in from outside to be written to the cache memory, a second buffer unit that retains a data piece to be currently written to the cache memory, among pieces of the... Agent: Staas & Halsey LLP
20080320224 - Multiprocessor system, processor, and cache control method: A multiprocessor system includes processors each having a primary cache and a secondary cache shared by the processors. The processors each include a read unit that reads data from the primary cache, a request unit that makes a write request when the data to be read is not stored in... Agent: Staas & Halsey LLP
20080320225 - Systems and methods for caching and serving dynamic content: A web server and a shared caching server are described for serving dynamic content to users of at least two different types, where the different types of users receive different versions of the dynamic content. A version of the dynamic content includes a validation header, such as an ETag, that... Agent: Knobbe Martens Olson & Bear LLP
20080320226 - Apparatus and method for improved data persistence within a multi-node system: Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining... Agent: International Business Machines Corporation
20080320227 - Cache memory device and cache memory control method: A cache memory device that includes a cache which stores data and tag information specifying an address of stored data, includes a detection unit that detects an error by reading out the tag information when a writing/readout request of desired data occurs to the cache, a search unit that searches... Agent: Staas & Halsey LLP
20080320228 - Method and apparatus for efficient replacement algorithm for pre-fetcher oriented data cache: Disclosed are a method and apparatus for replacing pre-fetched data in a pre-fetch cache. In one embodiment, each line of the pre-fetch cache will be accessed at most M times. A line accessed M times can be evicted from the cache without any performance loss. In this embodiment, a counter... Agent: Scully, Scott, Murphy & Presser, P.C.
20080320229 - Pre-fetch control apparatus: A pre-fetch control apparatus is equipped with a next-line pre-fetch control apparatus 38. An address overflowed from a pre-fetch address queue 26 is stored in the next-line pre-fetch control apparatus 38. An access address issued by a processor unit and stored in a register 25 is compared with the address... Agent: Staas & Halsey LLP
20080320230 - Avoiding livelock using a cache manager in multiple core processors: Livelocks are prevented in multiple core processors by verifying that a data access request is still valid before sending messages to processor cores that may cause other data access requests to fail. A cache coherency manager receives data access requests from multiple processor cores. Upon receiving a data access request... Agent: Mips- Law Office Of Jonathan Hollander PC
20080320231 - Avoiding livelock using intervention messages in multiple core processors: Livelocks are prevented in multiple core processors by canceling data access requests upon determining that they conflict with other data access requests. A requesting processor core sends a data access request potentially causing livelock to a cache coherency manager. A cache coherency manager receives data access requests from multiple processor.... Agent: Mips- Law Office Of Jonathan Hollander PC
20080320234 - Information processing apparatus and data transfer method: One aspect of the embodiments utilizes an information processing apparatus having a plurality of system boards connected via a bus, each system board including a CPU having a cache memory, a main memory that forms a shared memory, and a system controller that manages the CPU and the main memory... Agent: Staas & Halsey LLP
20080320232 - Preventing writeback race in multiple core processors: A processor prevents writeback race condition errors by maintaining responsibility for data until the writeback request is confirmed by an intervention message from a cache coherency manager. If a request for the same data arrives before the intervention message, the processor core unit provides the requested data and cancels the... Agent: Mips- Law Office Of Jonathan Hollander PC
20080320233 - Reduced handling of writeback data: The complexity of the logic of the cache coherency manager unit is reduced by leveraging the data path for intervention messages and responses to carry data associated with writeback requests. A processor core unit sends a writeback request to the cache coherency manager unit. The request does not include the... Agent: Mips- Law Office Of Jonathan Hollander PC
20080320235 - Processor cache management with software input via an intermediary: Software assists a processor subsystem in making cache replacement decisions by providing an intermediary with information regarding how instructions and/or data of a working set are expected to be used and accessed by the software. The intermediary uses this information along with its knowledge of system requirements, policy and the... Agent: Microsoft Corporation
20080320238 - Snoop control method and information processing apparatus: One aspect of the embodiments utilizes a system controller which has a broadcast transmitting and receiving unit that receives a memory access request from each of CPU and notifies to the other system controllers and a snoop control unit that judges when the memory access request from any of the... Agent: Staas & Halsey LLP
20080320237 - System controller and cache control method: A multiprocessor system comprises a plurality of system controllers, each of which performs a snoop processing regarding a cache device in its charge. The system controllers adjust the number of steps of a snoop pipeline for the snoop processing according to communication time with the other system controllers. The number-of-steps... Agent: Staas & Halsey LLP
20080320236 - System having cache snoop interface independent of system bus interface: A system includes processor units, caches, memory shared by the processor units, a system bus interface, and a cache snoop interfaces. Each processor unit has one of the caches. The system bus interface communicatively connects the processor units to the memory via at least the caches, and is a non-cache... Agent: Law Offices Of Michael Dryja
20080320239 - Data storage system: A data storage system is provided. The data storage system includes a first storage module for storing a first data, a second storage module for storing a second data, a control module and a processing module. The control module generates a first control signal and a second control signal, and... Agent: Joe Mckinney Muncy
20080320241 - Data storage device performance optimization methods and apparatuses: Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed. Method embodiments generally comprise identifying one or more isochronous requests among a plurality of requests which may be issued to a data storage device, assigning a completion deadline... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Intellevate, LLC
20080320240 - Method and arrangements for memory access: In one embodiment a multi-input, multi output memory system is disclosed. The system can include a plurality of single ported memory modules, an identifier module to provide an identify to each memory access requests of a plurality of memory access requests. The identity can include a port that receives the... Agent: Alan Carlson
20080320243 - Memory-sharing system device: A memory-sharing system device has a shared memory, divided into forward-direction and backward-direction memory areas; a first processor inputting transfer data in the forward direction, writing the data to the forward-direction memory area, reading transfer data in the backward direction from the backward-direction memory area and outputting the data; and... Agent: Arent Fox LLP
20080320244 - Moving records between partitions: In an embodiment, data is partitioned into partitions, which are divided into levels. The levels are ordered by creation times of the levels. A request is received at a current partition, which includes a key that identifies a field in a record and a value for the key. A determination... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20080320242 - Physical memory capping for use in virtualization: A method of implementing virtualization involves an improved approach to resource management. A virtualizing subsystem is capable of creating separate environments that logically isolate applications from each other. Some of the separate environments share physical resources including physical memory. When a separate environment is configured, properties for the separate environment... Agent: Brooks Kushman P.C. / Sun / Stk
20080320248 - Computer system architecture and operating method for the operating system thereof: In order to develop a mobile operating system for a computer, first the mobile operating system must be independent from the computer hardware device. Therefore, the present invention discloses a new computer system architecture which loads a Transient Resident Operating System (TROS) from an external device and provides a predefined... Agent: Troxell Law Office PLLC
20080320249 - Fully buffered dimm read data substitution for write acknowledgement: A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.... Agent: Marger Johnson & Mccollom, P.C.
20080320251 - Method and system for centralized memory management in wireless terminal devices: Methods and systems for controlling centralized memory management in wireless terminal devices. Memory management scripts associated with a wireless application are stored in a registry accessible through a data network for on-demand download and execution. A memory management kernel in each terminal device monitors a memory utilization of the terminal... Agent: Smart & Biggar P.o. Box 2999, Station D
20080320245 - Method for writing data of an atomic transaction to a memory device: A method for writing data to a memory device is disclosed. In one embodiment, data of an atomic transaction is written to a first memory in a memory device. A determination is made regarding whether all of the data of the atomic transaction was written to the first memory. The... Agent: Brinks Hofer Gilson & Lione/sandisk
20080320246 - Methods and apparatus for compiling instructions for a data processor: Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach... Agent: Ropes & Gray LLP
20080320247 - Processor and interface: A data processing apparatus comprises a processor constructed to operate under control of a sequence of program instructions selected from a predetermined instruction set; master circuitry to request access to storage locations of the processor; an interface circuit to provide an interface for an external apparatus to signal a request... Agent: Schwegman, Lundberg & Woessner, P.A.
20080320250 - Wirelessly configurable memory device: A configurable memory includes an interface section, a plurality of memory modules, and an internal configuration section. The interface section includes a millimeter wave (MMW) transceiver and interfaces with one or more external components. Each the plurality of memory modules includes a memory MMW transceiver and a plurality of memory... Agent: Garlick Harrison & Markison
20080320253 - Memory device with circuitry for writing data of an atomic transaction: A memory device with circuitry for writing data of an atomic transaction is disclosed. In one embodiment, data of an atomic transaction is written to a first memory in a memory device. A determination is made regarding whether all of the data of the atomic transaction was written to the... Agent: Brinks Hofer Gilson & Lione/sandisk
20080320252 - Optimized and robust in-place data transformation: In-place data transformations are performed on file data by moving data blocks from a source file into a temporary file and then from the temporary file into a destination file each time in a back to front fashion enabling truncation of the source file while the temporary file is being... Agent: Merchant & Gould (microsoft)
20080320255 - Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets: An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the... Agent: Rutan & Tucker, LLP.
20080320254 - Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary: A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single... Agent: Rutan & Tucker, LLP.
20080320256 - Lru control apparatus, lru control method, and computer program product: To reduce the number of bits required for LRU control when the number of target entries is large, and achieve complete LRU control. Each time an entry is used, an ID of the used entry is stored to configure LRU information so that storage data 0 stored in the leftmost... Agent: Staas & Halsey LLP
20080320257 - Network message logging and archival: A method includes receiving a message to be logged. The message is written to a stream corresponding to an active archive, wherein the active archive comprises compressed messages. The message is also written to an active log without compression.... Agent: Hewlett Packard Company
20080320261 - Coordinated storage management operations in replication environment: A method, system, computer system, and computer-readable medium for maintaining up-to-date, consistent copies of primary data without the need to replicate modified data when the data were modified as a result of an operation that is not an application-driven write operation captured during replication. Selected storage management operations are performed... Agent: Campbell Stephenson LLP
20080320260 - Data synchronization of multiple remote storage after remote copy suspension: A method and apparatus are provided for enhancing the performance of storage systems to allow recovery after all types of suspensions in remote copy operations. Data is synchronized after an interruption in transfer between a first storage volume of a primary storage system and a first storage volume of a... Agent: Townsend And Townsend And Crew, LLP
20080320259 - Method for providing fault tolerance to multiple servers: A method for providing fault tolerance to multiple computer servers is disclosed. Basically, t backup computer servers are utilized to back up data from multiple active computer servers such that up to t faults can be tolerated. Data from the active computer servers are categorized under their respective data structure... Agent: Dillon & Yudell LLP
20080320258 - Snapshot reset method and apparatus: A method, device, and system for resetting snapshots are provided. The reset of a snapshot incorporates the traditional snapshot delete and snapshot create operations into a single operation. Additionally, a snapshot created under the reset operation may receive an array partition from a snapshot being deleted under the same snapshot... Agent: Sheridan Ross PC
20080320262 - Read/write lock with reduced reader lock sampling overhead in absence of writer lock acquisition: An improved reader-writer locking for synchronizing access to shared data. When writing the shared data, a writer flag is set and a lock is acquired on the shared data. The shared data may be accessed following the expiration of a grace period and a determination that there are no data... Agent: Walter W. Duft
20080320264 - Chip card protected against copying and method for production thereof: A chip card is protected against copying by having a data memory for storage of data that are protected, at least in a sub-region of the data memory, against alteration by users or attackers outside of a privileged group. Members of this group can write an individual identifier for this... Agent: Schiff Hardin, LLP Patent Department
20080320263 - Method, system, and apparatus for encrypting, integrity, and anti-replay protecting data in non-volatile memory in a fault tolerant manner: According to some embodiments, a method for providing encryption, integrity, and anti-replay protection of data in a fault tolerant manner is disclosed. A data blob and an anti-replay table blob are copied to a temporary storage region in a non-volatile memory. In an atomic operation, a status indicator is set... Agent: Intel Corporation C/o Intellevate, LLC
20080320265 - System for providing a slow command decode over an untrained high-speed interface: A memory system for providing a slow command decode over an untrained high-speed interface. The memory system includes a memory system having a memory interface device, an untrained high-speed interface, and a memory controller. The untrained high-speed interface is in communication with the memory interface device. The memory controller generates... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20080320266 - Allocating disk space on a disk drive: Allocating disk space on a disk drive, the disk drive controlled by a device driver and a volume manager, including receiving in the volume manager a request to allocate disk space for semi-sequential data access of structured data; retrieving, from non-volatile memory by the volume manager, information describing access times... Agent: International Corp (blf)
20080320267 - Memory element, data processing system, method for setting operating parameters of a memory and computer program: A memory element includes a memory which is operable according to operating parameters from at least two sets of operating parameter values and an operating parameter control which is implemented to receive operating state information and to select a set of operating parameter values for the operation of the memory... Agent: Slater & Matsil, L.L.P.
20080320268 - Interconnect implementing internal controls: In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory... Agent: Rutan & Tucker, LLP.
20080320269 - Method and apparatus for ranking of target server partitions for virtual server mobility operations: A computer implemented method, data processing system, and computer program product for automated ranking of target server partitions based on current workload partition performance state. When a violation of a stack tier policy for the virtualized process collection in a source logical partition is detected, the stack tier comprising the... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20080320270 - Data read-and-write controlling device: In a data read-and-write controlling device, without waiting for confirmation that data is written in a RAM, data is written in a WER and an ADR, and at the same time, address information of the data is written in the RAM write-information table. That is, the data read-and-write controlling device... Agent: Staas & Halsey LLP
20080320271 - Hashing and serial decoding techniques: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number... Agent: Connolly Bove Lodge & Hutz LLP12/18/2008 > patent applications in patent subcategories. patents and inventions
20080313383 - Processor for virtual machines and method therefor: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively... Agent: Townsend And Townsend And Crew, LLP
20080313384 - Method and device for separating the processing of program code in a computer system having at least two execution units: A method and a device are provided for separating the processing of program code in a computer system having at least two execution units, in which method and device switching over takes place between at least two operating modes, and a first operating mode corresponds to a comparison mode and... Agent: Kenyon & Kenyon LLP
20080313385 - Process for contiguously streaming data from a content addressed storage system: What is disclosed is process for backing data objects from a content addressed storage system to a tape storage device such that the data objects are written in a contiguous sequential fashion. Data objects are kept together on the storage medium, rather than fragmented. An embodiment of the present invention... Agent: Emc Outside Counsel Dergosits & Noah LLP
20080313386 - Memory control apparatus and memory control method: A memory control apparatus and a memory control method are provided to enable an effective utilization of buffer memory in a system LSI by comprising buffer memory for temporarily storing data stored in memory, and comprising the processes of: receiving an instruction to the memory; transmitting a buffer memory security-dedicated... Agent: Staas & Halsey LLP
20080313392 - Data controlled power supply apparatus: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero”... Agent: Dickstein Shapiro LLP
20080313388 - Electronic data flash card with various flash memory cells: An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash... Agent: Blakely Sokoloff Taylor & Zafman LLP
20080313389 - Electronic data flash card with various flash memory cells: An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash... Agent: Blakely Sokoloff Taylor & Zafman LLP
20080313390 - Method and system for presenting an executing status of a memory card: A system and a method for presenting an executing status of a memory card are provided. The system comprises a processing apparatus and an access device. The processing apparatus stores an application program having a plurality of icons. The access device connects the memory card and the processing apparatus. The... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC
20080313391 - Semiconductor memory device and semiconductor device: A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of... Agent: Mcdermott Will & Emery LLP
20080313387 - Semiconductor memory device capable of reading data reliably: A control unit reads data from a plurality of memory cells connected to one of the word lines in a read operation at a first level CR generated by a voltage generator circuit and in a read operation at a second level CR−x and finds the number of cells included... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20080313393 - Device for writing data into memory: A device for writing data into a memory and a method thereof. The memory comprises a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The data are divided into a plurality of segments. The segments are written into first memory cells of the... Agent: Joe Mckinney Muncy
20080313394 - Motherboard and memory device thereof: A memory device can be directly mounted on a motherboard supporting DDR3 SDRAM, and then the memory device have advantages of the fly-by bus topology and the T branch topology established by the joint electron device engineering council (JEDEC). Thus, the system performance of a desktop computer in a unit... Agent: Jianq Chyun Intellectual Property Office
20080313395 - Apparatus and method to manage information using an optical and holographic data storage medium: A hybrid optical and holographic data storage medium is disclosed. In addition, a method is disclosed to manage information using that optical and holographic data storage medium. The method reads information from the optical data storage layer before reading data from, or writing data to, the holographic data storage layer.... Agent: Dale F. Regelman Quarles & Brady, LLP
20080313396 - System and method of monitoring data storage activity: Systems and methods of monitoring logical block address (LBA) activity are disclosed. In an embodiment, a pattern of a data storage device may be monitored. An LBA may be detected that is accessed based on the pattern. The LBA may be added to a list of LBAs stored in a... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.
20080313397 - Optimization of storage device accesses in raid systems: A result value, such as a parity value, for a set of corresponding data elements from a plurality of storage devices is determined using a commutative operation. When accessing the set of corresponding data elements from a plurality of storage devices, a dual access can be performed for the storage... Agent: Larson Newman Abel Polansky & White, LLP
20080313399 - Storage control system and method: A disk array system including a plurality of disk drives, including: a plurality of first-type disk drives being used to form a first-type logical unit having a plurality of a first-type of chunks; a plurality of second-type disk drives being used to form a second-type logical unit having a plurality... Agent: Antonelli, Terry, Stout & Kraus, LLP
20080313398 - Storage system that executes performance optimization that maintains redundancy: One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device withal lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080313400 - Data accessing system, controller and storage device having the same, and operation method thereof: A data accessing system for interfacing between a smart card and a non-volatile memory is provided. The non-volatile memory has a smart card exclusive area accessible to a plurality of smart card applications. The smart card exclusive area includes a plurality of record unit sets respectively having a plurality of... Agent: J C Patents, Inc.
20080313401 - Device for processing information and working method thereof: A device for processing information and the working method of the same are provided. The device for processing information comprises: a memory in which logic for driving a firmware is stored; a connector for connecting the memory to an external device; and a control unit for providing an interface with... Agent: Birch Stewart Kolasch & Birch
20080313402 - Virtual personal video recorder: The claimed subject matter provides a system and/or method that manages media content. The disclosed system includes a component that synchronizes with a multimedia player that is in communication with the component. The component upon synchronization automatically determines an amount of storage space available on the handheld device and based... Agent: Amin, Turocy & Calvin, LLP
20080313403 - Apparatus, system, and method for selecting an input/output tape volume cache: An apparatus, system, and method are disclosed for selecting an input/output tape volume cache (TVC). A history module maintains access history instances for a plurality of clusters. A request module receives an access request for a logical volume. An adjustment module weights the access history instances in favor of recent... Agent: Kunzler & Mckenzie
20080313405 - Coherency maintaining device and coherency maintaining method: A second-level cache device stores part of registration information of data for a first-level cache device in a second-level cache-tag unit in association with registration information in a second-level-cache data unit, and stores the registration information of data for the first-level cache device in a first-level cache-tag copying unit. A... Agent: Staas & Halsey LLP
20080313404 - Multiprocessor system and operating method of multiprocessor system: According to one aspect of embodiments, a multiprocessor system includes a cache memory corresponding to each of the processors, a hierarchy setting register in which the hierarchical level of each cache memory is set, an access control unit that controls access between each cache memory. The hierarchical level of the... Agent: Arent Fox LLP
20080313406 - Methods and systems for porting sysprof: Embodiments of the present invention provide a system profiler that can be used on any processor architecture. In particular, instead of copying an entire stack every time, the stack is divided into blocks of a fixed size. For each block, a hash value is computed. As stack blocks are sent... Agent: Mh2 Technology Law Group (cust. No. W/red Hat)
20080313407 - Latency-aware replacement system and method for cache memories: A method for replacing cache lines in a computer system having a non-uniform set associative cache memory is disclosed. The method incorporates access latency as an additional factor into the existing ranking guidelines for replacement of a line, the higher the rank of the line the sooner that it is... Agent: James J. Bitetto, Esq. Keusey, Tutunjian & Bitetto, P.C.
20080313408 - Low latency memory access and synchronization: A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing... Agent: Scully, Scott, Murphy & Presser, P.C.
20080313409 - Separating device and separating method: In a separating device that separates a processor configured to perform process by using data recorded in a cache memory connected to the processor, a stopping unit, upon receiving a processor separation request, stops the processor from performing a new process; and a separation executing unit, upon completion of process... Agent: Staas & Halsey LLP
20080313410 - Promoting a line from shared to exclusive in a cache: Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC
20080313411 - System controller and cache control method: A processor module having a cache device and a system controller having a copy TAG2 of a tag of the cache device configure a system to which a protocol representing the states of a data block of the cache device by six states, that is, an invalid state I, a... Agent: Staas & Halsey LLP
20080313412 - Data control apparatus, data control method, and data control program: A data control apparatus is connected to a central processing unit that processes data and to a main storage unit that stores therein the data, and controls output of the data. The data control apparatus includes a data storage unit that stores therein data output from the central processing unit... Agent: Staas & Halsey LLP
20080313415 - Copied file execution authorization using rfid tag: In a method for controlling execution of a digital copy of an original file, a radio frequency identification (RFID) tag read operation is performed using an RFID tag reader. A determination is then made as to whether the physical storage medium is present or absent based on the RFID tag... Agent: Westman Champlin (microsoft Corporation)
20080313414 - Execution of point-in-time copy operations in continuous mirroring environments: Provided are a method, system, and article of manufacture wherein a point-in-time copy operation command for a point-in-time copy of a point-in-time source volume to a point-in-time target volume is received while performing continuous copy operations from continuous copy source volumes to continuous copy target volumes. A determination is made... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37
20080313413 - Method and device for insuring consistent memory contents in redundant memory units: In a telecommunications or data processing system having at least one active control unit and at least one redundant passive control unit that are respectively provided with at least one memory unit, the following operations are performed: (a) a mirroring routine is invoked when a virtual memory region in a... Agent: Staas & Halsey LLP
20080313416 - Method, system and program for storing and using metadata in multiple storage locations: Provided are a method, system, and program for storing and using metadata in multiple storage location. Signature data is stored in a system storage indicating a plurality of metadata copy locations, each locating identifying a storage device and a copy location within the storage device. Each location contains one copy... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37
20080313417 - Apparatus and method of detecting and controlling privilege level violation process: Provided are an apparatus and method of detecting and controlling a privilege level violation process. The apparatus monitors whether higher-privileged processes depend on information provided from lower-privileged objects or denies the higher-privileged processes to access the lower-privileged objects. The apparatus is provided in a process, and monitors whether a process... Agent: Ladas & Parry LLP
20080313418 - Semiconductor memory device having processor reset function and reset control method thereof: A semiconductor memory device for use in a multiprocessor system includes a shared memory area and a reset signal generator. The shared memory area is accessible by the processors of the multiprocessor system through different ports, and is assigned to a portion of a memory cell array. The reset signal... Agent: Volentine & Whitt PLLC
20080313419 - Method and system for buffering data file to buffer memory: This invention provides a method and a system to read and buffer an audio data file from an optical storage medium into a buffer memory. The data file comprises blocks sequentially stored in the medium. Each block comprises a subcode block with encoded subcodes and a corresponding main data block... Agent: Patterson & Sheridan, LLP - - - Iptec
20080313420 - Managing working set use of a cache via page coloring: A processor cache is indexed by a group of distinct page colors. The use of this cache by different working sets is controlled using page coloring. Translations of virtual addresses of the instructions and/or data of a working set are constrained to physical addresses the page colors of which are... Agent: Microsoft Corporation12/11/2008 > patent applications in patent subcategories. patents and inventions
20080307152 - Memory module, memory controller, nonvolatile storage, nonvolatile storage system, and memory read/write method: In a storage having a nonvolatile RAM of destructive read type, the number of restorations attributed to data read from the nonvolatile RAM is decreased, and the overall life of the storage is prolonged. In a storage having a nonvolatile RAM of destructive read type and a volatile RAM and... Agent: Greenblum & Bernstein, P.L.C
20080307153 - Method and device for reorganizing data in a memory system, in particular for control devices in motor vehicles: A method for reorganizing performance quantity data in a segment of a non-volatile memory. The method encompasses the tasks or operations of generating a cohesive data block at an address space of a working memory, of performance quantity data from a first segment of the non-volatile memory and/or from the... Agent: Kenyon & Kenyon LLP
20080307158 - Method and apparatus for providing data type and host file information to a mass storage system: A method and system for providing advance data type information to a mass storage system is disclosed. The method may include a host system providing host file information, such as a host file identifier and/or a data type, to a memory system in addition to LBA format data. The system... Agent: Brinks Hofer Gilson & Lione/sandisk
20080307159 - Method and control device for operating a non-volatile memory, in particular for use in motor vehicles: A method for the consecutive writing of performance quantity data to a non-volatile memory, in particular in a control device in a motor vehicle. The method encompasses the operations of determining a write address, which defines an address space for the writing of a performance quantity datum to be written,... Agent: Kenyon & Kenyon LLP
20080307157 - Method and system for updating firmware of microcontroller: A system for updating firmware of a microcontroller includes a serial peripheral interface (SPI), an inter integrated Circuit (I2C or IIC) and a universal serial bus (USB) for the flexibility of using these interfaces. And, a method for updating firmware of a microcontroller is also provided to utilize each interface... Agent: Rosenberg, Klein & Lee
20080307155 - Method of interfacing a host operating through a logical address space with a direct file storage medium: A method and system for interfacing a system operating through a logical address space with a direct file storage (DFS) medium is disclosed. The method includes receiving data associated with addresses in a logical block address (LBA) format from a host system and generating file objects manageable by the DFS... Agent: Brinks Hofer Gilson & Lione/sandisk
20080307154 - System and method for dual-ported i2c flash memory: A method for emulating a dual-port I2C device includes monitoring a bus for I2C traffic. A system receives an I2C interrupt on the bus. The system determines whether the received I2C interrupt is one of either a hardware interrupt or a software interrupt. In the event the received I2C interrupt... Agent: Ibm Corporation (pec) C/o Patrick E. Caldwell, Esq.
20080307156 - System for interfacing a host operating through a logical address space with a direct file storage medium: A method and system for interfacing a system operating through a logical address space with a direct file storage (DFS) medium is disclosed. The method includes receiving data associated with addresses in a logical block address (LBA) format from a host system and generating file objects manageable by the DFS... Agent: Brinks Hofer Gilson & Lione/sandisk
20080307160 - Methods and structure for improved storage system performance with write-back caching for disk drives: Methods and associated structures for utilizing write-back cache management modes for local cache memory of disk drives coupled to a storage controller while maintaining data integrity of the data transferred to the local cache memories of affected disk drives. In one aspect hereof, a state machine model of managing cache... Agent: Lsi Corporation
20080307161 - Method for accessing target disk, system for expanding disk capacity and disk array: The present invention discloses a method for accessing a target disk and a system for expanding disk capacity. A processing unit of a master disk array sends a command or data to a PCIe switching unit of the master disk array upon receipt of the command or data; the PCIe... Agent: Ladas & Parry LLP
20080307162 - Preload controller, preload control method for controlling preload of data by processor to temporary memory, and program: A preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the readout data to a temporary memory, including a first acquiring device to acquire access hint information which represents a data access interval to the main memory, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20080307163 - Method for accessing memory: A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2n bits, n is a positive integer. The method for accessing memory includes the following steps: Firstly, threshold voltages of the storage are defined into 2n level respectively,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20080307165 - Information processor, method for controlling cache flash, and information processing controller: An information processor, a method for controlling cache flush, and an information processing controller that increases the data processing speed by efficiently performing cache flushing on a cache memory. A CPU includes a load/store unit and a flush control unit. The CPU controls data stored in a cache through a... Agent: Freescale Semiconductor, Inc. Law Department
20080307164 - Method and system for memory block flushing: A method and system for flushing physical memory blocks in a memory device is disclosed. The method includes detecting a quantity of available memory, background flushing partially obsolete memory blocks if the quantity decreases to a background activation threshold, disabling the background flushing if the quantity increases to a background... Agent: Brinks Hofer Gilson & Lione/sandisk
20080307166 - Store handling in a processor: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or... Agent: Mhkkg, PC/apple, Inc.
20080307167 - Converting victim writeback to a fill: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or... Agent: Mhkkg, PC/apple, Inc.
20080307168 - Latency reduction for cache coherent bus-based cache: In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a... Agent: Mhkkg, PC/apple, Inc.
20080307169 - Method, apparatus, system and program product supporting improved access latency for a sectored directory: A data processing system includes a coherence directory having a prefetch sector cache and a memory directory array containing a plurality of sectored entries. According to one method, in response to receiving a first directory lookup request specifying a first target address, an entry associated with the target address is... Agent: Ibm Corporation
20080307170 - Memory module and memory system: A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different rank pin signals to... Agent: Baker & Mckenzie LLP Patent Department
20080307171 - System and method for intrusion protection of network storage: Protection mechanism is provided for data stored in logical volumes, especially during the time the corresponding host computer is off line. Additionally, integrity check mechanism is provided for logical volume when the host computer is started, so that host computer can detect unauthorized access to its assigned logical volume during... Agent: Sughrue Mion, PLLC
20080307172 - System and method for reproducing memory error: An information processing apparatus includes a nonvolatile memory area having a storage area, and a main controller configured to store an access pattern to a main memory in the nonvolatile memory area, to end the storage of the access pattern when an error is detected in the main memory, and... Agent: Nec Corporation Of America
20080307173 - Efficient encoding for detecting load dependency on store with misalignment: In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask,... Agent: Mhkkg, PC/apple, Inc.
20080307174 - Dual use memory management library: A dual-use library that is able to handle calls from programs requiring either reference count or garbage collected memory management is described. This capability may be provided by introducing a new assignment routine, assign( ), and instrumenting the reference count routines responsible for updating an object's reference count—e.g., addReference( )... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri LLP
20080307178 - Data migration: The present invention provides for a method for managing the storage of data in a computing system that includes a data processor and local physical storage, involving the steps of: defining a virtual storage volume for access by the data processor, the data processor including a local storage pool mapped... Agent: Oppenheimer, Wolff & Donnelly, LLP
20080307177 - Program conversion device: An analysis section analyzes the live range of a first variable shared among subroutines and the live range of a second variable used only in a subroutine. The allocation section allocates the second variable in an allocation memory for the first variable if the live ranges of the first and... Agent: Mcdermott Will & Emery LLP
20080307179 - Shared data mirroring apparatus, method, and system: A network component useful in tracking write activity by writing logs containing write address information is described. The tracking component may be used in networked systems employing data mirrors to record data block addresses written to a primary storage volume during the time a data mirror is unavailable. The tracking... Agent: Kunzler & Mckenzie
20080307176 - Storage system and setting method for storage configuration information: Pairs are formed from a plurality of dispersed volumes and copying between the volumes is conducted by a series of remote operations from a management server. A management server 10 instructs the generation of configuration setting files 23, 30 to host computers 20, 30 selected so as to form copy... Agent: Townsend And Townsend And Crew, LLP
20080307175 - System setup for electronic backup: Systems and methods are provided for storing and restoring digital data. In some implementations, a method is provided. The method includes detecting a remote storage device, prompting the user to use the detected remote storage device for backup operations, receiving a user input to use the detected remote storage device... Agent: Fish & Richardson P.C.
20080307180 - Virtual machine control program and virtual machine system: The program attains compatibility of suppression of an overhead accompanying page exception handling in the case of operating a program whose amount of memory use is large on a virtual machine and suppression of the overhead accompanying page exception handling in the case of operating a first OS that has... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080307181 - Disk-resident streaming dictionary: A method, apparatus and computer program product for storing data in a disk storage system is presented. A dictionary data structure is defined and stored on the disk storage system. Key-value pairs can be inserted and deleted into the dictionary data structure, with full transactional semantics, at a rate that... Agent: Barry W. Chapin, Esq. Chapin Intellectual Property Law, LLC
20080307182 - Efficient and flexible memory copy operation: A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l.
20080307185 - Apparatus and method to set signal compensation settings for a data storage device: A method is disclosed to set signal compensation settings for a data storage device comprising a first port and a second port, where that first port is interconnected to a first switch via a first communication pathway having a predetermined first length. The method determines first signal compensation settings based... Agent: Dale F. Regelman Quarles & Brady, LLP
20080307183 - Automatic memory management (amm): The present invention manages the execution of multiple AMM cycles to reduce or eliminate any overlap. Specifically, the present invention provides an external supervisory process to monitor the AMM behavior of VMs on one or more nodes, and intervene when coincident AMM activity appears to be imminent. If AMM patterns... Agent: Hoffman Warnick LLC
20080307184 - Memory controller operating in a system with a variable system clock: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20080307186 - Conformal rolling buffer apparatus, systems, and methods: Methods, apparatus, and systems may operate to more efficiently utilize data stored in an array of storage blocks organized as rows and columns of contiguous blocks, where non-linearity is present in the data. Activities may include organizing data to discard useless elements from storage blocks when transferring the data to... Agent: Schwegman, Lundberg & Woessner, P.A.
20080307187 - Arrangements for memory allocation: In one embodiment a method is disclosed for allocating memory for a processor unit in a group of processing units. The method can include receiving a memory allocation request where the request can indicate a number of binary segments to be stored. The method can determine if the number indicates... Agent: Ibm Corporation (jss) C/o Schubert Osterrieder & Nickelson PLLC
20080307188 - Management of guest os memory compression in virtualized systems: The present invention provides a system and method for managing compression memory in a computer system. This system includes a hypervisor having means for identifying a operating system having a plurality of memory pages allocated, means for counting the number of a plurality of memory pages allocated, and means for... Agent: Cantor Colburn LLP-ibm Yorktown
20080307189 - Data partitioning via bucketing bloom filters: Multiple Bloom filters are generated to partition data between first and second disjoint data sets of elements. Each element in the first data set is assigned to a bucket of a first set of buckets, and each element in the second data set is assigned to a bucket of a... Agent: Microsoft Corporation
20080307190 - System and method for improved virtual real memory: A method for providing virtual real memory includes receiving a request for a memory page from a requestor. A system determines whether the requested memory page is available. In the event the requested memory page is available, the system satisfies the request. In the event the requested memory page is... Agent: Ibm Corporation (pec) C/o Patrick E. Caldwell, Esq.
20080307191 - Method, system and computer program product for managing the storage of data: The present invention provides for a method, system, and computer program product for managing the storage of data. Data is selectively compressed based on a pre-defined compression policy and metadata is stored for physical storage blocks. A stored compression policy identifies at least one criterion for compression, and physical blocks... Agent: Oppenheimer, Wolff & Donnelly, LLP
20080307192 - Method and system for storage address re-mapping for a memory device: A method and system for storage address re-mapping is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of data dispersed in logical address space are mapped in a contiguous manner into blocks in storage address space.... Agent: Brinks Hofer Gilson & Lione/sandisk12/04/2008 > patent applications in patent subcategories. patents and inventions
20080301353 - Boosting throughput of a computer file server: A software layer for boosting the throughput of a computer file server by reducing the number of required mechanical accesses to the physical storage is provided. The throughput boost is achieved through the combination of extending the data requests along the file path and inserting double-buffered paths in front of... Agent: Lumen Patent Firm, Inc.
20080301354 - Multi-processor circuit with shared memory banks: A plurality of processors (10) in a multiprocessor circuit is coupled to a plurality of independently addressable memory banks (12) via a connection circuit (14). The connection circuit is arranged to forward addresses from a combination of the processors (10) to addressing inputs of memory banks (12) selected by the... Agent: Nxp, B.v. Nxp Intellectual Property Department
20080301358 - Electronic device that downloads operational firmware from an external host: An electronic device comprises an interface unit, a control circuit and a microprocessor. The interface unit receives a first operational firmware from a host. The control circuit transfers the first operational firmware to a memory. The microprocessor executes the first operational firmware which stored in the memory. The microprocessor controls... Agent: North America Intellectual Property Corporation
20080301356 - Fast writing non-volatile memory: A method writes data in a non-volatile memory comprising memory cells that are erased before being written. The method comprises the steps of providing a main non-volatile memory area comprising target pages, providing an auxiliary non-volatile memory area comprising auxiliary pages, providing a look-up table to associate to an address... Agent: Seed Intellectual Property Law Group PLLC
20080301355 - Flash memory information reading/writing method and storage device using the same: A flash memory information read/write method in which an external resource such as host, external memory, EEPROM, or external controller is used to read and update new flash memory information after fabrication of a flash memory device, enabling the new flash memory information to be written in a predetermined address... Agent: J C Patents, Inc.
20080301359 - Non-volatile memory and method with multi-stream updating: In a memory that is programmable page by page and each page having multiple sectors that are once-programmable, even if successive writes are sequential, the data recorded to an update block may be fragmented and non-sequential. Instead of recording update data to an update block, the data is being recorded... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20080301357 - Non-volatile memory with auxiliary rotating sectors: A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector... Agent: Seed Intellectual Property Law Group PLLC
20080301361 - Dedicated flow manager between the processor and the random access memory: The invention proposes a flow manager between the main processor and the random access memory that improves performances and security with a memory access management interface processor positioned in interface between the main processor and the random access memory, this memory access management interface processor selecting the relevant flow characteristics... Agent: Touret
20080301360 - Random access memory for use in an emulation environment: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of... Agent: Klarquist Sparkman, LLP
20080301362 - Content addressable memory address resolver: Systems, devices, and methods, including executable instructions are provided for resolving content addressable memory (CAM) match address priority. One method includes retaining a first match address as the best match address. Subsequent match addresses are compared to the retained best match address, each match address being associated with a compare... Agent: Hewlett Packard Company
20080301363 - Virtual tape library device: A storage device system comprises interfaces connected to computers, a plurality of magnetic disks, and a control device that controls the plurality of magnetic disks. When a command from one of the computers instructing a tape library device to load a magnetic tape into a tape device is received by... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080301364 - Caching of microcode emulation memory: A processor includes a cache hierarchy including a level-1 cache and a higher-level cache. The processor maps a portion of physical memory space to a portion of the higher-level cache, executes instructions, at least some of which comprise microcode, allows microcode to access the portion of the higher-level cache, and... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20080301365 - Storage unit and circuit for shaping communication signal: The present invention relates to a storage unit comprising: a channel control portion for receiving a data input/output request; a cache memory for storing data; a disk control portion for performing input/output processing on data in accordance with the data input/output request; and a plurality of disk drives for storing... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080301366 - Raid system and data transfer method in raid system: There is provided a novel storage system in which the number of signal lines will not increase even if the number of storage devices to be connected in a RAID system increases, and a novel data transfer method to enable a high-speed data transfer even when the transfer rate of... Agent: Lucas & Mercanti, LLP
20080301367 - Waveform caching for data demodulation and interference cancellation at a node b: The present patent application discloses a method and apparatus for using external and internal memory for cancelling traffic interference comprising storing data in an external memory; and processing the data samples on an internal memory, wherein the external memory is low bandwidth memory; and the internal memory is high bandwidth... Agent: Qualcomm Incorporated
20080301368 - Recording controller and recording control method: Upon retrieving, after occurrence of replacement of a first cache, move out (MO) data that is a write back target, a second cache determines, based on data that is set in a control flag of a register, whether a new registration process of move in (MI) data with respect to... Agent: Staas & Halsey LLP
20080301369 - Processing of self-modifying code in multi-address-space and multi-processor systems: A method and system of storing to an instruction stream with a multiprocessor or multiple-address-space system is disclosed. A central processing unit may cache instructions in a cache from a page of primary code stored in a memory storage unit. The central processing unit may execute cached instructions from the... Agent: Kenyon & Kenyon LLP
20080301370 - Memory module: A memory module includes a module circuit board, an amplifier circuit disposed on the module circuit board for amplifying an input signal, and a memory component to store a data item, wherein the memory component is disposed on the module circuit board. The amplifier circuit includes an input to receive... Agent: Edell, Shapiro & Finnan, LLC
20080301372 - Memory access control apparatus and memory access control method: A memory access control apparatus includes an MIB for storing information on a plurality of requests and processing the requests in parallel. Upon receipt of a memory access request, the MIB selects a request for a data block to be processed corresponding to the same set of a data block... Agent: Staas & Halsey LLP
20080301371 - Memory cache control arrangement and a method of performing a coherency operation therefor: A memory cache control arrangement for performing a coherency operation on a memory cache comprises a receive processor for receiving an address group indication for an address group comprising a plurality of addresses associated with a main memory. The address group indication may indicate a task identity and an address... Agent: Freescale Semiconductor, Inc. Law Department
20080301373 - Technique for caching data to be written to main memory: A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache... Agent: Anne Vachon Dougherty
20080301374 - Structure for dynamic livelock resolution with variable delay memory access queue: A design structure for resolving the occurrence of livelock at the interface between the processor core and memory subsystem controller. Livelock is resolved by introducing a livelock detection mechanism (which includes livelock detection utility or logic) within the processor to detect a livelock condition and dynamically change the duration of... Agent: Dillon & Yudell LLP
20080301375 - Method, apparatus, and program to efficiently calculate cache prefetching patterns for loops: A mechanism is provided that identifies instructions that access storage and may be candidates for catch prefetching. The mechanism augments these instructions so that any given instance of the instruction operates in one of four modes, namely normal, unexecuted, data gathering, and validation. In the normal mode, the instruction merely... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20080301376 - Method, apparatus, and system supporting improved dma writes: A memory controller receives a stream of DMA write operations and enqueues them in a queue enforcing a First-In First-Out (FIFO) order. Prior to processing a particular DMA write operation, the memory controller acquires coherency ownership of a target memory block and stores the result in a low latency array.... Agent: Ibm Corporation
20080301377 - Data processing system, cache system and method for updating an invalid coherency state in response to snooping an operation: A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state... Agent: Dillon & Yudell LLP
20080301378 - Timestamp based transactional memory: A hardware implemented transactional memory system includes a mechanism to allow multiple processors to access the same memory system. A set of timestamps are stored that each correspond to a region of memory. A time stamp is updated when any memory in its associated region is updated. For each memory... Agent: Vierra Magen/microsoft Corporation
20080301379 - Shared memory architecture: Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a random access memory device, and a parallel link input/output port. The random access memory device may include a... Agent: Brake Hughes Bellermann LLP C/o Intellevate
20080301380 - Data processor: A data processor reads and writes content data from/on at least one unit area of a storage medium. A plurality of packets that store the content data are recorded on the unit area. The data processor includes: a reading section operable to read the packets; a control section operable to... Agent: Mark D. Saralino (pan) Renner, Otto, Boisselle & Sklar, LLP
20080301381 - Device and method for controlling commands used for flash memory: A method and device for controlling commands used for a flash memory are provided. The method includes, substantially reducing usage of a central processing unit (CPU) and a bus, when controlling the flash memory, by receiving information on at least one command currently stored in a system memory, receiving a... Agent: Sughrue Mion, PLLC
20080301382 - Storage system construction managing device and construction management method: The device of the present invention manages changes in the construction of a storage system in a unified manner, and optimally disposes resources. The servers are logically divided into a plurality of virtual servers, the switches are logically divided into a plurality of zones, and the storage devices are logically... Agent: Stanley P. Fisher Reed Smith LLP
20080301383 - Multiple access for parallel turbo decoder: A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to or from the memory bank. A control signal is generated for the first and second Butterfly networks... Agent: Harrington & Smith, PC
20080301384 - Logging and storing of a sequence of image frame data for optimal recovery after power failure: A method of logging and storing of a sequence of acquired X-ray image frame data in an X-ray imaging lab includes logging and updating image frame data related information in a non-volatile memory on a real-time basis upon completion of storage of each image frame data and deleting the logged... Agent: Siemens Corporation Intellectual Property Department
20080301387 - Method and arrangement for securing user-definable data of a franking machine: In a method for data backup of a franking machine in which, in a data backup step, a connection is established between the franking machine and a remote data center via a communication network, data stored in the franking machine are transmitted to the data center as backup data in... Agent: Schiff Hardin, LLP Patent Department
20080301386 - Remote copy system and remote copy control method: Providing a remote copy system for performing remote copy between a plurality of sites each constituted by a plurality of storage subsystems, wherein even if sub-data volumes at the remote site belong to the different storage subsystems, the update order of data copied from the main site to these sub-data... Agent: Antonelli, Terry, Stout & Kraus, LLP
20080301385 - Storage controller and control method for the same: An object of the invention is to provide a storage controller and control method that can efficiently and easily prevent reduced data I/O processing performance due to an imbalance between loads on controllers. In the storage controller and control method for providing, to a host computer, logical volumes created in... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080301388 - Information processing apparatus and computer readable medium: An information processing apparatus includes a restriction section, an acquisition section and a change section. The restriction section restricts maximum amount of stored data to be stored in each of information storage area in response to a reference value predetermined to each of information storage area. The acquisition section acquires... Agent: Sughrue-265550
20080301389 - Memory-protection method and apparatus: A memory-protection method and apparatus is provided that can protect a memory that is used by components in a real time operating system environment (RTOS). The memory-protection method includes requesting access to a first memory region that a first component uses when the first component is called to execute a... Agent: Sughrue Mion, PLLC
20080301390 - System and method for managing addresses in a computing system: A method for retrieving and managing addresses is provided. The steps may include of receiving, at a first buffer of m buffers, a request for an address; obtaining the address from a corresponding first register of the m registers; sending the address, received by said obtaining, to a destination; storing... Agent: Steptoe & Johnson LLP
20080301391 - Method and apparatus for modifying a burst length for semiconductor memory: A method and apparatus for performing a burst access operation for a memory device. The method includes receiving a burst access command for the burst access operation and receiving a burst length modifying value for the burst access operation. A modified burst length is generated from a pre-programmed burst length... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20080301392 - System and device having alternative bit organization: A system is disclosed that includes a first memory device operable according to either a first bit organization or a second bit organization, a second memory device operable according to only the first bit organization, and a central processing unit (CPU). The CPU is commonly connected to the first and... Agent: Volentine & Whitt PLLC
20080301394 - method and a system to determine device criticality during san reconfigurations: A method, a system and a computer program for determining device criticality during SAN reconfiguration operations comprising the steps of building the SAN connectivity graph and mapping the reconfiguration on SAN connectivity graph; locating the affected host systems; and determining the device criticality for each of the affected host systems.... Agent: Hewlett Packard Company
20080301393 - Apparatus and method of processing data of non-volatile memory: An apparatus for processing data of a non-volatile memory according to an aspect of the invention includes a non-volatile memory having a plurality of blocks, an operation processing unit writing, when a write operation is requested from a user, data in the blocks and allowing the blocks, where the data... Agent: Sughrue Mion, PLLC
20080301395 - Software development for parallel processing systems: Within a data processing system, a user-entered data declaration within a program source file is inspected to determine whether a first qualifier is provided with or omitted from the user-entered data declaration. If the first qualifier is provided, an unreserved data storage location disposed within a data-processing integrated-circuit (IC) device... Agent: Shemwell Mahamedi LLP
20080301396 - Dynamic logical mapping: Dynamic logical mapping (“DLM”) provides a virtual layer interposed between a host and a data storage library. Residing on the library, DLM creates a data storage map that records and manages the relationship between a storage cartridge's physical address and that cartridge's mapping to a logical address. During runtime of... Agent: Sun Microsystems, Inc C/o Marsh Fischmann & Breyfogle LLP
20080301397 - Method and arrangements for utilizing nand memory: A method of utilizing NAND type memory is disclosed herein. Operating system type instructions executable by a processor can be stored in a NAND based memory. The instructions can have logical addresses that can be utilized by the processor to fetch the operating system instructions. The method can store address... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Intellevate, LLC
20080301398 - Linear to physical address translation with support for page attributes: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the... Agent: Intel Corporation C/o Intellevate, LLC
20080301399 - Prefetching apparatus, prefetching method and prefetching program product: The efficient performance of prefetching of data prior to the reading of the data by a program. A prefetching apparatus, for prefetching data from a file to a buffer before the data is read by a program, includes: a history recorder, for recording a history for a plurality of data... Agent: Shimokaji & Associates, P.C.
20080301400 - Method and arrangement for efficiently accessing matrix elements in a memory: The invention relates to a method for accessing matrix elements, wherein accesses to two matrix elements that are adjacent in a row or in a column of a matrix and that are each specified by a respective relative address (ar, ac) are performed for the first of said elements in... Agent: Nxp, B.v. Nxp Intellectual Property DepartmentPrevious industry: Electrical computers and digital data processing systems: input/output
Next industry: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: memory patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: memory patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: memory patents we recommend signing up for free keyword monitoring by email.
Advertise on FreshPatents.com - Rates & Info
FreshPatents.com Support - Terms & Conditions
Results in 0.2871 seconds