Electrical computers and digital processing systems: memory inventions 02/08

20080052445 - Flash memory devices including block information blocks and methods of operating same: Disclosed is a semiconductor memory device including pluralities of memory blocks each of which is segmented into main and spare regions, and a block information storing region storing block information of the memory blocks.... Agent: Myers Bigel Sibley & Sajovec

20080052446 - Logical super block mapping for nand flash memory: Increased capacity of a NAND flash memory may be achieved by increasing the availability of non-defective physical blocks by allowing logical super blocks to have physical blocks with different associated position numbers within the physical blocks' respective planes. A flash memory module has one or more flash memory integrated circuits... Agent: Mark M. Friedman

20080052447 - Memory controller: A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080052444 - Method for page random write and read in blocks of flash memory: A method for page random write and read in blocks of flash memory is disclosed. The data could be random written in the pages of block. The pages would be arranged when the block was filled with data, so as to prevent from data copied and erased repeatedly. Present invention... Agent: Birch Stewart Kolasch & Birch

20080052449 - Modular command structure for memory and memory system: A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device.... Agent: Mosaid Technologies Incorporated

20080052452 - Electronic data flash card with various flash memory cells: An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash... Agent: Blakely Sokoloff Taylor & Zafman

20080052448 - Flash memory interface device: A memory interface module provides interfacing between a host processor with multiple flash memories and parallel interfaces of varying protocols. The interface module includes multiple register files, multiple operation information registers, an internal memory, a flash interface portion, and a finite state machine (FSM). The register files receive a command... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080052451 - Flash storage chip and flash array storage system: A flash storage chip including a single circuit board, a microcontroller, a flash memory, and a peripheral component interconnect express (PCI Express) connecting interface is provided. The microcontroller, the flash memory, and the PCI Express connecting interface are embedded on the single circuit board, and the microcontroller has a flash... Agent: Jianq Chyun Intellectual Property Office

20080052450 - System and method of utilizing off-chip memory: One or more methods and/or systems of utilizing a memory external to an integrated circuit chip are presented. In one embodiment, the system comprises an Integrated circuit containing a logic circuitry, a one time programmable memory, a control processor, and a data interface. In one embodiment, a method of storing... Agent: Mcandrews Held & Malloy, Ltd

20080052453 - Portable data storage device: A portable data storage device (10) includes a universal serial bus (USB) coupling device (1) and an interface device (2) is coupled to the USB coupling device (1). The portable data storage device (10) also includes a memory control device (3) and a non-volatile solid-state memory device (4). The memory... Agent: White & Case LLP Patent Department

20080052454 - Methods and systems for a memory section: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080052455 - Method and system for mapping disk drives in a shared disk cluster: An information handling system may include a cluster. The cluster may comprise at least a first node and a second node. The first node may include a first shared disk mapping driver and a second node may include a second shared disk mapping driver. The first node and the second... Agent: Baker Botts, LLP

20080052456 - Apparatus, system, and method for preventing write starvation in a partitioned cache of a storage controller: An apparatus, system, and method are disclosed for preventing write starvation in a storage controller with access to low performance storage devices. A storage device allocation module is included to assign a storage device write cache limit for each storage device accessible to a storage controller. The storage device write... Agent: Brian C. Kunzler Kunzler And Associates

20080052457 - Methods and apparatus for improved raid 1 mirror re-synchronization: Systems and methods for improving performance of a re-synchronization process in a RAID level 1 storage system. In one aspect a local cache memory associated with the second or mirrored disk drive is enabled during the re-synchronization operation but left disabled during normal operation processing host requests. The cache is... Agent: Lsi Corporation

20080052458 - Non-volatile, electrically-programmable memory: A solid-state mass storage device is provided. The solid-state mass storage device defines a storage area adapted to store data; the storage area is adapted to be exploited for storing data with a first storage density at a first data transfer speed. The storage area includes at least a first... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080052459 - Redundant array of independent disks system: A redundant array of independent disks (RAID) system is provided, comprising a nonvolatile memory card array and a RAID controller. Wherein, the non-volatile memory card array consists of at least a non-volatile memory card. The invention has several advantages such as capability to expand storage capacity according to users' needs,... Agent: Birch Stewart Kolasch & Birch

20080052460 - Method and apparatus for accessing a multi ordered memory array: A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080052462 - Buffered memory architecture: A memory architecture includes at least one unbuffered dual inline memory module (DIMM). At least one advanced memory buffer (AMB) provides an interface between the at least one DIMM and a host memory controller.... Agent: Hewlett Packard Company

20080052461 - Portable storage device: Portable storage devices and methods of configuring portable storage devices are disclosed. In an exemplary implementation, a method for configuring a portable storage device may include receiving user input on a portable storage device indicating a mode of operation of the portable storage device. The method may also include receiving... Agent: Hewlett Packard Company

20080052463 - Method and apparatus to implement cache-coherent network interfaces: A cache-coherent network interface includes registers or buffers addressable by a processor with reference to an address space of the processor. The processor and the cache-coherent network interface both share a common system bus. The registers or buffers are further cacheable into a cache of the processor with reference to... Agent: Blakely Sokoloff Taylor & Zafman

20080052464 - Self-trigerring outgoing buffers: A buffer output manager facilitates automatic self-triggering output of buffer contents. At least one processes writes control data to at least one buffer, the control data being such that a buffer output trigger address can be determined therefrom. For each buffer to which control data is written, a buffer output... Agent: Klein, O'neill & Singh, LLP

20080052465 - Method of accessing cache memory for parallel processing processors: A method of accessing cache memory for parallel processing processors includes providing a processor and a lower level memory unit. The processor utilizes multiple instruction processing members and multiple sub-cache memories corresponding to the instruction processing members. Next step is using a first instruction processing member to access a first... Agent: Rosenberg, Klein & Lee

20080052466 - System and method for instruction-based cache allocation policies: A cache is configured to have a first cache line allocation policy for a memory address. An instruction associated with the memory address is received and a second cache line allocation policy is determined based on the instruction. The cache is reconfigured to have the second cache line allocation policy... Agent: Larson Newman Abel Polansky & White, LLP

20080052467 - System for restricted cache access during information transfers and method thereof: Instructions involving a relatively significant information transfer or a particular type of information transfer via a cache, or specified address ranges within cache causing a cache miss result in the application of a restricted access policy to control access to one or more partitions of the cache so as to... Agent: Larson Newman Abel Polansky & White, LLP

20080052468 - Methods, systems and computer readable medium for detecting memory overflow conditions: Representative is a computer-implemented method of detecting a buffer overflow condition. In accordance with the method, a destination address for a computer process' desired right operation is received and a determination is made as to whether the destination address is within an illegitimate writable memory segment within the process' virtual... Agent: Buchanan, Ingersoll & Rooney PC

20080052469 - Reduced memory traffic via detection and tracking of temporally silent stores: A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store, comprising an address and a data value, to a cache is detected, a determination is made that a cache line in the cache... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080052470 - Runtime register allocator: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field,... Agent: Ference & Associates LLC

20080052471 - Data processing system and method for efficient communication utilizing an ig coherency state: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The... Agent: Dillon & Yudell LLP

20080052472 - Methods and apparatus for reducing command processing latency while maintaining coherence: In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least... Agent: Ibm Corporation, Intellectual Property Law

20080052473 - Information processing apparatus: A system controller which controls a plurality of storage devices comprises a unit which divides data of processor bus width from a processor into a plurality of divided data, a first transfer unit which simultaneously transfers the divided plurality of divided data to the plurality of storage devices distributing them,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080052475 - Ring optimization for data sieving writes: In one embodiment, a method and apparatus for ring optimization for data sieving writes is disclosed. The method includes dividing a file range to be written to via a data sieving write operation into N groups, where N is greater than or equal to a number of processes writing to... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney, LLP

20080052474 - Write data mask method and system: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the... Agent: Courtney Staniford & Gregory LLP

20080052476 - Probe-based data storage devices: A probe-based data storage device includes a storage surface having an array of A storage fields; a probe array comprising A probes for writing data to respective storage fields; and an apparatus for controlling writing of blocks of user data in the array of storage fields.... Agent: Michael Buchenhorner, P.A.

20080052477 - Controlling access to non-volatile memory: Access to non-volatile memory is controlled when a first data segment is loaded in the non-volatile memory from a hard disk, a weight is calculated for the first data segment stored in the non-volatile memory based on at least one of the access frequency, the access recency, and the size... Agent: Fish & Richardson P.C.

20080052478 - Relocating a logical volume from a first storage location to a second storage location using a copy relationship: Provided are a method, system, and article of manufacture for relocating a logical volume from a first storage location to a second storage location using a copy relationship. An operation is initiated to move a logical volume from a first storage location to a second storage location. A relationship is... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20080052480 - Data replication in a storage system: For a storage system having plural control units to which plural disk devices are connected, in the method for creating replication in a volume of the disk devices connected to different control units, when receiving update I/O of a replication source during an initial copy for replication, the reflection of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080052479 - Storage system, method of controlling storage system, and storage device: The present invention provides a storage system and a method of controlling the storage system, in which a second site rapidly resumes system process when a first site is damaged. The storage system comprises a first site including a first storage device, a second site including a second storage device,... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080052481 - Method and circuit for transmitting a memory clock signal: Embodiments of the invention generally provide a method and apparatus for transmitting and receiving clock signals. In one embodiment, the method includes receiving, at a memory device, a first clock signal and a second clock signal. The frequency of the first clock signal may be less than the frequency of... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080052482 - Semiconductor memory device and method for controlling clock latency according to reordering of burst data: In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control... Agent: Marger Johnson & Mccollom, P.C.

20080052483 - Thermal control of memory modules using proximity information: An information handling system includes a processor having access to a system memory. The system is operable to detect a thermal alert and identify an associated portion of system memory. The system may then modify memory allocation information used by an operating system to allocate system memory. When the thermal... Agent: Baker Botts, LLP

20080052484 - Method, apparatus, and computer program for image data processing: An image processing apparatus includes an input device, an encoder, a memory, a first allocator, a data block size determination mechanism, a second allocator, and a processor. The input device receives image data of a given data size and transmits the image data in N data blocks. The “N” represents... Agent: Dickstein Shapiro LLP

20080052486 - Method and apparatus for translating a virtual address to a real address using blocks of contiguous page table entries: A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080052485 - System for synchronous code retrieval from an asynchronous source: The present invention discloses a computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code including: program code for delivering, in response to a CPU request, from a host-system processor of a host system, for a command code, an SWI that is different than the... Agent: Mark M. Friedman

20080052487 - Network switching device and control method of network switching device: A network switching device includes multiple ports, multiple switching processors, and a table manager. The switching processors respectively have an address table, a output port specification module, an update requirement determination module, and a table update module. The output port specification module refers to a destination address in received data... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080052488 - Method for a hash table lookup and processor cache: The present, invention improves the hash table lookup operation by using a new processor cache architecture. A speculative processing of entries stored in the cache is combined with a delayed evaluation of cache entries. The speculative processing means that for each cache entry retrieved from main memory in a step... Agent: International Business Machines Corporation

20080046630 - Nand flash memory controller exporting a logical sector-based interface: Data are stored in a memory whose physical pages have a common physical page size by exporting, to a host, a flash-type NAND interface for exchanging data sectors with the host. The common size of the data sectors is different than the physical page size.... Agent: Mark M. Friedman

20080046631 - Memory control device: To provide a technology of increasing the number of ranks of a memory module with a small change in architecture. A memory control device accessing a memory module having a plurality of ranks, includes an interface unit having selection signal lines via which to flow selection signals for selecting the... Agent: Staas & Halsey LLP

20080046632 - Method and apparatus for managing write-to-read turnarounds in an early read after write memory system: A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080046633 - Electronic data storage medium with fingerprint verification capability: An electronic data storage medium is adapted to be accessed by a data terminal, and includes a processing unit connected to a memory device that stores a data file and security reference data possessed by a person authorized to access the data file, and an input-output interface circuit activable so... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080046634 - Electronic data storage medium with fingerprint verification capability: An electronic data storage medium is adapted to be accessed by a data terminal, and includes a processing unit connected to a memory device that stores a data file and security reference data possessed by a person authorized to access the data file, and an input-output interface circuit activable so... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080046635 - Electronic data storage medium with fingerprint verification capability: An electronic data storage medium is adapted to be accessed by a data terminal, and includes a processing unit connected to a memory device that stores a data file and security reference data possessed by a person authorized to access the data file, and an input-output interface circuit activable so... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080046636 - Monolithic read-while-write flash memory device: A memory device includes an executable flash memory partition and a non-executable partition, both partitions being fabricated on a common die. Preferably, both partitions are fabricated using the same flash memory technology. Most preferably, the flash cells of both partitions have insulating floating gates.... Agent: Mark M. Friedman

20080046639 - Memory system with nonvolatile semiconductor memory: A memory system includes a nonvolatile semiconductor memory and a controller. The memory has a plurality memory blocks each including memory cells capable of holding data. The data in each of the memory blocks is erased simultaneously. The data is written simultaneously in pages in each of the memory blocks.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080046640 - Memory system with reduced standby current: Provided is a memory system receiving an external supply voltage from a host. The memory system includes a plurality of flash memories, a memory controller generating a respective chip selection signals respectively selecting one or more of the plurality of the flash memories in response to a request from the... Agent: Volentine & Whitt PLLC

20080046638 - Multiprocessor system having an input/output (i/o) bridge circuit for transferring data between volatile and non-volatile memory: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash... Agent: Daffer Mcdaniel, LLP M/s: 5298

20080046637 - Semiconductor device and processing method for starting the same: A flash memory is made to store a same boot program in a plurality of blocks in it. When a flash memory controller receives an access command for accessing the storage region storing the boot program from a CPU (Step S101), it outputs the read out data to the CPU... Agent: Sonnenschein Nath & Rosenthal LLP

20080046643 - Memory card: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080046641 - Nand flash memory controller exporting a logical sector-based interface: A controller of a flash memory device exchanges data pages with the memory device via a host-type NAND interface and exchanges data sectors with a host via a flash-type NAND interface. The data sectors are different in size than the data pages. A data storage system includes the controller and... Agent: Mark M. Friedman

20080046642 - Nonvolatile memory card: The present invention provides a nonvolatile memory card in which a program is added, modified, changed, or the like by selecting arbitrary firmware on a flash memory from a plurality of pieces of firmware on flash memories. In a memory card, in addition to a program stored in a built-in... Agent: Miles & Stockbridge PC

20080046644 - Method and system to provide a redundant buffer cache for block based storage servers: A block based storage system and method uses RAM memory to implement the buffers and is made redundant by replicating the buffer cache to an in-memory buffer cache on a separate caching unit. Replication can be done using one or more parity schemes (e.g. RAID 1, RAID 5, RAID 6)... Agent: Dla Piper US LLP

20080046645 - Memory management apparatus and method for optical storage system: A memory management apparatus and a related method thereof for accessing digital versatile disc(DVD)data stored in a memory device are disclosed. The memory management apparatus includes an address mapping module, coupled to a bus, for receiving a logic address from the bus and for generating a physical address according to... Agent: North America Intellectual Property Corporation

20080046646 - Data storage apparatus and data access method: A data storage apparatus is provided. The data storage apparatus includes: a storage unit managed using a logical block address; a memory; a storage control unit for storing in the storage unit a free area control table transmitted from the host apparatus in which information on a free area in... Agent: Bell, Boyd & Lloyd, LLP

20080046647 - Apparatus, system, and method for integrating multiple raid storage instances within a blade center: An apparatus, system, and method are disclosed for integrating redundant array of independent disk (“RAID”) storage within a blade center. A plurality of mutually autonomous storage subsystems mount within the blade center through a switch. Each storage subsystem includes a storage module comprising a plurality of storage devices and a... Agent: Kunzler & Mckenzie

20080046648 - Method and system for increasing parallelism of disk accesses when restoring data in a disk array system: In a disk array environment such as a RAID-6 environment, the overall performance overhead associated with exposed mode operations such as resynchronization, rebuild and exposed mode read operations is reduced through increased parallelism. By selecting only subsets of the possible disks required to solve a parity stripe equation for a... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080046649 - Method of controlling semiconductor memory card system: A method of controlling a semiconductor memory card system including a host device incorporating a semiconductor memory card and communicating information with a user of the host device to warn the imminent end of the life of the memory card in the system is provided. According to one aspect, there... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080046650 - System for indicating a plug position for a memory module in a memory system: A memory system including a first and second of set of socket pads adapted for connection to memory module continuity pins. The memory system also includes a first indicator corresponding to the first set of socket pads. The memory system also includes a second indicator corresponding to the second set... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080046651 - Victim cache using direct intervention: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache... Agent: Dillon & Yudell LLP

20080046653 - Methods for reducing data cache access power in a processor, and applications thereof: Methods for reducing data cache access power in a processor. In an embodiment, a micro tag array is used to store base address or base register data bits, offset data bits, a carry bit, and way selection data bits associated with cache accesses. When a LOAD or a STORE instruction... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080046652 - Processor having a micro tag array that reduces data cache access power, and applicatons thereof: Processors and systems having a micro tag array that reduces data cache access power. The processors and systems include a cache that has a plurality of datarams, a processor pipeline register, and a micro tag array. The micro tag array is coupled to the cache and the processor pipeline register.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080046654 - Runtime register allocator: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field,... Agent: Ference & Associates LLC

20080046656 - Multiprocessor system, system board, and cache replacement request handling method: A request issued by the CPU is output from the local arbiter by way of the CPU bus and the CPU-issued request queue. The cache replacement request loop-back circuit determines at the loop-back determination circuit whether the outputted request is a cache replacement request or not. A request other than... Agent: Staas & Halsey LLP

20080046655 - Probabilistic technique for consistency checking cache entries: A facility for determining whether to consistency-check a cache entry is described. The facility randomly or pseudorandomly selects a value in a range. If the selected value satisfies a predetermined consistency-checking threshold within the range, the facility consistency-checks the entry, and may decide to propagate this knowledge to other cache... Agent: Perkins Coie LLP Patent-sea

20080046658 - Data processing system and method for predictively selecting a scope of a prefetch operation: A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains, and a cache memory within the first coherency domain. The cache memory comprises a data array, a cache directory of contents... Agent: Dillon & Yudell LLP

20080046660 - Information recording apparatus and control method thereof: According to one embodiment, a flash memory and an SDRAM having higher information writing and reading speeds are provided as caches with respect to a hard disk. When a free space corresponding to a size of information to be written is not present in the SDRAM and forming in the... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080046657 - System and method to efficiently prefetch and batch compiler-assisted software cache accesses: A system and method to efficiently pre-fetch and batch compiler-assisted software cache accesses are provided. The system and method reduce the overhead associated with software cache directory accesses. With the system and method, the local memory address of the cache line that stores the pre-fetched data is itself cached, such... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080046659 - Pre-fetch controller and method thereof: A pre-fetch controller for pre-fetching data from a memory and providing data to a logic operation unit is disclosed. The pre-fetch controller includes a register for storing a counter value and a controller connected to the register for changing the counter value when a pre-fetching is activated and for changing... Agent: North America Intellectual Property Corporation

20080046661 - Hardware acceleration for a software transactional memory system: A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an... Agent: Blakely Sokoloff Taylor & Zafman

20080046664 - Control device for snoop tag: To prevent a decrease in performance of controlling a snoop tag. A queue is stored with REPLACE target WAY information and an index as an entry associated with a REPLACE request received from a processor, the index stored in the queue is compared with an index of a subsequent READ... Agent: Staas & Halsey LLP

20080046662 - Information processing system, information processing board, and method of updating cache tag and snoop tag: In an information processing system loaded with a CPU having cache and a system controller having a copy of a tag of the cache (snoop tag), and the CPU not issuing replacement information about the cache tag, the number of WAYs of the snoop tags in the system controller is... Agent: Staas & Halsey LLP

20080046663 - System controller, snoop tag modification method and information processing apparatus having snoop tag modificaton function: In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered... Agent: Staas & Halsey LLP

20080046665 - Multiport memory device, multiprocessor system including the same, and method of transmitting data in multiprocessor system: A multiport memory device includes a first dedicated memory region, a second dedicated memory region, and a shared memory region. The first dedicated memory region can be accessed by a first, processor. The second dedicated memory region can be accessed fay a second processor. The shared memory region can be... Agent: F. Chau & Associates, LLC

20080046669 - Information management device, recording medium storing information management program, computer data signal embodied in a carrier wave and information management system: An information management device, including a memory that stores actual information and reference information referring to the actual information; a setting unit that sets to inhibit creation of reference information, regarding with actual information for which creation of reference information is to be inhibited; a receiving unit that receives a... Agent: Sughrue Mion, PLLC

20080046667 - Systems and methods for allowing incremental journaling: In one embodiment, systems and methods are provided for incremental journaling. In one embodiment, order-independent operations are journaled incrementally for the same storage location. In one embodiment, partially ordered operations are journaled incrementally for the same storage location. In one embodiment, order-independent operations and partially ordered operations are journaled incrementally... Agent: Knobbe Martens Olson & Bear LLP

20080046666 - Systems and methods for program directed memory access patterns: Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information.... Agent: Cantor Colburn LLP-ibm Burlington

20080046668 - Technique to perform memory reference filtering: A technique to filter regions of memory. More particularly, at least one embodiment of the invention relates to a technique to detect and filter accesses or information pertaining to a memory access in a computer system... Agent: Caven & Aghevli C/o Intellevate

20080046670 - System and method for storing data and accessing stored data: In one example of a method to access data, selected data stored in a virtual tape library (“VTL”) maintained in a selected format in a first non-tape storage medium is examined. One or more first directories and one more first files are identified within the selected data. One or more... Agent: Brandon N. Sklar. Esq. (patent Prosecution) Kaye Scholer, LLP

20080046671 - Storage system: A technique that can efficiently achieve migration of a configuration and data between storage units with varying constructions of configuration information and that can alleviate burdens of personal operation by an administrator, etc. With the configuration information of each storage unit controlled by the storage control server, based on each... Agent: Stanley P. Fisher Reed Smith LLP

20080046672 - Storage control system and boot control system: A PLD is interposed on the communication route between a microprocessor (hereinbelow called MP) and boot memories. The boot memories store MP start-up data needed to start up the MP and start-up protection code constituting protection code for the MP start-up data. The PLD reads the MP start-up data and... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080046673 - Method and system to optimize java virtual machine performance: A method to assist a software developer in optimizing performance of a Java virtual machine (Jvm) is disclosed. The method includes creating a model to predict future usage of heap memory by the Jvm. In response to the time series analysis model having an upward trend of heap memory usage,... Agent: Cantor Colburn LLP - IBM Rsw

20080046674 - Interface device for debugging and/or tracing a computer system comprising one or multiple masters and one or multiple slaves working together: An interface device (D) is dedicated to debugging and/or tracing in a computer system (CS) comprising at least one master (M1, M2, M3) working with at least one slave (SLj) adapted to be readable and writable at chosen addresses, each master being adapted to execute tasks and to deliver slave... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080046675 - Information recording medium: It is possible to solve the problem that a memory block of a group containing information frequently updated quickly reaches the rewrite service life end when the number of spare blocks prepared in a non-volatile semiconductor recording medium cannot be modified or when the memory block is divided into a... Agent: Mcdermott Will & Emery LLP

20080046676 - Efficient synchronised updates to a data record in a data store: A method for providing synchronized updates to a data record in a data store, the data record including a plurality of data fields, each of the plurality of data fields having an initial field value, the method includes reading the data record from the data store into a data record... Agent: Carey, Rodriguez, Greenberg & Paul, LLP Steven M. Greenberg

20080046677 - Processing system, memory and methods for use therewith: A memory includes an array of memory cells arranged in a plurality of rows and a plurality of columns. An address transform module receives a logical address including a logical column address and logical row address, and transforms the logical address into a physical address having a physical row address... Agent: Garlick Harrison & Markison

20080046678 - System controller, data processor, and input output request control method: A system controller includes an address map storage unit that stores therein an address map that includes mapped areas for accessing FWH that are mounted inside the same data processor. An target determining unit compares, upon receiving an input output request from a CPU, an address included in the input... Agent: Staas & Halsey LLP

20080046679 - Synchronizing a translation lookaside buffer to an extended paging table: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB),... Agent: Caven & Aghevli C/o Intellevate

20080046680 - Verification method, verification program, recording medium, information processor, and integrated circuit: A virtual machine can be implemented by anyone because the interface and other information necessary for implementation are publicly available. Therefore, it is possible that by implementing the virtual machine illegitimately, programs run thereon on will be made to operate illegitimately instead of legitimately. A program compares secret information held... Agent: Wenderoth, Lind & Ponack L.L.P.

20080040533 - Solid state memory device with pci controller: A system interface controller for enabling a computing appliance to read and write data to a fixed or removable non-volatile memory device includes a peripheral component interface having one or more disk and or bus controller registers, a flash memory controller, a random access memory controller, and a random access... Agent: Central Coast Patent Agency, Inc

20080040534 - Reuse of functional data buffers for pattern buffers in xdr dram: A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080040535 - Apparatus and method to manage one or more reserved volume serial numbers in a virtual library grid: An apparatus and method are disclosed to manage one or more reserved volume serial numbers in a virtual library grid. The method supplies a virtual library grid comprising one or more virtual library clusters, wherein each of said one or more virtual library clusters comprises a management interface node, at... Agent: Dale F. Regelman Chandler & Udall, LLP

20080040536 - Method and apparatus for device to request and operate an external buffer provided from the host: A method utilized in an electrical system is proposed. The electrical system includes a device, a host comprising a storage medium, and an interface interconnecting the device and the host. In an example of the proposed method, the device sends a buffer create request to the host. In response to... Agent: North America Intellectual Property Corporation

20080040537 - Digital video recorder having hierarchical memories and method for implementing hierarchical memories: A digital video recorder having hierarchical memories and a method for implementing the hierarchical memories are disclosed. The digital video recorder in accordance with an embodiment of the present invention includes i) a storage unit, which includes a volatile memory, a non-volatile memory, and a hard disk drive and ii)... Agent: Ked & Associates, LLP

20080040538 - File readahead method with the use of access pattern information attached to metadata: Provided is a computer system containing plural storage systems which manages the bandwidth of the storage systems in accordance with storage area attributes. The computer system is characterized in that: a control unit incorporates related file information in metadata, the related file information containing information for identifying a second file... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080040539 - Method and system for writing and reading application data: o

20080040540 - On-disk caching for raid systems: A method according to one embodiment may include creating a reserved partition on at least one volume of a RAID system. The method may also include creating a table to map data stored in the reserved partition to at least one intended volume address of at least one volume of... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Portfolio Ip

20080040543 - Disk array apparatus and disk array apparatus controlling method: Times at which requests for a data read or data write from/to a logical volume are received are stored in memory as access times of a RAID group making up the logical volume. When a predetermined time has elapsed after the access time, a number of the hard disk drives... Agent: Stanley P. Fisher Reed Smith LLP

20080040542 - Raid environment incorporating hardware-based finite field multiplier for on-the-fly xor: A hardware-based finite field multiplier is used to scale incoming data from a disk drive and XOR the scaled data with the contents of a working buffer when performing resync, rebuild and other exposed mode read operations in a RAID or other disk array environment. As a result, RAID designs... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080040541 - System and method for configuring memory devices for use in a network: The present invention is a system for and method of providing a flexible means of using and storing file configuration metadata in a RAID network, so that the memory system does not restrict the metadata to exact format or location in memory. A RAID controller includes software applications, an operating... Agent: Dickstein Shapiro LLP

20080040544 - Computer system for reading and writing data: A system for reading and writing data has a fixed or removable data storage device having a non-volatile memory for storing data, a non-volatile memory controller, a peripheral component interface ported to the controller, and a host computing appliance having a peripheral component interface connector and a host system bus... Agent: Central Coast Patent Agency, Inc

20080040545 - Cache structure: A method for the distribution of digital objects (370) in a peer-to-peer network is disclosed. The digital objects (370) are distributed in a plurality of pieces (371-373). At least some of a plurality of peers (40a-d) are connected to other ones of the plurality of peers (40a-d) and at least... Agent: Morgan, Lewis & Bockius, LLP.

20080040546 - Data processing apparatus and method for performing a cache lookup in an energy efficient manner: A data processing apparatus and method are provided for performing a cache lookup in an energy efficient manner. The data processing apparatus has at least one processing unit for performing operations and a cache having a plurality of cache lines for storing data values for access by that at least... Agent: Nixon & Vanderhye, PC

20080040547 - Structure for power-efficient cache memory: A design structure for a cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by... Agent: Greenblum & Bernstein, P.L.C

20080040549 - Direct deposit using locking cache: The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080040548 - Method for processor to use locking cache as part of system memory: The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080040551 - Cache metadata identifiers for isolation and sharing: Various technologies and techniques are disclosed for providing software accessible metadata on a cache of a central processing unit. A multiprocessor has at least one central processing unit. The central processing unit has a cache with cache lines that are augmented by cache metadata. The cache metadata includes software-controlled metadata... Agent: Microsoft Corporation

20080040550 - Method and apparatus for providing enhanced access to a lightweight directory access protocol (ldap) directory server: The present invention provides for a method and an apparatus for accessing a directory server. The directory server has information stored therein. A caching daemon establishes a first plurality of connections to the directory server. The caching daemon determines if an application is requesting information from the directory server over... Agent: Hewlett Packard Company

20080040552 - Duplex system and processor switching method: The occurrence of a failure in any of an operational processor and a standby processor is monitored, and when a failure occurs in the operational processor, switching to the standby processor is made. A cache memory of each processor has a plurality of ports through which data can be read... Agent: Katten Muchin Rosenman LLP

20080040553 - Method and system for grouping tracks for destaging on raid arrays: A method, system and processor for substantially reducing the write penalty (or latency) associated with writes and/or destaging operations within a RAID 5 array and/or RAID 6 array. When a write or destaging operation is initiated, i.e., when modified data is to be evicted from the cache, an existing data... Agent: Dillon & Yudell, LLP

20080040554 - Providing quality of service (qos) for cache architectures using priority information: In one embodiment, the present invention includes a method for associating a first priority indicator with first data stored in a first entry of a cache memory to indicate a priority level of the first data, and updating a count value associated with the first priority indicator. The count value... Agent: Trop Pruner & Hu, PC

20080040555 - Selectively inclusive cache architecture: In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with the data in the first level... Agent: Trop Pruner & Hu, PC

20080040556 - Data processing system and method for efficient communication utilizing an tn and ten coherency states: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory... Agent: Dillon & Yudell LLP

20080040557 - Data processing system and method for handling castout collisions: A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single update to the system memory.... Agent: Dillon & Yudell LLP

20080040558 - Determining whether data written to source storage locations according to a write order is copied to corresponding target storage locations in the write order: Provided are a method, system, and article of manufacture for determining whether data written to source storage locations according to a write order is copied to corresponding target storage locations in the write order. Values are written to indicated source storage locations in a write order. The values written to... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20080040559 - Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem: A memory system is disclosed. The memory system includes first and second memory devices, and a memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first... Agent: Qualcomm Incorporated

20080040560 - Lightweight single reader locks: A method, system and computer program product for generating a read-only lock implementation from a read-only lock portion of program code. In response to determining that a lock portion of the program code is a read-only lock, a read-only lock implementation is generated to protect at least one piece of... Agent: Ibm Corporation

20080040561 - Method and apparatus for subdividing local memory in nodes of a massively parallel computer system: A memory management mechanism a nodal having multiple processors in a massively parallel computer system dynamically configures nodal memory on demand. A respective variable-sized subdivision of nodal memory is associated with each processor in the node. A processor may request additional memory, and the other processor(s) may grant or veto... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080040564 - Sychronized light path scheme across mutiple sas storage enclosures: A system for synchronizing identify indicators in a computer storage subsystem includes a switch module electrically coupled to an initiator module. The switch module implements a queuing scheme, receives an identify command from the initiator module, executes the queuing scheme to synchronize the identify command, and broadcasts the identify command... Agent: Quarles & Brady LLP

20080040563 - Systems and methods for memory module power management: Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory includes a plurality of memory devices. The memory controller is in communication with the physical memory and has a logical memory... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080040562 - Systems and methods for providing distributed autonomous power management in a memory system: Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller for receiving and responding to memory access requests, a memory bus in communication with the memory... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080040565 - Method and apparatus for supporting immutable memory: A method for managing a memory in a computer system is disclosed. A mapping of a virtual page to physical page is locked in response to receiving a request to make the page immutable. According to an aspect of an embodiment of the invention, locking the mapping of the virtual... Agent: Lawrence Cho Attorney At Law C/o Intellevate

20080040566 - Nodma cache: A NoDMA cache including a super page field. The super page field indicates when a set of pages contain protected information. The NoDMA cache is used by a computer system to deny I/O device access to protected information in system memory.... Agent: Intel/blakely

20080040567 - Command control circuit: A command control circuit includes a read-clock generation circuit that generates a read clock ICLK-R at the time of reading, a write-clock generation circuit that generates a write clock ICLK-W at the time of writing, and a burst chop AL counter that counts an additive latency of a burst chop... Agent: Young & Thompson

20080040568 - Method and system for allocating memory to an electronic device: A method and system for allocating memory to an electronic device (202) is provided. The method includes providing (404) a first static memory allocation to each allocation request of a first plurality of allocation requests. The method also includes determining (406) a mean and a standard deviation from the first... Agent: Motorola Inc

20080040572 - Method, system, and article of manufacture for reserving memory: Provided are a method, system, and article of manufacture, wherein in certain embodiments, a plurality of logical memory blocks corresponding to a memory in a computational device are allocated. An attribute is associated with at least one logical memory block, wherein the attribute indicates whether the at least one logical... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20080040570 - System and method for persistent and robust storage allocation: A method for managing computer memory, in accordance with the present invention, includes maintaining multiple sets of free blocks of memory wherein a free block is added to a set based on its size. In response to a request for a block of a request size, a set of blocks... Agent: F. Chau & Associates, LLC

20080040569 - System, method and storage medium for bus calibration in a memory subsystem: A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration.... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080040571 - System, method and storage medium for bus calibration in a memory subsystem: A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration.... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080040573 - Mapping virtual internet protocol addresses: A method for remapping a Media Access Control (MAC) address mapped to a virtual IP address. The method includes examining an activity data file to identify the virtual IP address mapped to the MAC address and remapping the identified MAC address to an IP address. The virtual IP address may... Agent: Robert M. Mcdermott, Esq.

20080034148 - Systems and methods for providing performance monitoring in a memory system: Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080034149 - High capacity usb or 1394 memory device with internal hub: A high capacity USB or 1394 memory device includes a USB or 1394 port for connecting to an external USB or 1394 port (i.e. the USB or 1394 port of a host device such as a computer), a USB or 1394 hub controller having an upstream end connected to the... Agent: Ying Chen Chen Yoshimura LLP

20080034150 - Data processing circuit: The present invention realizes improvement in security in the case where a nonvolatile memory device which can be read/written by random access is mounted as a memory for storing both of a program and data. In a microcomputer including: a CPU enabling a computing process based on a preset program;... Agent: Miles & Stockbridge PC

20080034152 - Circuit for updating firmware of display apparatus and method thereof: The present invention relates to a circuit for updating firmware of a display apparatus and a method thereof. An optional update unit may be used for initializing the updating process. The first firmware information of the first display apparatus is transmitted to the second display apparatus for updating the second... Agent: Rosenberg, Klein & Lee

20080034151 - Programmable system-on-chip apparatus and method for updating firmware: A programmable system-on-chip (SOC) apparatus is disclosed. After connecting with a computer host, the apparatus temporarily stored boot loader codes into a volatile memory originally installed in the apparatus. Further, during the whole updating firmware procedure, no burner is required. Accordingly, the invention not only saves the hardware cost of... Agent: Birch Stewart Kolasch & Birch

20080034153 - Flash module with plane-interleaved sequential writes to restricted-write flash chips: A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between... Agent: Stuart T Auvinen

20080034154 - Multi-channel flash module with plane-interleaved sequential ecc writes and background recycling to restricted-write flash chips: A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical... Agent: Stuart T Auvinen

20080034157 - Massively parallel data storage and processing system: A distributed processing data storage system utilizing optimized methods of data communication between elements and that effectively collaborate to create and expose various types of unusual data storage objects. In preferred embodiments, such data storage systems would utilize effective component utilization strategies at every level to implement efficient and high-performance... Agent: Crockett & Crockett

20080034155 - Storage apparatus and conversion board: A storage apparatus has a plurality of first disk units of a specific size, each removable, and a controller that controls data read/write from/to the first disk units, and the storage apparatus includes: external connectors, each provided in corresponding positions where the first disk units are installed, and physically and... Agent: Stanley P. Fisher Reed Smith LLP

20080034156 - Storage system for suppressing failures of storage media group: A consumption value of each storage medium and an upper limit related to writing are managed. Respective consumption value and the upper limit of each of two or more storage media out of a plurality of storage media constituting a storage media group are specified, and a remaining use period... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080034158 - Disk array system: A disk array system including at least one channel control portion, at least one disk control portion, a cache memory, a cache switch, a shared memory, a power unit, and a casing for storing the channel control portion, the disk control portion, the cache memory, the cache switch, the shared... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080034159 - Memory card and method for storing data on memory card: A memory card, connected to a host, includes a NAND flash memory and a memory controller. The NAND flash memory includes multiple pages, and each page includes multiple sectors. The memory controller receives sector data and a corresponding sector address from the host. The memory controller enables the sector data... Agent: Volentine & Whitt PLLC

20080034161 - Sample rate converter and method to perform sample rate conversion: Embodiments of a sample rate converter and method for sample rate conversion are generally described herein. In some embodiments, an interpolation module calculates new digital samples for insertion into a digital sample ring, a cache module provides input digital samples of a digital sample stream to the interpolation module, and... Agent: Schwegman, Lundberg & Woessner/creative Labs

20080034160 - System and method for caching results: In certain aspects, the invention features a system and method for caching results, including receiving a job for computation by a distributed computing system having one or more node computing devices in communication with a cache, processing, on one of the node computing devices, the job to create an intermediate... Agent: Milbank, Tweed, Hadley & Mccloy

20080034162 - Cache system: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080034163 - Distributive network control: Included are systems and methods for distributive network control. Also embodiment of a method includes receiving an indication related to recording data stored on a local cache and determining whether to remotely store at least a portion of the data. Some embodiments include sending a request for the stored data.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080034164 - Methods, appartus, and systems for caching: Methods, apparatus, and systems are provided for caching. A caching process is automatically modified in response to update eligibility and an interference relation for a plurality of threads. Data is read into a cache, and a reference to the data is provided to a plurality of threads. An initial thread... Agent: Schwegman, Lundberg & Woessner, P.A.

20080034165 - System and method for achieving deferred invalidation consistency: In a system having a plurality of caches, a method for maintaining cached objects includes storing an object in a plurality of caches. In response to a request to update the object, a future invalidation time is determined when the object should be invalidated in caches currently storing the object.... Agent: James J. Bitetto, Esq. Keusey, Tutunjian & Bitetto, P.C.

20080034166 - Efficient non-blocking k-compare-single-swap operation: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory... Agent: Robert C. Kowert Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20080034167 - Processing a scsi reserve in a network implementing network-based virtualization: Methods and apparatus for processing a reserve request requesting a reservation of at least a portion of a volume in a system implementing network-based virtualization of storage are disclosed. More particularly, multiple ports and/or network devices together implement the virtualization of storage. When a network device or port receives a... Agent: Beyer Weaver LLP

20080034169 - Pseudo-fifo memory configuration using dual fifo memory stacks operated by atomic instructions: Pseudo-FIFO (first in, first out) memory apparatus comprises: a processor operative to execute atomic instructions; a first memory portion operated by the processor as a primary last in, first out (LIFO) memory stack using atomic instructions; and a second memory portion operated by the processor as a backup LIFO memory... Agent: Hewlett Packard Company

20080034168 - Transferring memory buffers between multiple processing entities: Techniques for transferring data between multiple processing entities are described. A processing entity, such as a process or thread, transfers a first data structure to another processing entity. The first data structure represents a first amount of memory and references a second data structure of a similar type. The second... Agent: Hickman Palermo Troung & Becker LLP And Apple Inc.

20080034170 - Method for reading out sensor data: A method is described for reading out sensor data from an intermediate memory written by at least one sensor to the intermediate memory at a data-transfer rate (Tpas). A sampling rate (Tsg) is selected in such a way as to avoid an overflow of the intermediate memory and all buffered... Agent: Kenyon & Kenyon LLP

20080034171 - Systems, methods, and apparatuses for digital wavelet generators for multi-resolution spectrum sensing of cognitive radio applications: Embodiments of the invention may provide for digital wavelet generators utilized in providing flexible spectrum-sensing resolutions for a Multi-Resolution Spectrum Sensing (MRSS) technique. Embodiments of the invention may provide for either multi-point or multi-rate digital wavelet generators. These digital wavelet generators may utilizing the same hardware resource optimally, and the... Agent: Sutherland Asbill & Brennan LLP

20080034172 - Combined pessimistic and optimistic concurrency control: Various technologies and techniques are disclosed that improve implementation of concurrency control modes in a transactional memory system. A transactional memory word is provided for each piece of data. The transactional memory word includes a version number, a reader indicator, and an exclusive writer indicator. The transactional memory word is... Agent: Microsoft Corporation

20080034175 - Methods for phased garbage collection: A method for operating a non-volatile memory storage system is provided. In this method, a write command is received to write data. The write command is allocated a timeout period to complete an execution of the write command. Within the timeout period, a portion of a garbage collection operation is... Agent: Winston & Strawn, LLP

20080034174 - Non-volatile memory storage systems for phased garbage collection: A non-volatile memory storage system is provided. The non-volatile memory storage system includes a memory configured to store a storage system firmware and a non-volatile memory cell array configured to maintain a buffer. A processor in communication with the memory and the non-volatile memory cell array also is included in... Agent: Winston & Strawn, LLP

20080034173 - Portable memory erasing device: An invention is disclosed for a portable memory erasing device that connects directly to one or more uninstalled computer “hard disk” memory storage drive(s) to provide the function of erasing all data stored on the drive without requiring use of a separate computer and/or extra hardware or software. The device... Agent: Gerald J. Iwanejko, Jr.

20080034176 - Computer system and snapshot creation method thereof: This computer system includes a first storage system and a second storage system. The first storage system has a data transfer unit for transferring the data stored in the first volume to the second volume of the second storage system The second storage system has a snapshot creation unit for... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080034178 - Storage device and information management system: Using a snapshot function, a remote copy is efficiently created. Data for a snapshot is converted into a first bitmap of differential data for a remote copy. The conversion is performed in advance at appropriate chronological intervals. Furthermore, when the snapshot function splits, a second bitmap of cascade differential data,... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080034177 - Storage system, method of controlling storage system, and storage device: The present invention provides a storage system and a method of controlling the storage system, in which a second site rapidly resumes system process when a first site is damaged. The storage system comprises a first site including a first storage device, a second site including a second storage device,... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080034179 - Guard bands in very large virtual memory pages: A computer implemented method, apparatus, and computer usable program code for guarding data structures in a data processing system. An exemplary method includes establishing a first guard address range in a portion of a first virtual memory page associated with the data processing system. The portion is less than the... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080034180 - Apparatus and method for processing storage medium and program therefor: A storage medium processing apparatus may include a recognizing unit which sequentially executes logical-format-specific recognizing operations included in a storage-medium recognizing process for recognizing a storage medium loaded in a loading mechanism of the apparatus so that the medium is operable in a software layer, the storage medium having a... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20080034182 - Data storage device, memory management method and program: A data storage device comprises a memory that includes a plurality of physically partitioned memory areas with a rewrite buffer area to be used for data rewrite set within each of the partitioned memory areas and a memory management unit that updates data recorded in each partitioned memory area by... Agent: William S. Frommer, Esq. C/o Frommer Lawrence & Haug LLP

20080034181 - Methods for partitioning an object: The concept of portioning is expanded with a variety of techniques. In particular, one technique involves partitioning an object at multiple levels, where at least one of the levels uses list-based partitioning. Further, a partitioning technique is provided which involves storing a data item in a default partition when the... Agent: Hickman Palermo Truong & Becker/oracle

20080034183 - Protecting critical pointer value updates to non-volatile memory under marginal write conditions: Methods, systems, and apparatuses for updating pointers in memory are described. A device can include pointer logic and a memory that stores a memory pointer. The pointer logic can increment or decrement the memory pointer according to Gray code. The device can increment or decrement the memory pointer in response... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.