|FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE|
USPTO Class 711 | Browse by Industry: Previous - Next | All
01/2008 | Recent | 08: Dec | Nov | Oct | Sp | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 07: D | N | O | S | A | J | J | M | A | M | F | J | | 06: 12 | 11 | 10 | 09 | 8 | 7 | 6 | 5 | 4 | Dec | Nov | | 2010 | 2009 |
Electrical computers and digital processing systems: memory January USPTO class listing 01/08Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/31/2008 > patent applications in patent subcategories. USPTO class listing
20080028123 - Computer system having daisy chained memory chips: A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20080028124 - Virtual machine system and operating method thereof: A virtual machine system includes a physical memory and a virtual machine monitor (VMM) When a kernel image of one guest OS, in startup of the one guest OS, has already been loaded on the physical memory, the VMM starts up one guest OS with the kernel image.... Agent: Mcginn Intellectual Property Law Group, PLLC
20080028125 - Computer system having an apportionable data bus: A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second portion dedicated... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20080028127 - Cross-threaded memory system: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requester IC devices are... Agent: Shemwell Mahamedi LLP
20080028128 - Memory access controller and method for memory access control: A memory access controller has a first interface connectable to a memory and a second interface coupled with a first and a second executing unit. A critical software portion is stored in a first segment of the memory, and an uncritical software portion is stored in a second segment of... Agent: Dickstein Shapiro LLP
20080028126 - Memory system having an apportionable data bus and daisy chained memory chips: A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20080028130 - Mass memory device and semiconductor memory card: A mass memory device has a nonvolatile semiconductor memory device that can be accessed via a contact bank using an access device. An auxiliary device can be used to read data stored in the semiconductor memory device without going through the access device.... Agent: Slater & Matsil LLP
20080028132 - Non-volatile storage device, data storage system, and data storage method: A non-volatile storage device comprises a non-volatile memory into which data is written per unit area, and a memory controller for controlling writing of data into the non-volatile memory. The memory controller comprises a first storage section for holding data input from the outside of the device, a first control... Agent: Mcdermott Will & Emery LLP
20080028131 - Nonvolatile memory system, and data read/write method for nonvolatile memory system: A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20080028129 - Semiconductor memory device: A writing completion flag table (105) for storing a writing completion flag corresponding to a predetermined storage unit such as a cluster or a physical block is stored in a non-volatile control memory (106). When completion of data writing into a predetermined storage unit is detected, a write completion flag... Agent: Greenblum & Bernstein, P.L.C
20080028134 - Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as... Agent: Antonelli, Terry, Stout & Kraus, LLP
20080028133 - Flash memory system and data writing method thereof: Provided are a flash memory system and a data writing method thereof, the method including (a) transmitting a predetermined command and an address signal to a flash memory device included in the flash memory system, (b) transmitting data to the flash memory device, and (c) generating a parity code for... Agent: F. Chau & Associates, LLC
20080028137 - Method and apparatus for refresh management of memory modules: One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to... Agent: Patterson & Sheridan, LLP Metaram
20080028135 - Multiple-component memory interface system and method: A system and method are provided, wherein a first component and a second component are operable to interface a plurality of memory circuits and a system.... Agent: Zilka-kotab, PC
20080028136 - Method and apparatus for refresh management of memory modules: One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to... Agent: Patterson & Sheridan, LLP Metaram
20080028139 - Content-addressable memory that supports a priority ordering between banks: One embodiment of the present invention provides a system that implements a content-addressable memory (CAM) which has multiple banks. During operation, the system receives a request to insert an item into the CAM, wherein the request includes a key which is used to index the item and a body containing... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP
20080028138 - Content-addressable memory that supports a priority ordering between banks of differing sizes: One embodiment of the present invention provides a system that implements a content-addressable memory (CAM) which has multiple banks. During operation, the system receives a request to insert an item into the CAM, wherein the request includes a key which is used to index the item and a body containing... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP
20080028140 - Lookups by collisionless direct tables and cams: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collision of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary... Agent: Driggs, Hogg & Fry Co. L.p.a.
20080028142 - Online storage medium transfer rate characteristics determination: A method for determining storage medium transfer rate characteristics. A host computer system issues a sequence of read commands to a storage medium to determine an accurate mapping of differences in transfer rate characteristics. For example, the host issues a sequence of relatively large reads to the storage medium at... Agent: Hickman Palermo Truong & Becker, LLP
20080028141 - System and method for implementing hard disk drive data clear and purge: A method, system, and computer-usable medium for implementing a hard disk drive data clear and purge. In a preferred embodiment of the present invention, a processor sends a predetermined data pattern to be written to a hard disk drive and issues a command for the hard disk drive to write... Agent: Dillon & Yudell, LLP
20080028143 - Management system for a virtualized storage environment: In a method to automate configuration of a storage virtualized environment in a system that includes one or more storage systems having array groups and one or more storage virtualizers, a management terminal selects an array group that is able to meet specifications for allocating a logical volume. The management... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080028144 - Method of restoring data by cdp utilizing file system information: The storage system includes a disk drive and a processor, the processor serving as a file system input/output processing unit and a block input/output processing unit. In the storage system, the block input/output processing unit provides, to the file system input/output processing unit, storage areas of the disk drive as... Agent: Townsend And Townsend And Crew, LLP
20080028145 - Implementing virtual disk reservations on a storage media for multiple distributed applications: A method for implementing virtual disk reservations on a storage media for multiple distributed applications. The method includes initializing a plurality of virtual disks, wherein each of the virtual disks is instantiated on a physical storage media. A reservation status is determined for each of the virtual disks and a... Agent: Wagner, Murabito & Hao LLP Third Floor
20080028146 - Usb flash disk device and method: A portable storage device includes a storage area for storing data; a first connector operative to enable access to only a first portion of the storage area; a second connector operative to enable access to only a second portion of the storage area; and a single housing that accommodates the... Agent: Mark M. Friedman
20080028147 - Affecting a caching algorithm used by a cache of a storage system: A storage system includes plural storage units having respective storage controllers and associated caches. A first one of the storage units further includes an internal workload generator to initiate a data operation with respect to at least one destination storage unit, where the data operation is associated with tag information... Agent: Hewlett Packard Company
20080028148 - Integrated memory device and method of operating a memory device: An integrated memory device includes a memory core having a plurality of memory cells and a group of terminals for communication between the memory device and an external electronic device. A data buffer temporarily stores data. The data buffer is coupled to the group of terminals and to the memory... Agent: Slater & Matsil LLP
20080028149 - Method and system for client-side caching: An improved method and system for client-side caching that transparently caches suitable network files for offline use. A cache mechanism in a network redirector transparently intercepts requests to access server files, and if the requested file is locally cached, satisfies the request from the cache when possible. Otherwise the cache... Agent: Workman Nydegger/microsoft
20080028150 - Autonomic mode switching for l2 cache speculative accesses based on l1 cache hit rate: A speculative access mechanism in a memory subsystem monitors hit rate of an L1 cache, and autonomically switches modes of speculative accesses to an L2 cache accordingly. If the L1 hit rate is less than a threshold, such as 50%, the speculative load mode for the L2 cache is set... Agent: Martin & Associates, LLC
20080028151 - Cache memory control method and cache memory apparatus: The present invention is contrived to divide an address for accessing cache memory into a first through a fourth fields from the uppermost bit side, use the first and third fields for respectively storing tag addresses, divide the second and fourth fields into one or more subfields, respectively, use one... Agent: Staas & Halsey LLP
20080028152 - Tiled cache for multiple software programs: Caching techniques for storing instructions, constant values, and other types of data for multiple software programs are described. A cache provides storage for multiple programs and is partitioned into multiple tiles. Each tile is assignable to one program. Each program may be assigned any number of tiles based on the... Agent: Qualcomm Incorporated
20080028154 - Method and apparatus for memory utilization: One embodiment of the invention provides a method and apparatus for utilizing memory. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20080028153 - Methods and apparatuses for mappable shared cache management: Methods and apparatuses enable separate management of shared data structures and shared data objects referenced by the shared data structures. The shared data structures are stored in a first memory, and the shared data structures are separately managed from the referenced shared data objects. The shared data objects can be... Agent: Sap/blakely
20080028155 - Data processing system and method for efficient coherency communication utilizing coherency domain indicators: In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master... Agent: Dillon & Yudell LLP
20080028156 - Data processing system and method for efficient storage of metadata in a system memory: A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory... Agent: Dillon & Yudell LLP
20080028157 - Global shared memory switch: Embodiments of the present invention provide functionality, within a storage-shelf-router integrated circuit, an I/O-controller integrated circuit, or other integrated-circuit implementations of complex electronic devices, for interconnecting all possible pairs of communications ports, a first member of each pair selected from a first set of communications ports and a second member... Agent: Olympic Patent Works PLLC
20080028162 - Automatic data block misalignment detection and correction in a computer system utilizing a hard disk subsystem: An embodiment of a data misalignment correction method for a mass storage controller system that couples drives having large internal block sizes to a computer operating system having input/output data block requests, including automatically determining an amount of misalignment between a request of the input/output data block to the storage... Agent: Hewlett Packard Company
20080028160 - Carrier having daisy chain of self timed memory chips: A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20080028159 - Carrier having daisy chained memory chips: A carrier having at least one memory chip in a daisy chain of memory chips. A first carrier has at least a portion of an entire daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20080028161 - Daisy chainable self timed memory chip: A memory chip suitable for use in a daisy chain of memory chips. Timing of an array on the memory chip is dynamically determined by circuitry on the memory chip that tracks an access timing of the array. The memory chip is configured to receive an address/command word, determine if... Agent: Robert R. Williams IBM Corporation, Dept. 917
20080028166 - Data processing system and method for operating a data processing system: A data processing method and system including a processor, a user data storage medium, and a management data storage medium, wherein the management data are used to manage the user data.... Agent: Dickstein Shapiro LLP
20080028164 - File storage control device and method: A file storage control device (for example NAS) comprises a storage space provision portion, which provides, to a higher-level device used by a user, a single storage space associated with a plurality of logical storage units (LUs) provided by a storage system; a reception portion, which receives requests to write... Agent: Antonelli, Terry, Stout & Kraus, LLP
20080028158 - Memory controller for daisy chained memory chips: A memory controller configured to control a daisy chain of memory chips. The memory controller receives read and write requests from a processor, determines a daisy chain of memory chips that the request is directed to, determines which memory chip in the chain of memory chips the request is directed... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20080028165 - Memory device, its access method, and memory system: A memory device comprises a controller having an interface and an MPU, and configured to enable transferring a device driver for a second access mode via the interface in a first access mode, the second access mode differently defined from the first access mode, and a semiconductor memory with the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20080028163 - Method and apparatus for repurposing compute resources to implement, or not implement, storage access protocols: In one embodiment, at least one characteristic of an ecosystem is monitored. The ecosystem includes i) a plurality of compute resources, and ii) a number of storage applications, wherein the number of storage applications are configured to use a plurality of storage access protocols. Which of the storage access protocols... Agent: Hewlett Packard Company
20080028167 - Epoch-based mud logging: Methods and apparatus for performing MUD logging for a volume in a system implementing network-based virtualization are disclosed. This is accomplished by enabling two or more MUD loggers to separately maintain a MUD log for the volume. Through enabling the MUD loggers to communicate, the MUD loggers may update their... Agent: Beyer Weaver LLP
20080028168 - Data storage apparatus, data protection method, and communication apparatus: A data storage apparatus includes a memory in a housing. The apparatus includes a wire which is routed at intervals each being sufficiently narrow for the length or width of each face of the housing, which covers substantially all the faces of the housing, and which is sufficiently thin for... Agent: Bell, Boyd & Lloyd, LLP
20080028171 - Backup system and backup method: When detecting the completion of remote copying of a primary volume to a secondary volume, a host computer splits a copy pair into the primary volume and the secondary volume and has the secondary volume store a snapshot of the primary volume. A backup server recognizes the secondary volume.... Agent: Stanley P. Fisher Reed Smith LLP
20080028169 - Extending non-volatile storage at a computer system: The present invention extends to methods, systems, and computer program products for extending non-volatile storage at a computer system. In some embodiments, a file operation is performed on at least one shadow copy of a file that is perceived by an application to be stored on a single volume. A... Agent: Workman Nydegger/microsoft
20080028170 - Protocol for managed copy of media content: Various embodiments allow for managed copies of multimedia content to be made by end users. The managed copy process can ensure that end users can make legitimate and controlled copies of content while, at the some time, give content producers the ability to control and authorize such copies.... Agent: Lee & Hayes PLLC
20080028173 - Soft media changer: A first data is written to a removable storage medium at a target device. A request is received to eject the removable storage medium from the target device, wherein the removable storage medium is not ejected from the target device. The first data on the removable storage medium is copied... Agent: Microsoft Corporation
20080028172 - Storage system performing remote copying: If the pair state of a certain volume pair in one copy group is a fault state which has changed due to occurrence of a fault in the volume pair, then a write holding state is set for the copy group, and after setting the write holding state, the pair... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080028174 - System and method for managing resets in a system using shared storage: A method of managing storage device resets in a system using shared storage is provided. A reset instruction is received at a shared storage device from a first node. In response, the storage device is at least partially reset, including aborting one or more queued I/O commands including a first... Agent: Baker Botts, LLP
20080028177 - Memory controller for daisy chained self timed memory chips: A memory controller for controlling a daisy chain of self timed memory chips. The memory controller has information as to how long each self timed memory chip in the daisy chain of memory chips takes to make a read access and a write access to an array on the self... Agent: Robert R. Williams
20080028176 - Memory system having self timed daisy chained memory chips: A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20080028175 - Self timed memory chip having an apportionable data bus: A self timed memory chip having an apportionable data bus. Access timing to an array on the memory chip is dynamically determined by circuitry on the memory chip. A ring oscillator on the memory chip has a frequency that is indicative of how fast an array on the memory chip... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20080028178 - Detection of memory leaks: Embodiments are configured to manage memory, including detecting one or more memory leaks. The various embodiments are configured to detect memory leaks and/or associated data without adding extra space or overhead for each associated memory allocation as compared with current implementations. In an embodiment, memory is managed including the detection... Agent: Merchant & Gould (microsoft)
20080028179 - System and method for recompiling code based on locality domain and thread affinity in numa computer systems: A technique for reducing non-local access, in dynamically generated code that resides in a code buffer of a NUMA computer system including multiple nodes, for improving overall performance of dynamic optimization systems. In one example embodiment, this is accomplished by partitioning the code buffer into multiple smaller code buffers and... Agent: Hewlett Packard Company
20080028180 - Inappropriate access detector based on system segmentation faults: Embodiments of the present invention provide an inappropriate access detector of system segmentation faults. Other embodiments may be described and claimed.... Agent: Schwabe, Williamson & Wyatt, P.C.
20080028181 - Dedicated mechanism for page mapping in a gpu: Circuits, methods, and apparatus that reduce or eliminate system memory accesses to retrieve address translation information. In one example, these accesses are reduced or eliminated by pre-populating a graphics TLB with entries that are used to translate virtual addresses used by a GPU to physical addresses used by a system... Agent: Townsend And Townsend And Crew LLP
20080028182 - Address counter for nonvolatile memory device: An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.01/24/2008 > patent applications in patent subcategories. USPTO class listing
20080022032 - Concurrent virtual machine snapshots and restore: Various mechanisms are disclosed herein for the saving and restoring of virtual machine environment state. For example, virtual machine state can be either be saved or (multiple) snapshots can be taken of the virtual machine state. In the latter case, virtual processors can be allowed to run while the memory... Agent: Woodcock Washburn LLP (microsoft Corporation)
20080022033 - Boot read-only memory (rom) configuration optimization: Embodiments of the invention address deficiencies of the art in respect to boot ROM handling and provide a method, system and computer program product for optimized boot ROM handling for I/O devices. In one embodiment of the invention, a ROM scan area optimization method can be provided. The method can... Agent: Carey, Rodriguez, Greenberg & Paul, LLP Steven M. Greenberg
20080022035 - Recordable device that could record flash disks without computers: The present invention is related to a recordable device that can record flash disks without computers. There are two slots for general serial buses. Two flash disks can insert into these two slots for mutual copy. A control circuit chooses the file format and the file date according to the... Agent: Anthony R. Barkume
20080022034 - Segmentation for a flash memory of a flash disc: A segmentation design for dividing the flash memory of a flash disc into three segments A, B and C, or more segments. Segment A is a control area, segment B (only readable but not writable to ordinary user) is a storage area particularly for storing the special program and data... Agent: Bacon & Thomas, PLLC
20080022036 - System and method for persistent ram disk: The contents of a RAM disk are copied to an image file in nonvolatile memory on power-down and copied back on reboot to provide an appearance of persistence. A locking method can use in-use tables to limit access to the same blocks of data in a RAM disk.... Agent: Wilmerhale/boston
20080022037 - Memory system and method for transferring data therein: A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from... Agent: Slater & Matsil, L.L.P.
20080022038 - Method and system for controlling access to tape media from a plurality of virtual computers: A tape library comprises: a plurality of tape media; a plurality of slots in which the plurality of tape media are respectively stored; a drive in which a tape medium extracted from any of the plurality of slots is set and which performs tape reading or writing in respect of... Agent: Sughrue Mion, PLLC
20080022039 - Random number generation: A controller for controlling the operation of a hard disk drive is capable of generating a random number using the hard disk drive. Initially the hard disk drive is disabled from performing a read-ahead operation. Random addresses on the hard disk drive are generated from the output of the pseudo-random... Agent: Harness, Dickey & Pierce, P.L.C
20080022040 - Cache memory system: The cache memory system 1 comprises: a virtual index obtaining unit 13 operable to obtain, based on a virtual address, virtual indexes of an access-target cache line and a cache line potentially having a cache-aliasing relationship with the access-target cache line; a physical tag obtaining unit 15 operable to obtain... Agent: Mcdermott Will & Emery LLP
20080022041 - Storage control system, control method for storage control system, port selector, and controller: An object of the present invention is to provide a means for detecting a logical command error, and a storage system and its control method that can properly perform error handling, and detection and blockage of a malfunctioning section. A storage control system includes controller units 130A and 130B for... Agent: Antonelli, Terry, Stout & Kraus, LLP
20080022042 - Computer system and a method of replication: In a cluster-structured disk subsystem, when creating a volume for an online backup separately from a volume for a normal I/O, it is desirable to be able to achieve such a creation for any volume under subsystem. Further, with an increase in the capacity of the subsystem, it becomes more... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080022043 - Method, system and smart card reader for management of access to a smart card: The described embodiments relate generally to devices, methods and systems for managing access to a memory card, such as a smart card, by a plurality of accessing devices. Certain embodiments relate to a smart card reader (SCR) for managing access to a smart card by a plurality of accessing devices.... Agent: Bereskin And Parr
20080022044 - Digital data processing apparatus having multi-level register file: A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20080022045 - Handling fetch requests that return out-of-order at an instruction fetch unit: One embodiment of the present invention provides a system that handles instruction fetch requests that return out-of-order at an IFU of a processor. During operation, the system sends a request to obtain a cache line to an instruction cache, wherein the request can be serviced and the cache line can... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP
20080022046 - Partial cache way locking: Systems and methods are disclosed for locking code in cache. In one embodiment, a processor comprises a cache and a cache controller. The cache is configured to store a temporary copy of code residing in main memory. Also, the cache is divided into a number of cache ways, where each... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20080022047 - Storage circuit and method therefor: Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (103-106), a shared read word line (107), and separate write word lines (108-111) are used. In... Agent: Freescale Semiconductor, Inc. Law Department
20080022048 - Avoiding cache line sharing in virtual machines: Avoiding cache-line sharing in virtual machines can be implemented in a system running a host and multiple guest operating systems. The host facilitates hardware access by a guest operating system and oversees memory access by the guest. Because cache lines are associated with memory pages that are spaced at regular... Agent: Woodcock Washburn LLP (microsoft Corporation)
20080022049 - Dynamically re-classifying data in a shared cache: In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared... Agent: Trop Pruner & Hu, PC
20080022050 - Pre-fetching data for a predictably requesting device: Systems and methods are disclosed herein for controlling the way in which data access requests from different masters are handled. In one example, a memory controller comprises a request analyzer configured to receive a data access request via a data bus. The request analyzer is further configured to analyze the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20080022051 - Systems and methods for providing fixed-latency data access in a memory system having multi-level caches: Systems and methods for bypassing lower level caches and enabling direct access to higher level caches in order to provide fixed data latency and increased amounts of immediately accessible storage. One embodiment comprises a memory system having multiple cache memories that have increasing data latencies and amounts of storage. In... Agent: Law Offices Of Mark L. Berrier
20080022052 - Bus coupled multiprocessor: There is provided a bus coupled multiprocessor capable of reducing the number of snooping processes of each of a plurality of processors (CPU) constituting the multiprocessor, whereby the performance of the CPU is improved and its power consumption is reduced. According to the present invention, each of the CPUs includes... Agent: Buchanan, Ingersoll & Rooney PC
20080022053 - Device unit, an image forming apparatus, a management system, and a recycling system capable of using non-genuine device unit as replacement product: A novel device unit is detachably provided to an image forming apparatus having a control unit configured to control the image forming apparatus. The device unit includes a CPU configured to communicate with the control unit; and a memory configured to store property information including information provided through a communication... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20080022054 - Object based conflict detection in a software transactional memory: Object-based conflict detection is described in the context of software transactional memory. In one example, a block of instructions is received for execution as an object in a software transactional memory transaction. The base of the object is computed, a lock is found for the object using the base of... Agent: Blakely Sokoloff Taylor & Zafman
20080022056 - Data recording apparatus, data recording method, and computer product: In a data recording apparatus, a monitoring unit detects a VLU including an MRB that manages an area that has not been accessed for a specified time period based on a current time, a time management table, and a parameter table. From MRBs of the detected VLU, the monitoring unit... Agent: Staas & Halsey LLP
20080022055 - Processor, memory device, computer system, and method for transferring data: A processor connected to a memory device includes a random number generator that generates random numbers identical to random numbers generated in the memory device; an XOR logic unit that performs a XOR operation of the random numbers and an address in the memory device to be accessed; and an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20080022060 - Data recording apparatus, program product, and data recording method: A data recording apparatus includes a determining unit that determines whether a storable area is present in the first storage device. The storable area is a combination of a plurality of empty areas having contiguous physical addresses with a total data volume larger than that of a volume of the... Agent: Staas & Halsey LLP
20080022058 - Removable portable data backup for a network storage system: A storage server creates a first mirror of a primary volume of data on a first storage set that includes at least one disk and creates a second mirror of the primary volume, on a second storage set that also includes at least one disk. The server then quiesces the... Agent: Network Appliance/blakely
20080022059 - Sequencing transactions and operations: Systems and techniques for sequencing transactions and operations. In one aspect, an article includes one or more machine-readable media storing instructions operable to cause one or more machines to perform operations. The operations include identifying a delta of a first data store, and replicating the delta, including the transaction, to... Agent: Mintz, Levin, Cohn, Ferris, Glovsky & Popeo, P.C.
20080022057 - Synchronization of change-tracked data store with data store having limited or no change tracking: A data store in which changes are not tracked is synchronized with a data store in which changes are tracked utilizing a shadow store. The shadow store contains shadow data indicative of the most recent synchronization operation between the data stores. The shadow data comprises hash values of the data... Agent: Woodcock Washburn LLP (microsoft Corporation)
20080022061 - Backup system, recording/reproduction device, backup device, backup method, program, and integrated circuit: A content of Copy Once cannot be copied to an external device or the like, even for the purpose of making a backup. This is inconvenient for the user. However, if copying to another device for the purpose of making a backup is permitted, the content may be copied in... Agent: Wenderoth, Lind & Ponack L.L.P.
20080022062 - Storage apparatus and data protection method: A virtual first volume is provided to a host apparatus, and a storage area with a necessary capacity from among one or more storage areas is dynamically allocated to the first volume in response to a write access request from the host apparatus; and write data from the host apparatus... Agent: Antonelli, Terry, Stout & Kraus, LLP
20080022063 - Relocating of system management interface code within an information handling system: A method for relocating system management interface code in an information handling system which includes extracting a relocation table from the system management interface code, inserting a relocation identifier in each entry of the system management interface code having an address, searching the system management code for the relocation identifier... Agent: Hamilton & Terrile, LLP
20080022064 - Memory pipelining in an integrated circuit: A method for pipelining a memory in an integrated circuit includes providing a first clock phase and providing a second clock phase, wherein the first clock phase and the second clock phase are at least partially non-overlapping. The method further includes providing a first memory array and providing a second... Agent: Freescale Semiconductor, Inc. Law Department
20080022065 - Dynamically sharing a stack between different code segments: In one embodiment, the present invention includes a method for receiving a request from a caller code portion of a first color to color at least a portion of a stack with a second color, determining if the request is valid, and if so remapping the stack portion from a... Agent: Trop Pruner & Hu, PC
20080022066 - Memory tracking with preservation of alignment semantics: A method and system for tracking usage of memory in a computer system is provided. Arguments for both the size of a memory allocation and the type of memory being allocated are reserved in a fixed location. A first fixed location is reserved for small memory allocations, i.e. less than... Agent: Lieberman & Brandsdorfer, LLC
20080022067 - Method, system and program product for storing downloadable content on a plurality of enterprise storage system (ess) cells: The present invention takes advantage of unused storage space within the ESS cells to provide for the efficient and cost effective storage of downloadable content. Specifically, the system of the present invention generally includes a download grid manager that communicates with the ESS cells. Content to be replicated to the... Agent: Hoffman Warnick & D'alessandro, LLC
20080022068 - Leverage guest logical to physical translation for host-side memory access: Guest logical to physical translation is leveraged for host-side memory access. A contiguous portion of host physical address space is dedicated to the guest operating system. A reusable offset value may be calculated upon guest operating system initialization. Everything stored in the guest “physical” address space can be directly mapped... Agent: Woodcock Washburn LLP (microsoft Corporation)01/17/2008 > patent applications in patent subcategories. USPTO class listing
20080016267 - Memory controller, flash memory system having memory controller, and method for controlling flash memory: In the case where a sector count written in a sector count register R2 as information which indicates the access operation is m, the memory controller according to the present invention starts a access operation after a physical block address register R11, a sector number register R12, and a counter... Agent: Oliff & Berridge, PLC
20080016269 - Flash / phase-change memory in multi-ring topology using serial-link packet interface: A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock... Agent: Stuart T Auvinen
20080016268 - System and method for updating firmware in a non-volatile memory without using a processor: A processing system coupled to an apparatus is provided. The processing system includes: a non-volatile memory (NVM) storing firmware needed by the processing system; and an NVM control interface writing and reading data stored in the NVM. The apparatus verifies a previous piece of data being already written into the... Agent: North America Intellectual Property Corporation
20080016270 - Semiconductor memory device: A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier circuit which amplifies data transferred to the bit lines, a first dummy cell group including first dummy cells, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20080016271 - Semiconductor memory device: A semiconductor memory device includes: phase-change memory cells whose states change to a set resistance state or a reset resistance state in response to an applied current pulse; a set pulse driving circuit outputting a set current pulse having first through n-th stages in response to a first control signal... Agent: Volentine & Whitt PLLC
20080016272 - Method of refreshing dynamic random access memory, in particular in standby mode and in active operating mode, and corresponding dynamic random access memory device, for example incorporated into a cellular mobile telephone: A dynamic random access memory may include at least one group of memory cells, and a respective auxiliary memory for each group of memory cells. The respective auxiliary memory is for storing refresh information specific to each respective group of memory cells. The refresh information may include a current refresh... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20080016273 - System and method to reduce disk access time during predictable loading sequences: A method, software, and system for loading data from disk include comparing a current sequence of disk I/O requests to data indicative of a previous disk I/O request sequence. Responsive to detecting a match between the current disk I/O sequence and the previous disk I/O sequence, a copy of data... Agent: Ibm Corporation
20080016274 - Method of protecting cache memory data in storage system: A method of protecting the cache memory data in a storage system is used to protect the data in the cache memory of a battery backed storage system. The method provides a preserved area in the random access memory (RAM) of the system for storing the information of disk cache... Agent: Harness, Dickey & Pierce, P.L.C
20080016275 - Allocation-unit-based virtual formatting methods and devices employing allocation-unit-based virtual formatting methods: In various embodiments, the present invention provides virtual disk formatting by intermediate devices including: (1) a storage shelf router and the storage shelf in which the storage-shelf is included, to external computing entities, such as disk-array controllers and host computers; (2) an I/O controller; and (3) a storage-bridge device. The... Agent: Olympic Patent Works PLLC
20080016276 - Folding usb flash memory device for providing memory storage capacity: A USB flash memory device connected to a USB bus includes a flash memory module including at least one flash memory, a USB connector for transferring data packets onto the USB bus and receiving the data packets from the USB bus, a USB controller for controlling the USB connector according... Agent: Mills & Onello LLP
20080016277 - Dram hierarchical data path: A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown
20080016279 - Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality: A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and... Agent: Dillon & Yudell LLP
20080016278 - Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule: A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory... Agent: Dillon & Yudell LLP
20080016280 - System, method and storage medium for providing data caching and data compression in a memory subsystem: A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20080016281 - System, method and storage medium for providing data caching and data compression in a memory subsystem: A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20080016282 - Cache memory system: A cache memory system includes: a plurality of cache lines, each including a data section for storing data of main memory and a line classification section for storing identification information that indicates whether the data stored in the data section is for instruction processing or for data processing; a cache... Agent: Mcdermott Will & Emery LLP
20080016283 - Cache operation with non-cache memory: A system and method are provided for bypassing cache memory when reading data from system memory particularly when the primary memory could include memory types where the read operation mixes non-data with data. A system and method are provided for bypassing and invalidating cache memory when writing data to system... Agent: F. Drexel Feeling, Esq. Jones Day
20080016284 - Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction: According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.... Agent: Dillon & Yudell LLP
20080016285 - Disk array device, method for controlling the disk array device and storage system: A disk array device is equipped with a plurality of input/output channels that receive data input/output requests from an external device, a plurality of cache memories provided for the corresponding respective input/output channels, each of the cache memories connected to each of the corresponding respective input/output channels, a disk drive... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080016286 - Method, system and computer program product for data caching in a distributed coherent cache system: A data caching approach is provided for a distributed computing environment employing coherent data caching. The data caching approach includes dynamically deciding whether to associate a priority tag with requested data for a processing unit, wherein the priority tag is to be employed in deciding whether to hold the requested... Agent: Heslin Rothenberg Farley & Mesiti P.C.
20080016287 - Symbol rate hardware accelerator: A hardware accelerator includes a first buffer, a second buffer, address generator(s), a translation read-only memory (ROM), a cyclic redundancy check (CRC) generator, a convolutional encoder and a controller. The first and second buffers store information bits. The address generator(s) generate(s) an address for accessing the first buffer, the second... Agent: Volpe And Koenig, P.C. Dept. Icc
20080016288 - Address masking between users: Provided is a method for uniquely masking addressing to the cache memory for each user, thereby reducing risk of a timing attack by one user on another user. The method comprises assigning a first mask value to the first user and a second mask value to the second user. The... Agent: Hewlett Packard Company
20080016289 - External memory interface engine: A configurable device interface enhances the ability of a processor to communicate with other devices. The configurable device interface provides programmers with an efficient mechanism for communicating with a wide variety of external memories, each of which may have their own unique interface requirements. As a result, the configurable device... Agent: Brinks Hofer Gilson & Lione
20080016290 - Dynamic instruction and data updating architecture: A memory update engine provides flexible modification of data in memory. A processor may employ the update engine to update filter coefficients, special effects parameters, signal sample processing instructions, or any other instruction or data during processing. The update engine supports dynamic updating without requiring processor shutdown, thereby allowing the... Agent: Brinks Hofer Gilson & Lione
20080016291 - Information storage apparatus, information transfer method, information transfer system, program, and storage medium: An information storage apparatus transmits or receives information to or from another information processing apparatus in one of a plurality of data transfer modes. The information storage apparatus includes first storage means for storing the information; information transmission/reception control means for controlling transmission or reception of the information between the... Agent: Robert J. Depke Lewis T. Steadman
20080016292 - Access controller and access control method: An access controller includes an access control cache configured to store access control data that associates an address range with an access permission. The access control cache reads the access control data by selecting a cache line. A line decision device receives an object code of an assembler instruction to... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.
20080016293 - System and method for controlling the updating of storage device: Arrangements for controlling the updating of a storage device, which investigates the number of times that a lock waiting time exceeds an upper limit value to judge whether or not the number of times that the upper limit value has been exceeded exceeds a frequency threshold value; stops the reception... Agent: Antonelli, Terry, Stout & Kraus, LLP
20080016294 - Memory controller and method for optimized read/modify/write performance: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in... Agent: Martin & Associates, LLC
20080016296 - Data processing system: A data processing system includes: a processor; a first memory for storing data which is accessed by the processor; a second memory having an area in which transferred data is stored; and a data control section for making a data transfer section transfer data from the first memory to the... Agent: Mcdermott Will & Emery LLP
20080016295 - Reducing bitmap management overhead: A bitmap manager creates a cached copy of a bitmap and a shadow copy of a bitmap. The contents of the shadow copy are examined as are the bitmap cache to determine when it is necessary to write bitmap data to persistent storage. Extra bits are set or left set... Agent: Hogan & Hartson LLP
20080016297 - Multi-level memory architecture with data prioritization: In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location, different from the first memory location that is selected based on... Agent: Ibm Corporation
20080016299 - Cache memory, system, and method of storing data: A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority... Agent: Wenderoth, Lind & Ponack L.L.P.
20080016298 - Drawing resources: This disclosure relates to drawing within a computer environment using a drawing resource. The computer environment includes a managed code portion and a native code portion. The computer environment compares a draw parameter call value being passed from the managed code portion to the native code portion with a stored... Agent: Microsoft Corporation
20080016300 - Asynchronous replication with write concurrency grouping: A method for controlling write order in a remote data storage system used for asynchronous replication. The data backup method includes receiving writes issued concurrently by a host prior to any being completed. An async write manager, such as a software application on a storage controller or on a host,... Agent: Hogan & Hartson LLP
20080016302 - Method of mass duplication: A method for duplicating data of a source medium to a plurality of target media through a duplicator includes connecting the source medium and the target media to the duplicator. The duplicator transfers the data of the source medium to the target media in an order and repeatedly. The target... Agent: Birch Stewart Kolasch & Birch
20080016301 - System for backing up cache memory in a double backup server structure: The present invention is to provide a system for backing up cache memory in a double backup server structure, which comprises a first backup server having a first SAS controller; a second backup server having a second SAS controller; and a SAS channel for connecting said first and second SAS... Agent: Bacon & Thomas, PLLC
20080016304 - Method and system for creating and restoring an image file: An image file format and a method of creating and restoring an image file is provided by the present invention. The image file format includes a plurality of streams such as a control stream, a data stream, a bitmap stream, and a cluster map stream. An audit trail stream, properties... Agent: Lee & Hayes PLLC
20080016303 - Storage system and storage control device: A virtualization system, including: at least one first port coupled to at least one host system; at least one second port coupled to a plurality of storage systems; wherein the virtualization system is capable to control to perform processes of splitting a relationship between the first virtual volume and the... Agent: Antonelli, Terry, Stout & Kraus, LLP
20080016305 - Implementation of soft protections to safeguard program execution: A program executing on a computer system implements a soft protection by allocating a region of memory in the computer system, initializing a soft protection on a page in the region of memory, detecting a use of the page having the soft protection, receiving a signal from an operating system... Agent: Quarles & Brady LLP
20080016306 - Semiconductor memory device having ram and rom areas: A semiconductor memory having two different memory areas in one chip includes a memory cell array including a first variable memory area controlled to be accessible in at least first and second operation modes, and a second variable memory area controlled to be inaccessible in owe of the first and... Agent: Frank Chau, Esq. F. Chau & Associates, LLC
20080016307 - Storage device and storing method: In order to securely back up data that is recorded in a mobile storage device, a storage device that connects to an external device so as to communicate with the external device includes a switch for switching functions of a control section under the control, a section for holding unique... Agent: Antonelli, Terry, Stout & Kraus, LLP
20080016308 - Dynamic latency map for memory optimization: In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a plurality of data units is determined. Upon each occurrence of a predefined event, a memory latency for each of the plurality of memory locations is determined. After the predefined event, a... Agent: Robert R. Williams IBM Corporation, Dept. 917
20080016309 - Apparatus and method to set the signaling rate for a plurality of data storage devices: A signaling speed module wherein that signaling speed module sets the signaling rate for each of a plurality of data storage devices. In certain embodiments of the invention, the signaling speed module comprises a memory device encoded with a pre-determined signaling rate. In other embodiments of the invention, the signaling... Agent: Dale F. Regelman Chandler & Udall, LLP
20080016310 - Methods, apparatus and computer programs for scheduling stroage requests: Provided are methods, apparatus arid computer programs for scheduling storage input and/or output (I/O) requests. A method for scheduling storage access requests determines a request processing sequence calculated to maximize SLA-based revenues achievable from processing a number of requests. A storage controller includes a scheduler which implements a revenue-based scheduling... Agent: Frederick W. Gibb, Iii Mcginn & Gibb, PLLC
20080016312 - Method for managing data on removable storage devices in an electronic library: Methods for managing data from removable data storage devices are described. One method may include receiving at least two removable data storage devices of a first type in a removable data storage device reader, accessing directory information for the removable data storage devices and emulating a single removable data storage... Agent: Brinks Hofer Gilson & Lione
20080016311 - San/nas integrated management computer and method: A computer, which manages a SAN/NAS system, comprises a configuration information acquisition part, and a configuration association part. The configuration information acquisition part respectively acquires NAS host configuration information managed by a NAS host, and storage configuration information managed by a storage system. The configuration association part retrieves from storage... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080016313 - Methods and systems for achieving high assurance computing using low assurance operating systems and processes: A computing system contains and uses a partitioning microkernel (PMK) or equivalent means for imposing memory partitioning and isolation prior to exposing data to a target operating system or process, and conducts continuing memory management whereby data is validated by security checks before or between sequential processing steps. The PMK... Agent: Vern Maine & Associates
20080016314 - Diversity-based security system and method: The prevalence of identical vulnerabilities across software monocultures has emerged as the biggest challenge for protecting the Internet from large-scale attacks against system applications. Artificially introduced software diversity provides a suitable defense against this threat, since it can potentially eliminate common-mode vulnerabilities across these systems. Systems and methods are provided... Agent: Mcguirewoods, LLP
20080016316 - Method and system to indicate an exception-triggering page within a microprocessor: A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW)... Agent: Qualcomm Incorporated
20080016315 - Tagged translation lookaside buffers in a hypervisor computing environment: Tagged translation lookaside buffer consistency is enabled in the presence of a hypervisor of a virtual machine computing environment, in which multiple processes of multiple logical processors of guests are hosted by a virtual machine monitor or hypervisor component. The virtual machine monitor or hypervisor component maintains tagged TLB data... Agent: Woodcock Washburn LLP (microsoft Corporation)01/10/2008 > patent applications in patent subcategories. USPTO class listing
20080010393 - Adaptive thread id cache mechanism for autonomic performance tuning: An apparatus and method for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache. The apparatus temporarily splits a data cache into multiple regions and each region is selected according to a thread ID indicator in an instruction register.... Agent: Ibm Corporation
20080010394 - Devices and methods for storing and delivering music excerpts: Devices and methods for storing and retrieving information on demand wherein the information is associated with, for example, a compact disc or digital video disc.... Agent: Adam Bell
20080010395 - Performance optimization in solid-state media: A host device is coupled to a peripheral device such as a multi media card or the like, where the peripheral device includes a solid state data storage segment. The peripheral device has means for initiating a defragmentation function, such as registers for comparing a current performance measure against a... Agent: Harrington & Smith, PC
20080010396 - Apparatus and method for managing key in library apparatus: In order to facilitate the management of the hardware key of a library apparatus employing the LTO system, a write function of a noncontact memory (CM: cartridge memory) contained in an LTO tape cartridge is implemented in a medium carrying mechanism part of the library apparatus, and during an insertion... Agent: Staas & Halsey LLP
20080010397 - Flash memory with simulating system and method thereof: The invention presents a multi-type flash memory with simulating system and a method thereof. Meanwhile the method includes the steps of a) providing a simulating circuit data for the multi-type flash memory; b) transforming the simulating circuit data into a programmable circuit device; c) connecting a flash memory access interface... Agent: Yiannis Nicolaos Fragos
20080010398 - Storage system and write distribution method: A storage system includes: a flash disk having a plurality of flash memory units; a management table for hierarchically managing the write life of each flash memory unit on a specified storage area basis; and a controller for hierarchically distributing write-processing to the flash memory according to the management table.... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080010399 - Program control device and program control method: Disclosed is a program control device for managing cache information and generating an optimum linker option to thereby improve use efficiency of a cache memory. A cache line information generating section is formed which, when a target program is loaded into a main memory, generates cache line information. Therefore, the... Agent: Staas & Halsey LLP
20080010400 - Method and apparatus for automatically determining optimal access time of hard disk: A method for automatically determining an optimal access time in a hard disk, the method including determining an optimal access time of the hard disk based on an access time table in which optimal access times of the hard disk according to different environments are classified into a plurality of... Agent: Stein, Mcewen & Bui, LLP
20080010401 - Cache write integrity logging: An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver. In an embodiment, a non-volatile cache may be implemented by creating a device option read only... Agent: Schwegman, Lundberg & Woessner, P.A.
20080010402 - Disk array control device with an internal connection system for efficient data transfer: A disk array controller which includes a channel interface unit for connecting a host computer through a first type channel, a channel interface unit for connecting a host computer through a second type channel, a plurality of disk interface units provided with an interface with a magnetic disk unit respectively,... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080010403 - Raid apparatus, module therefor, disk incorporation appropriateness judgment method and program: A disk incorporation process unit 54 shares information (i.e., a common table) managed by a disk statistics unit 53 and judges whether or not to permit an incorporation of an installed disk by referring to the common table in the event of a discretionary disk having been isolated followed by... Agent: Staas & Halsey LLP
20080010404 - Information processing apparatus, storage medium supporting device, and identifier changing method: An information processing apparatus which makes it possible to accurately manage a plurality of storage media realized by cooperation with each other while maintaining a combination or combinations thereof, and manage data for each OS. A storage media supporting device removably supporting at least one storage medium is removably attached... Agent: Rossi, Kimms & Mcdowell LLP.
20080010406 - Apparatus and method for discerning a host interface: A system, apparatus and method are provided for discerning a host interface, the system including a host having at least one interface, a device in signal communication with the at least one interfaces an interface identifier for identifying a specification of the at least one interface, the interface identifier having... Agent: F. Chau & Associates, LLC
20080010405 - Selectable profiles and actions for removable memory devices: An invention is disclosed for creating selectable user profiles and associated actions for removable computer and/or electronics system memory devices. Specifically, a device, method and system are disclosed for using a software application to create and use selectable data profiles for information contained in a removable portable memory device, so... Agent: Gerald J. Iwanejko, Jr.
20080010407 - Buffered indexing to manage hierarchical tables: Buffered indexing for a computer's array such as a cache is used to synchronize parent entries with children and allow background invalidation (that is, suspending the invalidation should a new request of the array come in, resuming the invalidation after the request is satisfied) of the child entries. A method... Agent: International Business Machines Corporation
20080010410 - Cache memory storage: An improved caching method comprising: (a) employing circuitry to identify and analyze a plurality of data streams, each of said data streams resulting from a request to access a same content item stored in a cache; (b) calculating an initial access interval for said content item based upon said analyzing;... Agent: Ryan, Mason & Lewis, LLP
20080010408 - Cache reconfiguration based on run-time performance data or software hint: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not... Agent: Scully Scott Murphy & Presser, PC
20080010409 - Dynamic, on-demand storage area network (san) cache: Disclosed are apparatus and methods for facilitating caching in a storage area network (SAN). In general, data transfer traffic between one or more hosts and one or more memory portions in one or more storage device(s) is redirected to one or more cache modules. One or more network devices (e.g.,... Agent: Beyer Weaver LLP
20080010411 - Scsi-to-ip cache storage device and method: A SCSI-to-IP cache storage system interconnects a host computing device or a storage unit to a switched packet network. The cache storage system includes a SCSI interface (40) that facilitates system communications with a host computing device or the storage unit, and a Ethernet interface (42) that allows the system... Agent: Connolly Bove Lodge & Hutz LLP
20080010412 - Transmission apparatus, reception apparatus, transmission method, reception method, and integrated circuit: A reception apparatus is capable of correcting an error that occurs during communication according to serial communication that does not use error correction information. A repairing unit 122 in a reception circuit 117 generates two types of repaired blocks in which 1 and 0, respectively, are inserted into an error... Agent: Mcdermott Will & Emery LLP
20080010413 - Method and apparatus for application-specific dynamic cache placement: One embodiment of the present method and apparatus for application-specific dynamic cache placement includes grouping sets of data in a cache memory system into two or more virtual partitions and processing a load/store instruction in accordance with the virtual partitions, where the load/store instruction specifies at least one of the... Agent: Patterson & Sheridan LLP IBM Corporation
20080010414 - Method and apparatus for dynamic priority-based cache replacement: One embodiment of the present method and apparatus for dynamic priority-based cache replacement includes selectively assigning relative priority values to at least a subset of data items in the cache memory system, fetching a new data item to load into the cache memory system, the data item being associated with... Agent: Patterson & Sheridan LLP IBM Corporation
20080010415 - A pseudo lru tree-based priority cache: Exemplary embodiments include a method for updating an Cache LRU tree including: receiving a new cache line; traversing the Cache LRU tree, the Cache LRU tree including a plurality of nodes; biasing a selection the victim line toward those lines with relatively low priorities from the plurality of lines; and... Agent: Cantor Colburn LLP - IBM Rochester Division
20080010416 - Adaptive read ahead method of data recorded on a sequential media readable via a variable data block size storage device: A read request of a sequential media from a host is executed with a read request data block size equal to a maximum recorded data block size parameter of the variable data block size storage device. Subsequently, if warranted, an adaptive read ahead data block size variable is set to... Agent: Cardinal Law Group
20080010417 - Read/write permission bit support for efficient hardware to software handover: In one embodiment, a method comprises communicating with one or more other nodes in a system from a first node in the system in response to a trap experienced by a processor in the first node during a memory operation, wherein the trap is signalled in the processor in response... Agent: Lawrence J. Merkel Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20080010418 - Method for accessing a non-volatile memory via a volatile memory interface: Embodiments of the invention provide a method, devices, and system for accessing data in a nonvolatile memory device via a volatile memory device. In one embodiment, the method includes configuring a size and a base address of an overlay window within an address space of the volatile memory device. The... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda
20080010420 - Method for accessing control registers via a memory device: Embodiments of the invention provide a method, devices, and system for accessing remote control registers in a remote device via a volatile memory device. In one embodiment, the method includes receiving, by the volatile memory device via a volatile memory interface, a write command updating mirrored control registers within the... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda
20080010419 - System and method for issuing commands: Embodiments of the invention provide a method, devices, and system for issuing commands from a first device to a second device. In one embodiment, the method includes receiving, by the first device, a first command which writes a second command to a memory location within the first device. The second... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda
20080010423 - Network device and time synchronization method thereof: A network device is provided, the network device connected to a local exchange, and comprising a main interface system, a backup interface system, and a management system. The main interface system comprises a main transceiving module that receives an instruction from the local exchange, and transmits time information in the... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp
20080010421 - Snapshot expansion system and method thereof: A snapshot expansion system and a method, applicable to a logical volume manager, are provided. A snapshot space is allocated in a volume group space of a logical volume (LV) to create a snapshot. When a data write request is sent to the LV, the total capacity of the snapshot... Agent: Birch Stewart Kolasch & Birch
20080010422 - Storage system and method for managing data using the same: A storage apparatus enables efficient data restoration even if restoration is attempted using several different restoration points. The storage system is connected to a host apparatus, and includes a storage unit having various logical volumes formed therein and a controller configured to control I/O processing with respect to the storage... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080010424 - Remote copy system and control method thereof: This invention provides a control method of a remote copy system for establishing a disaster recovery system for transmitting data in database by a copy function between storage devices possessed by the storage device so as to minimize a public line necessary for the data transmission. In a remote copy... Agent: Stanley P. Fisher Reed Smith LLP
20080010426 - Processor system and processing method for operating system program in processor system: A processor system including a CPU core, a functional unit connected to the CPU core, and a plurality of register banks each having at least one system register storing at least one of control information and operation status of at least one of the CPU core and the functional unit... Agent: Mcginn Intellectual Property Law Group, PLLC
20080010425 - System for protecting sensitive data from user code in register window architecture: A system for protecting supervisor mode data from user code in a register window architecture of a processor is provided. The system, when transitioning from supervisor mode to user mode, setting at least one invalid window bit in the invalid window mask of the architecture additional to the invalid window... Agent: Silverbrook Research Pty Ltd
20080010427 - Method and apparatus for controlling access to storage device: The storage regions under command of a storage controller can be simply enabled and disabled to access to by automatically registering connected host computers. Such system can be achieved by taking a step of acquiring N_Port_Name information included in a login frame from the host computers, and a step of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20080010428 - Method and system for updating network flow statistics stored in an external memory: A method for updating a current network flow statistic stored in a memory device, comprising: storing a first statistic and a first address corresponding to a location in the memory device in a first stage of a multiple stage delay pipeline; shifting the first statistic and the first address to... Agent: Kramer & Amado, P.C.
20080010429 - Pipelined semiconductor memories and systems: The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900
20080010430 - Method and apparatus for freeing memory: A method of apparatus to free at least a portion of memory space of a memory device from at least a portion of a stored data block, wherein the freeing is based on the block sequence number of the stored data block and/or a quality indicator value related to at... Agent: Schwabe, Williamson & Wyatt, P.C.
20080010431 - Memory storage device and read/write method thereof: A memory storage device and a read/write method thereof, first defining logically the flash memory as at least one particular data management area and at least one common data management area; next, determining the logical block address located in the particular data management area or the common data management area... Agent: Rosenberg, Klein & Lee
20080010432 - System and method for thread creation and memory management in an object-oriented programming environment: A system and a method for thread creation where only copied threads share the same stack location for execution, so unrelated threads have individual stack space and can be executed concurrently in multi-processor system. Also, the copy operation of the stack frame is only necessary among the copied threads, so... Agent: Fenwick & West LLP
20080010433 - Method and apparatus for efficiently accessing both aligned and unaligned data from a memory: A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one... Agent: Ibm Corp (ya) C/o Yee & Associates PCPrevious industry: Electrical computers and digital data processing systems: input/output
Next industry: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
RSS FEED for 20130509:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: memory patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: memory patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: memory patents we recommend signing up for free keyword monitoring by email.
FreshPatents.com Support - Terms & Conditions
Results in 1.15847 seconds