Electrical computers and digital processing systems: memory inventions 08/07

20070204096 - Memory structure for optimized image processing: A memory architecture for image processing comprising a memory array having multiple multi-byte memory data paths of equal multi-byte data width, and a multiplexing structure connected to the output of the multiple multi-byte data paths, capable of selectively providing a multi-byte data path of a desired width containing a desired... Agent: Docket Clerk

20070204097 - Downloading system: A downloading system which can be used freely by many and unspecified persons. A recording medium is loaded in a public downloading apparatus, and use condition confirmation processing is performed by using information recorded on the medium. Processing for downloading various sorts of information using the public downloading apparatus is... Agent: Bell, Boyd & Lloyd, LLP

20070204099 - Methods for programming nand flash memory and memory system: A method of programming a memory system including a flash memory comprising; in response to a conventional data input command, sequentially executing an address mapping operation, an address input operation, a load data operation, and a program execution operation, or in response to a new data input command, sequentially executing... Agent: Volentine & Whitt PLLC

20070204100 - Storage apparatus using nonvolatile memory as cache and mapping information recovering method for the storage apparatus: A storage apparatus using a nonvolatile memory as a cache and a mapping information recovering method for the storage apparatus are provided. The storage apparatus includes a mapping information storage module which stores in the nonvolatile memory mapping information of the nonvolatile memory and a first physical block address allocated... Agent: Sughrue Mion, PLLC

20070204098 - Non-volatile memory having a multiple block erase mode and method therefor: A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with... Agent: Freescale Semiconductor, Inc. Law Department

20070204101 - Nonvolatile memory card: A nonvolatile memory card includes a nonvolatile memory, two or more nonvolatile memory card controllers, and a common memory controller. The nonvolatile memory stores data. The two or more nonvolatile memory card controllers have properties different from each other. The common memory controller is configured to commonly operate with the... Agent: Cooper & Dunham, LLP

20070204102 - Cache feature in electronic devices: The specification and drawings present a new method, system, apparatus and software product for increasing operation time in electronic devices (e.g., mobile electronic devices) by using a cache for a hard disk. By adding a read/write memory, e.g. a flash memory, to buffer the accesses from the hard disk, it... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070204103 - Infiniband boot bridge with fibre channel target: A data storage system comprises an InfiniBand port, a fibre channel port, and a controller. The InfiniBand port is operable to connect the data storage system to a computer, and the fibre channel port is operable to connect the data storage system to one or more fibre channel storage devices.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070204105 - System and method for remote raid configuration: A deployment module of a RAID deployment management system integrates vendor-specific RAID configurations into a vendor-independent infrastructure with a RAID configuration utility that translates vendor-specific formatted configuration information to vendor-independent formatted configuration information. A user interface determines a RAID configuration for a target information handling system from a unique identifier... Agent: Hamilton & Terrile, LLP

20070204104 - Transparent backup service for networked computers: In a specific embodiment, the present invention provides a method of providing transparent file backup service based on networked computers. The method includes establishing an online redundant array of independent disks (RAID) of a plurality of networked computers maintained by a central service controller on a server. The plurality of... Agent: Townsend And Townsend And Crew, LLP

20070204106 - Adjusting leakage power of caches: Methods and apparatus to adjust leakage power of a cache are described. In one embodiment, leakage power of a cache is adjusted based on the measured leakage power and a target leakage power value.... Agent: Caven & Aghevli LLC C/o Portfolioip

20070204107 - Cache memory background preprocessing: A cache memory preprocessor prepares a cache memory for use by a processor. The processor accesses a main memory via a cache memory, which serves a data cache for the main memory. The cache memory preprocessor consists of a command inputter, which receives a multiple-way cache memory processing command from... Agent: Wolf Greenfield & Sacks, P.C.

20070204108 - Method and system using stream prefetching history to improve data prefetching performance: Computer implemented method, system and computer program product for prefetching data in a data processing system. A computer implemented method for prefetching data in a data processing system includes generating attribute information of prior data streams by associating attributes of each prior data stream with a storage access instruction which... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070204109 - System, method and storage medium for prefetching via memory block tags: A method and system for memory management are provided. The system includes a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of recently accessed memory blocks, each tag corresponding to one of the memory blocks and including tag contents.... Agent: Cantor Colburn LLP-ibm Yorktown

20070204110 - Data processing system, cache system and method for reducing imprecise invalid coherency states: A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state... Agent: Dillon & Yudell LLP

20070204111 - Method and apparatus for reducing memory latency in a cache coherent multi-node architecture: A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache... Agent: Kenyon & Kenyon LLP

20070204112 - Low latency memory access and synchronization: A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing... Agent: Scully, Scott, Murphy & Presser, P.C.

20070204115 - Systems and methods for storage shuffling techniques to download content to a file: The present invention provides a comprehensive development platform and client-side technology for intelligent and cost-effective delivery of video, audio and broadband content over a network, such as the Internet, to desktop, mobile computing, and network connected devices. In one embodiment of the present invention, an intelligent delivery system (IDS) uses... Agent: Choate, Hall & Stewart LLP

20070204114 - Configurable hardware scheduler calendar search algorithm: Apparatus and method that schedules movement of packets within network devices, such as network processors, includes a calendar using a segmented hierarchical routine to identify the next packet to be moved from one of a plurality of flow queues.... Agent: Ibm Corporation

20070204116 - Memory arrangement: A memory arrangement includes an interface configured to transmit coding and/or decoding data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two... Agent: Dicke, Billig & Czaja

20070204113 - Method and system for reducing latency: Embodiments generally relate to a method of reducing latency and cost. A device access request is received in a memory of non-local node over a NUMA interconnect from a source node. The device access request is forwarded to an off-node controller from the memory of the non-local node. The device... Agent: Mh2 Technology Law Group (cust. No. W/red Hat)

20070204117 - Kernel and application cooperative memory management: Embodiments of the present invention provide a mechanism for an operating system and applications to cooperate in memory management. Applications register with the operating system for cooperative memory management. The operating system monitors the memory and determines a memory “pressure” related to the amount of demand for the memory. As... Agent: Mh2 Technology Law Group (cust. No. W/red Hat)

20070204118 - System and method of managing the memory content of a device: A method of managing the content of a digital video recorder (DVR) is disclosed. The method includes receiving digital content and accessing a memory device used for storing digital content. The received digital content is compared with previously stored digital content stored in the memory device. Based on the comparison,... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070204119 - Storage control device, and data migration method using storage control device: The storage control device of the present invention performs data migration without any increase of the load on a NAS control unit. A volume based on a FC disk and a volume based on a ATA disk are joined together, so as to create one virtual volume. An update manager... Agent: Stanley P. Fisher Reed Smith LLP

20070204120 - Managing set of target storage volumes for snapshot and tape backups: A mechanism using special properties on data containers of a snapshot backup allows the snapshot backup used for a tape backup to be excluded from the policy enforcement. In addition, reconciliation of a local (client-side) backup repository and server repository bypass the snapshot backup to ensure its validity for the... Agent: Canady & Lortz LLP- Ibm

20070204121 - Moveable locked lines in a multi-level cache: A processor includes a multi-level cache hierarchy where a lock property is associated with a cache line. The cache line retains the lock property and may move back and forth within the cache hierarchy. The cache line may be evicted from the cache hierarchy after the lock property is removed.... Agent: Intel Corporation C/o Intellevate, LLC

20070204122 - Multimedia three-dimensional memory (m3dm) system: Among all semiconductor memory technologies, three-dimensional memory (3D-M), particularly mask-programmable 3D-M (3D-MPM), has the largest storage capacity and is the only one that can store movies at a reasonable price. Accordingly, the present invention discloses a multimedia three-dimensional memory (M3DM).... Agent: Guobiao Zhang

20070204123 - Media library assembly that decreases time-to-data: A media library assembly (10) includes a host controller (12), a first data transfer assembly (18A) and a second data transfer assembly (18B), which can be remotely positioned from the first data transfer assembly (18A). The host controller (12) sends a first command signal to the first data transfer assembly... Agent: The Law Office Of Steven G Roeder

20070204127 - Memory allocation method for reducing memory fragmenting: A memory allocation method comprises: providing a memory, wherein a memory block of the memory has a first side and a second side; providing a memory controller; determining a memory allocation direction, wherein the first side is a starting point of a first allocation direction when the memory allocation direction... Agent: Birch Stewart Kolasch & Birch

20070204124 - Power saving method and system: The present invention relates to reduction of power consumption of electronic mass storage devices, and more particularly to such a reduction of power consumption in mobile infotainment products. These devices are equipped with a subsystem comprising a mass storage device (48) and a buffer memory (43, 44). The size of... Agent: Philips Intellectual Property & Standards

20070204126 - Reclaim algorithm for fast edits in a nonvolatile file system: A processing device stores fragmented files in a nonvolatile memory that are tracked in RAM as direct pointers. The initial file is stored in memory and data edits are stored in new memory locations and tracked as file offsets in the header structures associated with the memory blocks. The new... Agent: Intel Corporation C/o Intellevate, LLC

20070204125 - System and method for managing applications on a computing device having limited storage space: A device and method are provided for managing applications stored on a wireless device having limited storage space, wherein each application includes one or more components. Predefined criteria for each component are monitored. A trigger is generated in response to a trigger event. Components to be deleted are selected in... Agent: Gowling Lafleur Henderson LLP

20070204128 - Two-level ram lookup table for block and page allocation and wear-leveling in limited-write flash-memories: A restrictive multi-level-cell (MLC) flash memory prohibits regressive page-writes. When a regressive page-write is requested, an empty block having a low wear-level count is found, and data from the regressive page-write and data from pages stored in the old block are written to the empty block in page order. The... Agent: Stuart T Auvinen

20070204129 - Address converting apparatus: A first address conversion table stores first address data corresponding to a receiving buffer in a main memory from among address data stored in a page table. A second address conversion table stores second address data corresponding to an area other than the receiving buffer area in the main memory... Agent: Staas & Halsey LLP

20070204130 - Advanced processor translation lookaside buffer management in a multithreaded system: Advanced processors for executing software applications on different operating system are presented including: a number of processor cores each configured to execute multiple threads, wherein each of the number of processor cores includes a data cache and an instruction cache; a data switch interconnect ring arrangement directly coupled with the... Agent: Stevens Law Group

20070198764 - Semiconductor arrangement and method for operating a semiconductor arrangement: A semiconductor arrangement includes a first control unit, a second control unit and at least one memory module. Between the first control unit and the at least one memory module and between the second control unit and the at least one memory module, data can be transferred both in a... Agent: Slater & Matsil LLP

20070198765 - Use of nand flash for hidden memory blocks to store an operating system program: A memory device has a plurality of memory blocks utilized to store data. One of the blocks is used as a hidden memory block to store an operating system program, instead of data. The hidden memory block is designated as a bad block so that data will not be written... Agent: Garlick Harrison & Markison

20070198766 - Semiconductor memory and method for manufacturing a semiconductor memory: A semiconductor memory includes: a first memory cell transistor including: a first floating gate electrode provided on and insulated from the substrate; and a first control gate electrode provided on and insulated from the first floating gate electrode; and a second memory cell transistor including: a second floating gate electrode... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070198767 - Apparatus and method for controlling flash memory: Provided are an apparatus and method for controlling a flash memory, more particularly, an apparatus and method for controlling flash memory that updates control information of a flash memory stored in a predetermined volatile memory when the type of flash memory is changed and controls the changed flash memory using... Agent: Sughrue Mion, PLLC

20070198768 - Apparatus and method for operating flash memory according to priority order: Provided is an apparatus and method for operating a flash memory according to a priority order, in which a fast response is insured. The apparatus includes a time calculation unit which calculates an operation execution time required to perform a first operation, a remaining time calculation unit which calculates a... Agent: Sughrue Mion, PLLC

20070198769 - Method and apparatus for managing blocks according to update type of data in block-type memory: A method and an apparatus are provided for managing blocks according to the update type of data in block-type memory. The method includes receiving data to be stored from an application; determining an update frequency of the data; extracting information of nonvolatile memory space in which the data will be... Agent: Sughrue Mion, PLLC

20070198770 - Memory system and memory card: A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The... Agent: Miles & Stockbridge PC

20070198771 - Dynamic memory refresh controller, memory system including the same and method of controlling refresh of dynamic memory: A dynamic memory refresh controller includes a first in first out (FIFO) memory, a scheduler, a refresh control unit, and a signal generator. The FIFO memory stores and manages requests from a master device. The scheduler reorders the requests from the master device based on priorities assigned to the master... Agent: F. Chau & Associates, LLC

20070198772 - Automatic caching generation in network applications: Automatic software controlled caching generations in network applications are described herein. In one embodiment, a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses is identified, where the external memory accesses have a substantially identical base address. One or more... Agent: Blakely Sokoloff Taylor & Zafman

20070198775 - Automatic media readying system and method: One aspect of the invention is a method for automatically readying a medium. The method comprises monitoring a state of a storage medium using readying logic and determining a physical media type for the storage medium using the readying logic. The method also comprises determining a recorded type for the... Agent: Hewlett Packard Company

20070198773 - Data storage drive for automated data storage library: A method, system, and a device have a data storage drive for an automated data storage library in which a data storage drive may have in one embodiment, both a host-drive interface port and a host-library interface port. In one aspect, drive commands from a host system are conducted primarily... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20070198774 - Method and apparatus for implementing feedback directed deferral of nonessential dasd operations: A method, apparatus and computer program product are provided for implementing feedback directed deferral on nonessential direct access storage device (DASD) operations. A kernel DASD I/O manager maintains a queue depth count value for a DASD unit and maintains a busy flag that indicates when the queue depth count value... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070198776 - Optical disc drive controlling system: The present invention discloses an optical disc drive controlling system. The system includes: a first memory for storing at least a program code; and a control circuit for controlling operation of the optical disc drive controlling system. The control circuit includes: a communication interface coupled to the first memory for... Agent: North America Intellectual Property Corporation

20070198777 - Fractional caching: A microprocessor-based system generates an electronic document based on a set of microprocessor-readable instructions organized in logical units known as instruction nodes. Each instruction node includes at least one microprocessor-readable instruction. If an instruction node is eligible for caching, it is associated with a cache key value, which is compared... Agent: Moore, Hansen & Sumner Suite 4850

20070198778 - Enforcing memory-reference ordering requirements at the l2 cache level: One embodiment of the present invention provides a system that enforces memory-reference ordering requirements at an L2 cache. During operation, the system receives a load at the L2 cache, wherein the load previously caused a miss at an L1 cache. Upon receiving the load, the system performs a lookup for... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070198779 - System and method for cache management: Aspects of the invention relate to improvements to the Least Recently Used (LRU) cache replacement method. Weighted LRU (WLRU) and Compact Weighted LRU (CWLRU) are CPU cache replacement methods that have superior hit rates to LRU replacement for programs with poor locality, such as network protocols and applications. WLRU assigns... Agent: Bereskin And Parr

20070198780 - Apparatus, system, and method for determining prefetch data: An apparatus, system, and method are disclosed for determining prefetch data. A start module communicates a start of a target software process to a storage device. A learning module learns data blocks accessed for the target software process. In one embodiment, a prefetch module prefetches the learned data blocks in... Agent: Kunzler & Mckenzie

20070198781 - Methods and apparatus to implement parallel transactions: Cache logic associated with a respective one of multiple processing threads executing in parallel updates corresponding data fields of a cache to uniquely mark its contents. The marked contents represent a respective read set for a transaction. For example, at an outset of executing a transaction, a respective processing thread... Agent: Barry W. Chapin, Esq. Chapin Intellectual Property Law, LLC

20070198785 - Computer systems with lightweight multi-threaded architectures: Embodiments of the present invention provide a class of computer architectures generally referred to as lightweight multi-threaded architectures (LIMA). Other embodiments may be described and claimed.... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20070198784 - Data storage system, data storing method, and recording medium: A data storage system has a first storage unit and a second storage unit for storing the same data received from a plurality of higher-level devices. The first storage unit transmits sequence information representative of a sequence for storing the data received from the higher-level devices, to said second storage... Agent: Young & Thompson

20070198786 - Method for estimating and reporting the life expectancy of flash-disk memory: A method for managing a memory device, a memory device so managed and a system that includes such a memory device. A value of a longevity parameter of the device is monitored after a data operation on the device in which the monitoring is performed by the device. A grade... Agent: Dr. Mark Friedman Ltd. C/o Bill Polkinghorn

20070198782 - Memory controller: A memory controller for accessing a memory module comprising a plurality of memory banks. The memory controller is operable to write copies of program data to one or more memory banks according to the size of the program data. The memory controller is additionally operable to read program data, e.g.... Agent: Hewlett Packard Company

20070198783 - Method of temporarily storing data values in a memory: The present invention relates to a memory management unit (MMU) for storing data values, said memory management unit comprising a memory unit (IM) which is adapted to store temporarily at least two sets of data values; and a controller (CTRL) which is configured such that it is able to store... Agent: Philips Intellectual Property & Standards

20070198788 - Memory access methods: A memory access method is implemented in an electronic device comprising a main memory, a storage unit with a first bank and a second bank. Upon booting or resetting an electronic device, a first data set in the first bank is loaded to the main memory to be a second... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070198787 - Patching rom code: An instruction set is executed from Read Only Memory (ROM). When a current instruction in the instruction set corresponds to a reserved patch memory block of ROM, a Random Access Memory (RAM) index and a ROM return address are loaded into a memory map, and a program counter is set... Agent: Garlick Harrison & Markison

20070198790 - Computer system for copying data between virtual storage areas: It has been impossible in prior art to copy every piece of data that is stored in a virtual volume. A management computer of this invention receives a copy request that designates a real storage area as a copy source, selects a virtual storage area that is associated with plural... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070198791 - Multi-site remote-copy system: Two storage areas are created in a first storage subsystem, a synchronous remote copy is performed from a first storage area included in the first storage subsystem to a storage area included in a second storage subsystem, and an asynchronous remote copy is performed from a second storage area included... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070198789 - System to capture, transmit and persist backup and recovery meta data: A system to capture, transmit and persist backup and recovery meta data over a network (16). An agent (48) captures the meta data at a computerized backup management system (22). The agent transmits the meta data from the backup management system to a storage console portal system (30). And the... Agent: Beyer Weaver LLP

20070198793 - Application-based commit for local storage subsystems and remote storage subsystems: A system to protect data including a processor and a memory coupled to the processor to store instructions executable by a digital processing apparatus. The memory is operable to perform operations to protect stored data. The operations include receiving a write request for a current data input comprising input to... Agent: Cardinal Law Group

20070198792 - Methods and apparatus to implement parallel transactions: A computer system includes multiple processing threads that execute in parallel. The multiple processing threads have access to a global environment including different types of metadata enabling the processing threads to carry out simultaneous execution depending on a currently selected type of lock mode. A mode controller monitoring the processing... Agent: Barry W. Chapin, Esq. Chapin Intellectual Property Law, LLC

20070198795 - Application executing apparatus and application execution method: An application executing apparatus includes a connecting unit configured to receive connection of an external storage medium that stores therein an application and first medium identification information unique to the external storage medium. A storage unit stores therein permission information associated with the application and the first medium identification information.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070198794 - Optical disc, illegal copy finding system and method using optical disc, optical disc manufacturing apparatus and optical disc manufacturing method: An optical disc manufacturing apparatus (46) recording a BCA code constituted by plural marks and including a secret code which is modulated in a range capable of recognizing a position in a radial direction of an optical disc and/or a position in a track direction of the plural marks as... Agent: Bacon & Thomas, PLLC

20070198796 - Enhanced data integrity using parallel volatile and non-volatile transfer buffers: Method and apparatus for transferring data. The apparatus preferably includes a first volatile memory block, a second volatile memory block coupled to a non-volatile circular buffer, and a controller configured to direct first data to the first volatile memory block for subsequent transfer to a downstream block, such as a... Agent: David Lucents, Seagate Technology LLC Intellectual Property - Col2lgl

20070198798 - Storage control apparatus and method thereof: In a storage system having a first storage control apparatus and a second storage control apparatus, the first storage control apparatus has: a first memory; a second memory; an input/output control unit for data transfer information in the second memory; and a data transfer control unit having a data buffer... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070198797 - Systems and methods for migrating components in a hierarchical storage network: System and methods for selectively or automatically migrating resources between storage operation cells are provided. In accordance with one aspect of the invention, a management component within the storage operation system may monitor system operation and migrate components from storage operation cell to another to facilitate failover recovery, promote load... Agent: Brown, Rudnick, Berlack & Israels, LLP.

20070198799 - Computer system, management computer and storage system, and storage area allocation amount controlling method: To provide a computer system, a management computer and a storage system, and a storage area allocation amount controlling method for improving I/O performance of the host computer. In a computer system comprising a storage system comprising one or more storage devices with storage areas, a host computer which uses... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070198801 - Method of setting a storage device: A method of setting a storage device that a storage management program is built in an application system is used to set a disk label of the storage device and without specially developed application program is set between the application system and the storage device. Some command codes are set... Agent: Rosenberg, Klein & Lee

20070198800 - Storage system, virtualization method and storage apparatus: Provided is a highly-reliable storage system, virtualization method, and storage apparatus that are less burdensome settings-wise. The internal apparatus recognizes one or more logical devices defined in a host apparatus as being connected to a channel, based on an inquiry command sent from the host apparatus when the channel comes... Agent: Stanley P. Fisher Reed Smith LLP

20070198802 - System and method for allocation of organizational resources: System and methods for storing electronic data is provided, where the system comprises a storage manager component and a management module associated with the storage manager component. The management module is configured to receive information related to storage activities associated with one or more storage operation components within the storage... Agent: Brown, Rudnick, Berlack & Israels, LLP.

20070198803 - Storage system with alterable background behaviors: A method and apparatus associated with circuitry configured to perform a selected one of a plurality of different data integrity operations on stored data in relation to a manner in which the data are to be retrieved. In some embodiments a data storage device is partitioned into a plurality of... Agent: Fellers, Snider, Blankenship, Bailey & Tippens

20070198804 - Data processing system having address translation bypass and method therefor: In a data processing system a processor including processing logic performs data processing. An address translator that is coupled to the processing logic performs address translation and a method thereof. The address translator receives a logical address and converts the logical address to both a physical address and one or... Agent: Freescale Semiconductor, Inc. Law Department

20070198805 - Non-intrusive address mapping having a modified address space identifier and circuitry therefor: A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space identifier where the mapping modifier is based on at least one external signal generated outside the processor, using the effective address and... Agent: Freescale Semiconductor, Inc. Law Department

20070198806 - Memory management unit: A system and method for managing memory is disclosed. The system includes a computer memory array and a memory management unit accessible to the memory array. The memory management unit includes a plurality of parallel comparators. The comparators receive a virtual memory address and perform a comparison of the virtual... Agent: Toler Schaffer, LLP

20070198807 - Internally derived address generation system and method for burst loading of a synchronous memory: An address generation system and method is provided for internally storing and thereafter producing an address to be sent to a memory device. The address that is stored need not be sent from an external address bus at each clock cycle, but the processing can remain internal to the memory... Agent: Daffer Mcdaniel LLP

20070192529 - Multi-processor systems and methods thereof: Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the... Agent: Harness, Dickey & Pierce, P.L.C

20070192527 - Memory system: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a... Agent: Arent Fox PLLC

20070192528 - Semiconductor device: A semiconductor device includes an electrical circuit formed on a substrate; a level detector outputting a first level signal which has a signal level based on power supply voltage and which determines an operation of the electrical circuit; a command decoder decoding a command that is inputted from the outside,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070192533 - Apparatus and method for managing mapping information of nonvolatile memory: Provided is an apparatus and method for managing mapping information of a nonvolatile memory, in which a time period required for a request for access to a logic sector of the nonvolatile memory is minimized. The apparatus includes an extractor which extracts a logical sector mapped with each physical sector... Agent: Sughrue Mion, PLLC

20070192534 - Flash memory management system and apparatus: Provided are a flash memory management apparatus and method which divide blocks of a memory into data blocks and i-node blocks and respectively specify storage paths of data, which is stored in the data blocks, in the i-node blocks in order to easily access pieces of the data by searching... Agent: Sughrue Mion, PLLC

20070192532 - Efficient system and method for updating a memory device: A system and method for updating a binary image stored across a block-structured memory device, such as a flash memory device. From comparison of original and new images, an update package is generated which includes an encoded instruction set comprising COPY and ADD operations instructing the copying of source data... Agent: Smyrski Law Group, A Professional Corporation

20070192531 - Microcomputer: The present invention provides a microcomputer having a CPU, a flash ROM which stores programs or the like therein and a read controller which controls reading of the flash ROM. In the microcomputer, the flash ROM is partitioned by sectors. When a read address is designated, the flash ROM outputs... Agent: Nixon Peabody, LLP

20070192530 - Writing to flash memory: Writing to a page of flash memory may include receiving write commands that are substantially independent of an internal architecture of the flash memory. In certain embodiments, two operand flash commands are received at a flash controller from a remote controller. In various implementations, the writing process may further include... Agent: Fish & Richardson P.C.

20070192536 - Apparatus for accessing a computer-readable medium device: A computer system and method includes a computing device and an optical drive. The optical drive is accessed by the computing device to provide information. The information describes the optical drive's write capability, whether the drive executes a pre-determined write strategy, and a digital data extraction capability of the optical... Agent: Haynes And Boone, LLP

20070192535 - Method and apparatus for updating data on disk storage medium: The use of disk-assisted, dynamic databases is to be optimized. To this end, provision is made for new data intended to update an old stock of data to have a second index, relating to the new data, generated for them, and for said second index to be stored on the... Agent: Joseph J. Laks, Vice President Thomson Licensing LLC

20070192537 - Request processing order in a cache: A method and apparatus for preserving the processing order of some requests in a system is disclosed. The method may include blocking requests from executing based on a blocked count data field, blocking list data field, and a last request data field. The apparatus may include a system or a... Agent: Trop Pruner & Hu, PC

20070192538 - Automatic raid disk performance profiling for creating optimal raid sets: A method, information handling system, and software are disclosed for creating a RAID set from a plurality of hard disks. A performance profile for the plurality of hard disks is determined. The performance profile associated with each of the hard disks is stored at a location on the hard disk.... Agent: Baker Botts, LLP

20070192539 - Disk array system: A disk array system having first and second housings and a controller for controlling the first and second housings. Fiber channel hard disk drives are received in the first housing, and serial ATA hard disk drives are received in the second housing. When reading data stored in a serial ATA... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070192540 - Architectural support for thread level speculative execution: A method and apparatus for hardware support of the thread level speculation for existing processor cores without having to change the existing processor core, processor core's interface, or existing caches on the L1, L2 or L3 level. Architecture support for thread speculative execution by adding a new cache level for... Agent: Scully Scott Murphy & Presser, PC

20070192541 - Microarchitectural wire management for performance and power in partitioned architectures: A method for utilizing heterogeneous interconnects comprising wires of varying latency, bandwidth and energy characteristics to improve performance and reduce energy consumption by dynamically routing traffic in a processor environment.... Agent: Holme Roberts & Owen, LLP

20070192542 - Method of operating distributed storage system: An embodiment of a method of operating a distributed storage system includes reading m data blocks from a distributed cache. The distributed cache comprises memory of a plurality of independent computing devices that include redundancy for the m data blocks. The m data blocks and p parity blocks are stored... Agent: Hewlett Packard Company

20070192543 - Techniques to manage a flow cache: Techniques are described herein that may be used to invalidate all entries in a table. For example, the table may be a flow cache. For example, an expiry time may be associated with one or more entries in the table. The expiry time of an entry may be initially set... Agent: Intel Corporation C/o Intellevate, LLC

20070192544 - Method of operating replicated cache: An embodiment of a method of operating a replicated cache includes generating a timestamp. A unit of data is read from memory of the replicated cache. The replicated cache comprises a plurality of independent computing devices. Each independent computing device comprises a processor and a portion of the memory. Confirmations... Agent: Hewlett Packard Company

20070192545 - Low complexity speculative multithreading system based on unmodified microprocessor core: A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional... Agent: Scully Scott Murphy & Presser, PC

20070192546 - Control apparatus of storage unit, and method of controlling the control apparatus of storage unit: A control apparatus of a storage unit having a first and a second communication ports for conducting communication with a computer, a first and a second processors that control respectively the first and the second communication ports, first and second storage devices that store respectively a first and a second... Agent: Townsend And Townsend And Crew, LLP

20070192549 - Method of improving the detection of opening and method for reducing the booting time of a wireless terminal: Disclosed is a method for reducing booting time of a wireless terminal by decreasing the time taken for copying the codes of the NAND memory to the RAM, and thus shortening the time taken for readying the wireless terminal. The method includes executing a program counter of the code region... Agent: The Farrell Law Firm, P.C.

20070192550 - Adaptive granularity refinement in detecting potential data races: A method and apparatus are provided for detecting data races that overcome the limitations of the prior art. In some embodiments, this is accomplished by detecting a first access to an object, determining whether the first access is associated with a suspicious pattern, automatically refining a pattern detection granularity from... Agent: Woodcock Washburn LLP (microsoft Corporation)

20070192548 - Method and apparatus for detecting the presence of subblocks in a reduced-redundancy storage system: Method and apparatus for rapidly determining whether a particular subblock of data is present in a reduced-redundancy storage system. An aspect of the invention achieves this by hashing each subblock in the storage system into a bitfilter that contains a ‘1’ bit for each position to which at least one... Agent: Wilson Sonsini Goodrich & Rosati

20070192547 - Programmable processing unit: In general, in one aspect, the disclosure describes a processing unit that includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control... Agent: Blakely Sokoloff Taylor & Zafman

20070192553 - Backup apparatus and backup method: There is proposed a backup apparatus and a backup method capable of improving the cost performance of a storage apparatus. A backup volume having a capacity corresponding to at least the summation of the capacities of online volumes is created. The storage area of the created backup volume is divided... Agent: Sughrue Mion, PLLC

20070192552 - Dynamically determining and managing a set of target volumes for snapshot operation: Systems and methods for managing a backup process of a database are disclosed. Typically, one or more backup logical unit numbers (LUNs) are identified in a backup management file from one or more available LUNs identified in a universe file are allocated. The backup management file comprises a plurality of... Agent: Canady & Lortz LLP- Ibm

20070192551 - Method for mirroring data between clustered nas systems: Data of a global file system spread over multiple local NAS systems may be consolidated as a copy into a single remote NAS system. When remote copy is set up, the local NAS systems replace referrals within the global file system with directories and send these in place of the... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070192555 - Remote copy system: In a system in which data employed by a computer is stored in a storage system, the storage system transfers this data to another storage system and a copy of the data is maintained in the other storage system. The consistency of the copy is maintained even when data is... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070192554 - Storage system and storage control device: A first storage control device is provided with a virtual LU for showing a logical volume possessed by a second storage control device as if it were its own volume. When data processing requested from a host device is, for example, a specific processing of large load (such as direct... Agent: Reed Smith LLP Suite 1400

20070192556 - System and method for virtual tape management with creation and management options: Remote configuration and utilization of a virtual tape management system with creation and management options. At least one security administrator CPU is communicably attached to a virtual tape management CPU. A pair of disk drives is communicably attached to the virtual tape management CPU and to the security administrator. First... Agent: Head, Johnson & Kachigian

20070192557 - Disk array system and method for security: A disk array system includes a memory that stores first key data inherent to the disk array system, and a disk controller that controls data input/output to/from disk drives. Each of the disk drives includes a disk medium, and an HDD controller, the disk medium having a system area that... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070192558 - Virtualization controller and data transfer control method: System for controlling data transfer between a host system and storage devices. A virtualization controller implements the data transfer and includes first ports for connection with the storage devices, a second port for connection with the host system, a processor, and a memory configured to store volume mapping information which... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070192559 - Microcomputer and a semiconductor device: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070192560 - Storage controller: Provided is a storage controller that will not impair the operation of a storage control system even when a new storage area is added to a pool corresponding to an AOU volume. This storage controller includes a logical volume accessible by a host system; a pool associated with the logical... Agent: Stanley P. Fisher Reed Smith LLP

20070192562 - Storage management method and storage management system: There is provided a storage management system capable of utilizing division management with enhanced flexibility and of enhancing security of the entire system, by providing functions by program products in each division unit of a storage subsystem. The storage management system has a program-product management table stored in a shared... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070192561 - Virtual storage system and control method thereof: A virtual storage system is equipped with a plurality of storage systems and a virtualization device for virtualizing the plurality of storage systems logically into a single storage resource provided to a host computer. When one of the storage systems receives a command from the host computer, in the event... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070192563 - System and method for translating an address associated with a command communicated between a system and memory circuits: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.... Agent: Zilka-kotab, PC

20070192564 - Methods and arrangements for inserting values in hash tables: Methods and arrangements to insert values in hash tables are contemplated. Embodiments include transformations, code, state machines or other logic to insert values in a hash table stored in electronic memory by hashing a value to determine a home address of an entry in the hash table, the hash table... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20070186028 - Synchronized storage providing multiple synchronization semantics: A shared resource access control system having a gating storage responsive to a plurality of controls with each of the controls derived from an instruction context identifying the shared resource, the gating storage including a plurality of sets of access method functions with each set of access method functions including... Agent: Huffman Law Group, P.C.

20070186029 - Address assigning method, disk drive, and data writing method: Embodiments in accordance with the present invention enable a disk drive of an address system to write data normally, wherein track groups of different track widths are discretely disposed on the storage medium in a same disk drive and the dimensional relationship among physical block addresses of a sector is... Agent: Townsend And Townsend And Crew LLP

20070186030 - Fast random access dram management method: A method of fast random access management of a DRAM-type memory, including the steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request; comparing the address of the bank concerned by a current request... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070186032 - Flash memory systems with direct data file storage utilizing data consolidation and garbage collection: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where... Agent: Davis Wright Tremaine LLP

20070186033 - Nonvolatile memory wear leveling by data replacement processing: A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed... Agent: Miles & Stockbridge PC

20070186031 - Time efficient embedded eeprom/processor control method: In an embedded system with a processor and an EEPROM that provides an EEPROM BUSY signal if the EEPROM is in a write mode, a block-before-write subroutine is used to hold the processor before a write operation to the EEPROM. A detector circuit finds read functions that are to be... Agent: Schneck & Schneck

20070186034 - Semiconductor memory asynchronous pipeline: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to... Agent: Borden Ladner Gervais LLP

20070186035 - Content-addressable-memory device and method of controlling content addressable memory: A tag storing unit stores, in a plurality of entries, a plurality of tags corresponding to a plurality of addresses, a parity bit of each of the tags, and a reverse bit obtained by reversing the parity bit. A data storing unit stores a plurality of data corresponding to the... Agent: Staas & Halsey LLP

20070186036 - Random access memory (ram) based content addressable memory (cam) management: A Random Access Memory (RAM) based Content Addressable Memory (CAM) architecture is disclosed. In an implementation, the CAM architecture includes a CAM data structure associated with a RAM to store one or more tags and associated data values. Each of the tags includes one or more bit fields which are... Agent: Lee & Hayes PLLC

20070186037 - Method for controlling a data processing device: A method for controlling a data processing device connected to a computer via an interface wherein a device specific command is generated on the computer by an application program, the command is stored in a special file and is then transmitted by the computer to the device with the aid... Agent: Michael E Martin Gardere Wynne Sewell

20070186038 - Recording device and recording and reproducing device: To make content irreproducible in a recording device after a set expiration time, the recording device has a read/write unit for reading and writing data on a recording unit, the read/write unit having electric power supplied from an external power source, a clock containing a built-in battery, an input/output interface... Agent: Mcdermott Will & Emery LLP

20070186039 - Cache control method for hybrid hdd, related program, and hybrid disk drive using same: A cache control method for a hybrid hard disk drive (HDD) comprising a nonvolatile cache (NVC) and a hard disk. When the hybrid HDD is operating in a non-parallel mode of operation, the control method sequentially searches the NVC and then reads the hard disk for requested data, but when... Agent: Volentine & Whitt PLLC

20070186041 - Mass storage device, mass storage controller and methods for use therewith: A mass storage controller includes a packet filter module for receiving a packet containing an updated sector of a remote file allocation table from a host device. The packet filter module is further operable for scanning the updated sector contents to determine their state. The updated sector is written to... Agent: Garlick Harrison & Markison

20070186040 - Memory card, data processor,memory card control method and memory card setting: A memory card (1) includes a host interface (2) that transmits and receives a command and data to and from the data processor (50), a nonvolatile memory (7) that stores data, a controller (3) that controls the operation of the memory card, and a storage section (32) that stores specified... Agent: Greenblum & Bernstein, P.L.C

20070186042 - Systems and methods for sharing media in a computer network: A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device with at least a first storage policy copy and a second storage policy copy; copying, to the first piece... Agent: Knobbe Martens Olson & Bear LLP

20070186043 - System and method for managing cache access in a distributed system: Embodiments directed to novel systems and method for cache management in a distributed system are described. In one embodiment, a system comprises a plurality of processing nodes, each processing node comprising a functional unit and has a local memory directly coupled therewith. Each processing node, of the plurality of processing... Agent: Hewlett Packard Company

20070186044 - Symmetric multiprocessor system: Systems, methods, and device are provided for symmetric multiprocessor (SMP) systems. One method embodiment includes creating a child process for each processor in the SMP. An event address register (EAR) associated with each processor is used to record information relating to cache misses. The EAR records are analyzed for each... Agent: Hewlett Packard Company

20070186045 - Cache eviction technique for inclusive cache systems: A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the potential impact to other cache levels within the cache hierarchy.... Agent: Blakely Sokoloff Taylor & Zafman

20070186046 - Pseudo lru algorithm for hint-locking during software and hardware address translation cache miss handling modes: The present invention provides an improved way to calculate a replacement way within a processor cache that is effective with different combinations of hardware address translation cache miss handling, software address translation cache miss handling, and hint lock bits. For some embodiments, LRU bits used to select an entry for... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070186047 - Method, system, and program for demoting tracks from cache: Provided are a method, system, and program for destaging a track from cache to a storage device. The destaged track is retained in the cache. Verification is made of whether the storage device successfully completed writing data. Indication is made of destaged tracks eligible for removal from the cache that... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20070186048 - Cache memory and control method thereof: The cache memory in the present invention includes a prediction unit 39 which predicts, based on the progress of the memory access outputted from the memory, a line address which should be prefetched next. The prediction unit 39 includes: a prefetch unit 414 which prefetches data of the predicted line... Agent: Greenblum & Bernstein, P.L.C

20070186050 - Self prefetching l2 cache mechanism for data lines: Embodiments of the present invention provide a method and apparatus for prefetching instruction lines. In one embodiment, the method includes fetching a first instruction line from a level 2 cache, extracting, from the first instruction line, an address identifying a first data line containing data targeted by a data access... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070186049 - Self prefetching l2 cache mechanism for instruction lines: Embodiments of the present invention provide a method and apparatus for prefetching instruction lines. In one embodiment, the method includes fetching a first instruction line from a level 2 cache, identifying, in the first instruction line, a branch instruction targeting an instruction that is outside of the first instruction line,... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070186053 - Method and apparatus for enforcing memory reference ordering requirements at the l1 cache level: One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor. During operation, while executing instructions in a speculative-execution mode, the system receives an invalidation signal for a cache line at... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070186051 - Memory system and method for controlling the same, and method for maintaining data coherency: A memory system including a bus 10, 11, a memory 17, a memory controller 16, a first device 13 having a cache, and a second device 15, all connected to the bus, wherein the memory controller includes a buffer 20 for temporarily storing cache data and write data that the... Agent: Ibm Microelectronics Intellectual Property Law

20070186052 - Methods and apparatus for reducing command processing latency while maintaining coherence: In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least... Agent: Ibm Corporation Intellectual Property Law Dept. 917

20070186054 - Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag: A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track completion of invalidations. The central coherency controller reads snoop tags to identify sharing caches having... Agent: Stuart T Auvinen

20070186056 - Hardware acceleration for a software transactional memory system: A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines reference by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an... Agent: Intel Corporation C/o Intellevate, LLC

20070186055 - Technique for using memory attributes: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.... Agent: Intel Corporation C/o Intellevate, LLC

20070186057 - Small and power-efficient cache that can provide data for background dma devices while the processor is in a low-power state: Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected... Agent: Sawyer Law Group LLP

20070186058 - Create virtual track buffers in nvs using customer segments to maintain newly written data across a power loss: A method for storing customer data at a non-volatile storage (NVS) at a storage server. A track buffer is maintained for identifying first and second sets of segments that are allocated in the NVS. A flag in the track buffer identifies which of the first and second sets of segments... Agent: Scully, Scott, Murphy, & Presser

20070186059 - Shared/exclusive control scheme among sites including storage device system shared by plural high-rank apparatuses, and computer system equipped with the same control scheme: In a computer system where a site including a storage device system connected to high-rank apparatuses, via a network such as a SAN, and a site including a storage device system similarly connected to high-rank apparatuses via a network are connected to each other via an inter-high-rank-apparatuses network, arbitration-emulation software... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070186062 - Content control systems and methods: A control system comprises an interface configured to receive a content request from a request source wherein the content request identifies content stored on a storage medium. The control system also comprises a processing system coupled to the interface and configured to process the content request to determine when the... Agent: Setter Roche LLP

20070186060 - Method and apparatus for exploiting parallelism across multiple traffic streams through a single channel: Methods of obtaining, enqueueing and executing several memory transactions are described, where the memory transactions may be generated in a first order but executed in a second order. Despite the relaxed ordering, essential programming paradigms such as producer-consumer relationships are not affected. Chipsets and systems using the methods are also... Agent: Blakely Sokoloff Taylor & Zafman

20070186061 - Shared interface for components in an embedded system: Embodiments of the invention provide a method and apparatus for accessing a non-volatile memory controller and a volatile memory via a shared interface. In one embodiment, the method includes selecting one of the non-volatile memory controller and the volatile memory via shared control signals of the shared interface, wherein the... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070186063 - Portable electronic device: Content data is classified into a data block group of high priority and an other data block group of low priority related to a user's operation. When the content data is read from a storage unit to store it in a buffer memory, a preferential data block group is firstly... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070186064 - Apparatus and method of managing storage space through time-variant consumption estimation: An apparatus and a method for managing a storage space through time-variant consumption estimation. More particularly, an apparatus and a method for managing a storage space through time-variant consumption estimation that estimates consumption of an entire storage space when a user instructs program editing, program recording or reserved recording, and... Agent: Sughrue Mion, PLLC

20070186065 - Data storage apparatus with block reclaim for nonvolatile buffer: An embodiment of a data storage apparatus includes a storage medium, a flash memory buffer configured to store write data to be written in the storage medium, and a controller configured to compare the amount of unused space in the flash memory buffer to a first reference value, compare the... Agent: Marger Johnson & Mccollom, P.C.

20070186067 - Storage system and control method thereof: Upon receiving a primary/secondary switching command from a secondary host system, a secondary storage control device interrogates a primary storage control device as to whether or not yet to be transferred data that has not been remote copied from the primary storage control device to the secondary storage control device... Agent: Reed Smith LLP

20070186069 - Coordinating synchronization mechanisms using transactional memory: Transactional memory (TM) may be used in conjunction with various synchronization mechanisms, such as that copy a current version of an object, update the copy, and then cause the copy to become current atomically by changing a “current version” indicator. Software operations to modify an object may first make a... Agent: Robert C. Kowert Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070186066 - Fast verification of computer backup data: A backup method for a computer system that affords fast verification of source data written to backup media includes reading a portion of the source data from a source storage volume and generating a hash of the source data. The source data is written to the backup media as backup... Agent: Law Offices Of Barry N. Young

20070186068 - Network redirector systems and methods for performing data replication: Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is... Agent: Knobbe Martens Olson & Bear LLP

20070186070 - Computer operating system with selective restriction of memory write operations: A computer system and method that are useful for embedded operating systems, thin client computing applications and the like, protects memory blocks in a nonvolatile version of the system program used at startup (reboot), for example in flash memory. Write operations to protected memory blocks are intercepted. A potentially revised... Agent: Duane Morris, LLPIPDepartment

20070186072 - Memory systems capable of reducing electromagnetic interference in data lines: A memory system capable of reducing electromagnetic interference in data lines includes a memory controller and a synchronous semiconductor memory device. The memory controller controls the phases of write data strobe signals, which fetch write data transmitted through respective data lines. The synchronous semiconductor memory device receives the write data... Agent: Harness, Dickey & Pierce, P.L.C

20070186071 - Optimizing data bandwidth across a variable asynchronous clock domain: Embodiments of the present invention optimize data bandwidth across an asynchronous buffer in a system with a variable clock domain. A move signal may be asserted to transfer data associated with a command into the asynchronous buffer. After the data has been moved into the buffer, an acknowledge signal may... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070186073 - D-cache miss prediction and scheduling: A method and apparatus for D-cache miss prediction and scheduling is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070186074 - Multiple page size address translation incorporating page size prediction: Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page... Agent: Robert R. Williams IBM Corporation, Dept, 917

20070186075 - Clearing selected storage translation buffer entries based on table origin address: An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented... Agent: International Business Machines Corporation

20070180183 - Hologram retrieval method and holographic recording and reproducing apparatus: Provided is a hologram retrieval method and a holographic recording and reproducing apparatus for preventing an increase in SNR, a decrease in retrieval accuracy, or the retrieval itself from being made impossible, which would otherwise occur because of a small size of data used for retrieval. Digital information is recorded... Agent: Oliff & Berridge, PLC

20070180185 - Integrated circuit for receiving data: An integrated circuit for receiving data includes an input receiver circuit that is supplied with a data signal and a reference signal. The input receiver circuit converts the data signal into differential input control signals that are supplied to first and second signal paths. The first and second signal paths... Agent: Edell, Shapiro & Finnan, LLC

20070180184 - Semiconductor device and control method therefor: The present invention provides a semiconductor device and a method for controlling a semiconductor device having a memory cell array having a plurality of nonvolatile memory cells, the method including detecting the number of bits to be written as division data that is divided from data to be programmed into... Agent: Wagner, Murabito & Hao LLP

20070180186 - Non-volatile memory management: A host processor is coupled to a memory controller and configured to retrieve from the memory controller at least one attribute of at least one non-volatile memory device operatively coupled to the memory controller. A memory management policy is modified based on the attribute.... Agent: Fish & Richardson P.C.

20070180187 - Reducing power consumption by disabling refresh of unused portions of dram during periods of device inactivity: Power consumption of a mobile communication device is reduced by disabling refreshing of unused portions of DRAM. DRAM includes multiple separately refreshable memory refresh ranges (MRRs). A memory refresh manager (MRM) within the device's operating system identifies ranges of virtual memory that will not be used during subsequent sleep mode... Agent: Qualcomm Incorporated

20070180188 - Virtual path storage system and control method for the same: Provided is a storage system having improved access performance. The storage system includes: a hard disk drive, and a storage controller for reading/writing data from/to the hard disk drive, the storage controller including: at least one interface connected to a host computer through a network; and a plurality of processors... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070180189 - Disk array system, host interface unit, control method for disk array system, and computer program product for disk array system: A disk array system includes a dedicated cache memory, a first host computer exclusively using the dedicated cache memory, data for a dedicated disk being written to or being read from the dedicated cache memory. The disk array system is connectable to the first host computer and to a second... Agent: Mcginn Intellectual Property Law Group, PLLC

20070180190 - Raid systems and setup methods thereof: RAID (Redundant Arrays of Independent Disks) systems and setup methods thereof. At least a first group of disks is selected to create a RAID 5 architecture. A second group of disks within the first group is selected to create a RAID 1 architecture. The RAID 5 and RAID 1 architectures... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070180191 - Storage system and replication creation method thereof: In a storage system having a plurality of control units each connected with a plurality of disk units, it is provided that a replication is created in the volume of the disk units connected to different control units. The replication creation unit of a given control unit creates a replication... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070180192 - Cache memory observation device and method of analyzing processor: A cache miss judger judges a cache miss when a cache access is executed. An entry region judger judges which of a plurality of entry regions constituted with one or a plurality of cache entries in the cache memory is accessed by each of the cache accesses using at least... Agent: Mcdermott Will & Emery LLP

20070180193 - History based line install: Using local change bit to direct the install state of the data line. A multi-processor system that having a plurality of individual processors where each of the processors has an associated L1 cache, and the multi-processor system has at least one shared main memory, and at least one shared L2... Agent: Richard M. Goldman

20070180194 - Technique for data cache synchronization: A technique for synchronizing data caches. Data is maintained in the data caches as records. The records are associated with buckets which represent collections of one or more records. The buckets are collectively maintained in a synchronization set which represents a state of a data cache. A local entity synchronizes... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070180195 - Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations: A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally take many cycles, address translation requests may have faster access to the address... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1