Electrical computers and digital processing systems: memory inventions 02/07

20070043895 - Method and apparatus for row based power control of a microprocessor memory array: An apparatus, a method, and a computer program are provided to efficiently use a microprocessor array. Typically, microprocessor arrays can be divided into multiple subarrays. Also, in the conventional arrays, each of the subarrays were engaged when the microprocessor array is used. To alleviate the power consumed by the microprocessor... Agent: Ibm Corporation (cs) C/o Carr LLP

20070043896 - Virtualized measurement agent: Executing a monitor, in a memory region of a platform protected from access by programs executing in a partition provided on the platform, and the monitor executing an agent to measure a program executing in the partition to obtain a measurement.... Agent: Blakely Sokoloff Taylor & Zafman

20070043898 - Information processing system: An information processing system includes a host device, a storage device and a bus. The bus transmits data to which an error correction code is appended, between the host device and the storage device. The storage device includes a storage section that stores the data. The storage device writes and... Agent: Fildes & Outland, P.C.

20070043897 - Method and device for storing information: A method is described for writing an optical disc (2) having a user storage space (USS). The method comprising the steps of determining a reserved storage section (VRSS 80) of the user storage space (USS) for use by a specific application;—determining which parts (81) of said reserved storage section (VRSS... Agent: Philips Intellectual Property & Standards

20070043899 - Data transfer device and data transfer method: A data transfer device for transferring data from a first sector of a flash memory to a second sector of the flash memory, the data transfer device comprising: a reading unit that reads data from the first sector; and a writing unit that writes the data read by the reading... Agent: Arent Fox PLLC

20070043900 - Flash memory management method and flash memory system: A flash memory management method for effectively deleting a file and a flash memory system, the flash memory system including: a flash memory; and an interface determining whether a sensed sector write operation instructs a file system to delete a file by examining metadata of the file system and deleting... Agent: Stein, Mcewen & Bui, LLP

20070043901 - Optical disc recording system with shared non-volatile memory design: An optical disc recording system comprises a front-end volatile memory, a back-end non-volatile memory, and a front-end processor. The front-end volatile memory stores sector data. The back-end non-volatile memory stores front-end codes and back-end codes. The front-end processor downloads the front-end codes from the back-end non-volatile memory to the front-end... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070043902 - Dual work queue disk drive controller: Herein described is at least a method and system for improving the performance of a disk drive. A cache work queue and a disk work queue operate together as a dual work queue to facilitate efficient processing of one or more read/write operations performed by the disk drive. In a... Agent: Mcandrews Held & Malloy, Ltd

20070043903 - Data processing apparatus and method, control program therefor, and recording medium having program recorded thereon: A data processing apparatus for writing data to a recording medium having a predetermined file system configured therein includes the following elements: an insertion portion that removably holds the recording medium, the data processing apparatus writing data to the recording medium inserted in the insertion portion; an insertion/removal detector that... Agent: Hogan & Hartson L.L.P.

20070043904 - Semiconductor integrated circuit: It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second... Agent: Steptoe & Johnson LLP

20070043905 - Variable cache data retention system: A customizable cache discard policy is provided which reduces adverse consequences of conventional discard policies. In a data processing system, a cache controller invokes a cache data discard policy as the cache approaches its capacity. Using one possible policy, data having the shortest retrieval (fetch) time is discarded before data... Agent: Law Office Of Dan Shifrin, PC - Ibm

20070043906 - Method for data set replacement in 4-way or greater locking cache: A method and means are provided for increasing both the MMBR (minimum misses before replaceable) and MHBR (minimum hits before replaceable) parameters for a virtual 3-way cache, consisting of three unlocked sets, from one to two. Thus, a minimum of two accesses to the sets B, C and D would... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070043910 - Memory control apparatus executing prefetch instruction: A memory controller reads data from DRAM at a request from a plurality of masters. It includes a prefetch buffer for storing a result of a pre-reading operation, and a register for setting a specific master among a plurality of masters. When a master requests a read, the memory controller... Agent: Fitzpatrick Cella Harper & Scinto

20070043907 - Microprocessor with improved data stream prefetching: A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates load/store requests to transfer data between the system... Agent: Huffman Law Group, P.C.

20070043908 - Microprocessor with improved data stream prefetching: A microprocessor includes a hierarchical memory subsystem, an instruction decoder, and a stream prefetch unit. The decoder decodes an instruction that specifies a locality characteristic parameter. In one embodiment, the parameter specifies a relative urgency with which a data stream specified by the instruction is needed rather than specifying exactly... Agent: Huffman Law Group, P.C.

20070043909 - Microprocessor with improved data stream prefetching: A microprocessor coupled to a system memory has a memory subsystem with a translation look-aside buffer (TLB) for storing TLB information. The microprocessor also includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and an abnormal TLB access policy. The microprocessor... Agent: Huffman Law Group, P.C.

20070043915 - Conditional multistore synchronization mechanisms: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the... Agent: Robert C. Kowert Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070043912 - Multi-socked symmetric multiprocessing (smp) system for chip multi-threaded (cmt) processors: In one embodiment, a node comprises a plurality of processor cores, coherency control circuitry coupled to the plurality of processor cores, and at least one coherence unit coupled to the coherency control circuitry. Each processor core is configured to have a plurality of threads active and each processor core includes... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070043911 - Multiple independent coherence planes for maintaining coherency: In one embodiment, a node comprises at least one processor core and a plurality of coherence units. The processor core is configured to generate an address to access a memory location. The address maps to a first coherence plane of a plurality of coherence planes. Coherence activity is performed within... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070043914 - Non-inclusive cache system with simple control operation: A cache system includes a processing device operative to access a main memory device, a primary cache coupled to the processing device and accessible from the processing device at faster speed than the main memory device, and a secondary cache coupled to the processing device via the primary cache and... Agent: Staas & Halsey LLP

20070043913 - Use of fbdimm channel as memory channel and coherence channel: In one embodiment, a node comprises at least one memory control unit configured to couple to an industry standard memory interface for coupling to a memory; and at least one coherence unit configured to transmit and receive coherence messages to and from other nodes to maintain coherent memory among the... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070043916 - System and method for light weight task switching when a shared memory condition is signaled: A system and method for using a handler to detect asynchronous lock line reservation lost events, and switching tasks based upon whether a condition is true or a mutex lock is acquired is presented. A synergistic processing unit (SPU) invokes a first thread and, during execution, the first thread requests... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20070043917 - Storage system and storage control method without requiring formatting of storage device: Each storage unit is provided with a table for storing a corresponding unit ID and count value. The controller receives a formatting instruction specifying a first unit ID, and updates the count value on a table corresponding to the first unit ID. The controller receives a write command specifying a... Agent: Stanley P. Fisher Reed Smith LLP

20070043918 - Coordinated storage management operations in replication environment: A method, system, computer system, and computer-readable medium for maintaining up-to-date, consistent copies of primary data without the need to replicate modified data when the data were modified as a result of an operation that is not an application-driven write operation captured during replication. Selected storage management operations are performed... Agent: Eric A. Stephenson Campbell Stephenson Ascolese LLP

20070043919 - Information processing method and system: A plurality of storage devices connected to at least one host computer via a network is to be managed. Access information about accesses from the host computer to each of the storage devices is referred to; a storage area in the storage device that has low access efficiency is determined... Agent: Townsend And Townsend And Crew, LLP

20070043920 - Memory controller capable of locating an open command cycle to issue a precharge packet: A memory controller capable of locating an open command cycle for the purpose of issuing a precharge packet to extreme data rate (XDR) dynamic random access memory (DRAM) devices is disclosed. In response to a receipt of two request packets concurrently, a determination is made as to whether one of... Agent: Dillon & Yudell LLP

20070043922 - Memory system for selectively transmitting command and address signals: A system includes a memory controller adapted to output address signals, command signals and select signals; a plurality of memory modules; and a plurality of buses each corresponding to one of the memory modules. Each bus is adapted to transmit corresponding ones of the address signals, the command signals, and... Agent: Volentine Francos, & Whitt PLLC

20070043921 - Wave pipelined output circuit of synchronous memory device: Provided is a wave pipelined output circuit of a synchronous memory device. In the wave pipelined output circuit, paths for transferring data in a high frequency mode of the synchronous memory device are separated from paths for transferring the data in a low frequency mode of the synchronous memory device.... Agent: Mills & Onello LLP

20070043923 - Apparatus, system, and method for modifying data storage configuration: An apparatus, system, and method are disclosed for modifying storage configuration. A monitor module monitors a storage fullness of a storage configuration. If the storage fullness exceeds a policy threshold, a modification module modifies the storage configuration. If the storage fullness does not exceed the policy threshold, an analysis module... Agent: Kunzler & Associates

20070043924 - Method for controlling memory card and method for controlling nonvolatile semiconductor memory: A method for controlling a memory card which includes a nonvolatile semiconductor memory whose memory area includes a plurality of write areas is disclosed. A first area which is a part of the plurality of write areas is set in accordance with management executed by a first file system. The... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070043925 - Storage system: In a storage system having a plurality of virtualization apparatuses that allocate a storage area which a storage device has, form a plurality of virtual volumes, and process input-output from a host processor to one of the virtual volumes, a request for completing all the input-output being processed that is... Agent: Townsend And Townsend And Crew, LLP

20070043926 - System and method for limiting the size of a local storage of a processor: A system and method for limiting the size of a local storage of a processor are provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070043927 - Information reproducing apparatus, data management information obtaining method, data management information obtaining program, and storage medium: An information reproducing apparatus reproducing information of an information recording medium is disclosed. In the information recording medium, a record area is divided into a plurality of data areas. Also, data are recorded for each of the divided data areas. In addition, management information relating to the data recording is... Agent: Dickstein Shapiro LLP

20070043928 - Method and system for device address translation for virtualization: A method of improving USB device virtualization is proposed that allows giving virtual machines (VMs) direct access to USB devices with a combination hardware and software solutions. The USB host controller replaces device identifiers assigned by the VM with real device identifiers that are unique in the system. The real... Agent: Blakely Sokoloff Taylor & Zafman

20070043929 - System and method for responding to tlb misses: The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and... Agent: Hewlett Packard Company

20070038799 - Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (iommu): In one embodiment, an input/output memory management unit (IOMMU) comprises a cache to cache translation data from memory; and a control unit coupled to the cache. The control unit is configured to implement address translation and memory protection for memory requests sourced by one or more input/output (I/O) devices. The... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20070038797 - Methods and apparatus for invalidating multiple address cache entries: In a first aspect, a first method is provided for removing entries from an address cache. The first method includes the steps of (1) writing data to a register; and (2) removing a plurality of address cache entries from the address cache based on the data written to the register.... Agent: Ibm Corporation Intellectual Property Law Dept. 917

20070038798 - Selective replication of data structures: Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070038800 - Contiguous block addressing scheme: An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage... Agent: Leffert Jay & Polglaze, P.A.

20070038801 - Control circuit, electronic device using the same, and firmware update method: A control circuit for updating firmware includes a CPU for performing processing on the basis of firmware stored in a flash ROM and writes updated firmware, which is an updated new firmware, into a file system region of the flash ROM that is accessible to the user. Furthermore, the CPU... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20070038802 - System and method for configuration and management of flash memory: A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive... Agent: Rosenberg, Klein & Lee

20070038803 - Transparent sdram in an embedded environment: A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column address latch signals, among others. The... Agent: Jones Day

20070038804 - Testmode and test method for increased stress duty cycles during burn in: Embodiments of the invention provide a method, apparatus, and system for operating a memory device. In one embodiment, an inverted refresh command is received. In response to receiving the inverted refresh command, an all bank precharge command is issued. After the all bank precharge command is issued, an all bank... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070038805 - High granularity redundancy for ferroelectric memories: A scheme for dealing with or handling faulty ‘grains’ or portions of a nonvolatile ferroelectric memory array is disclosed. In one example, a grain of the memory is less than a column high and less than a row wide. A replacement operation is performed on the memory portion when a... Agent: Texas Instruments Incorporated

20070038806 - Selective information caching on disk drive: A non-mechanical persistent storage is provided for a mechanical storage device. The operating system instructs the mechanical storage device to cache ranges of data stored in the mechanical storage device in the non-mechanical persistent storage. The mechanical storage device then transfers the data to the non-mechanical persistent storage. When the... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070038807 - Reduced stress relaxation in elastomeric compression structures adapted for use with electrical components: Disclosed are enhanced methods and elastomeric compression structures utilizing embedded gas-filled gas-filled polymeric microspheres that are expanded in predefined conditions that are usable in electrical components for reducing stress relaxation.... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070038808 - Data storage system with complex memory and method of operating the same: A data storage system and a data storing method for the data storage system are provided. The data storage system includes a host unit, a storage unit, and a first input/output bus functioning as an interface between the host unit and the storage unit. The storage unit includes a non-volatile... Agent: Staas & Halsey LLP

20070038809 - Method and apparatus for aging data in a cache: A computer implemented method, apparatus, and computer usable code for managing cache data. A partition identifier is associated with a cache entry in a cache, wherein the partition identifier identifies a last partition accessing the cache entry. The partition identifier associated with the cache entry is compared with a previous... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070038810 - Optimizing cached access to stack storage: A processing device employs a stack memory in a region of an external memory. The processing device has a stack pointer register to store a current top address for the stack memory. One of several techniques is used to determine which portion or portions of the external memory correspond to... Agent: Marger Johnson & Mccollom, P.C.

20070038812 - Output cache manager: A web page is generated by locating an area in a website to place the page and selecting a template for the page. An output cache manager allows a user to attach a cache profile in the form of metadata to the template and the area in the website. The... Agent: Merchant & Gould (microsoft)

20070038811 - Playback system and method supporting improved trick mode performance for disc-based multimedia: A playback apparatus and associated method is disclosed for use in a reproducing system, the apparatus including a cache memory configured to store data read from a data source (1); a cache replacement unit (341) configured to identify certain of the data to be deleted from the cache memory (335)... Agent: Philips Intellectual Property & Standards

20070038813 - System and method for cache coherence: A system and a method for cache coherence are provided. The system includes a memory apparatus, a detector, a plurality of access-consumers and a plurality of pass-gates. At least one of the access-consumers is a processor having a cache. When the processor replaces the first data in cache with the... Agent: Jianq Chyun Intellectual Property Office

20070038814 - Systems and methods for selectively inclusive cache: Embodiments include systems and methods for selectively inclusive multi-level cache. When data for which memory coherency is designated is received from a process and stored into a lower level cache the data is copied into a higher level of cache. When the data is snooped it is snooped from the... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20070038816 - Ensuring data integrity in network memory: A first appliance for ensuring data integrity in network memory is disclosed. The first appliance includes a processor and a communications interface that communicates over a communication network with a second appliance of the network memory. The processor determines whether reconciliation between a first peer state information in the first... Agent: Carr & Ferrell LLP

20070038815 - Network memory appliance: A first appliance of a network memory includes a processor configured to receive data. The processor determines whether the data is locally accessible to a second appliance of the network memory and generates an instruction based on the determination in order that the second appliance obtain the data. The processor... Agent: Carr & Ferrell LLP

20070038817 - Memory access control in a multiprocessor system: Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and... Agent: O'shea, Getz & Kosakowski, P.C.

20070038818 - Routing interrupts in a multi-node system: A method, apparatus, system, and signal-bearing medium that, in an embodiment, detect a new task priority for a processor, where the processor is connected to a first node, find a home node for the processor via a cluster to which the processor belongs, and send the new task priority to... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070038819 - Storage system construction managing device and construction management method: The device of the present invention manages changes in the construction of a storage system in a unified manner, and optimally disposes resources. The servers are logically divided into a plurality of virtual servers, the switches are logically divided into a plurality of zones, and the storage devices are logically... Agent: Stanley P. Fisher Reed Smith LLP

20070038820 - System and method for obscuring hand-held device data traffic information: Increasing security for a hand-held data processing device with communication functionality where such a device includes an access-ordered memory cache relating to communications carried out by the device. The hand-held data processing device has a locked state that is entered by the device receiving or initiating a trigger. On occurrence... Agent: Dimock Stratton LLP

20070038822 - Copying storage units and related metadata to storage: Provided are a method, system, and program for copying storage units and related metadata to storage. A user data storage location includes user data and a metadata storage location includes metadata data for the user data. A first type of copy operation is performed to copy a at least one... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20070038824 - Data processing system: A data processing system includes at least a first storage system, a second storage system and a third storage system. The third storage system maintains a replication of data stored in the first storage system. When updating data in the first storage system, the first storage system updates the replication... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070038823 - Data replication from one-to-one or one-to-many heterogeneous devices: Embodiments of the system described herein can be implemented in a software application that runs on a host device or is embedded in a logic or memory device such as a gate array, EEPROM, a control, or dynamical system. The system embodiment allows a set of similar or dissimilar intelligent... Agent: Ingrassia Fisher & Lorenz, P.C.

20070038821 - Hard drive with integrated micro drive file backup: The present invention is directed to backing up temporal information in a primary storage memory of a computer system. A temporal backup memory is provided as being physically separate from a primary hard drive of the computer system, and removable coupled to a primary drive assembly with the primary hard... Agent: Rudolph J. Buchel Jr., Law Office Of

20070038825 - Remote copy system: In asynchronous remote copy, there is time difference between data update and remote copy in a primary storage system. The primary storage system loses data unreflected on a secondary storage system in disaster and cannot control the amount of data lost. The primary storage system obtains the data reflection state... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070038828 - Chip protection register lock circuit in a flash memory device: A chip protection register lock circuit uses a plurality of lock bits in a lock bit register. If the register contains N bits, N/2 bits of the register are coupled to an erase circuit and the remaining N/2 bits are coupled to a programming circuit. After the chip protection register... Agent: Leffert Jay & Polglaze, P.A.

20070038826 - Method and system for providing an energy efficient register file: A register file is disclosed. The register file includes a plurality of registers and a decoder. The decoder may be configured to receive an address for any one of the registers, and disable a read operation to the addressed register if data in the addressed register is invalid.... Agent: Qualcomm Incorporated

20070038827 - Use management method for peripheral device, electronic system and component device thereof: Managing the use of an optical disc drive by a program at high security. An OS of a host apparatus 100 sends one user certificate incorporating the policy information defining the use contents permissible for the optical disc drive 200 and a user key to the optical disc drive 200... Agent: Paul, Hastings, Janofsky & Walker LLP

20070038832 - Communication system of cascaded devices with a backup function and active/standby switchover method thereof: A communication system of cascaded devices with a backup function includes a line adapter with multiple inputs and multiple outputs. Wherein, the communication devices of adjacent levels are cascaded through the line adapter, in each communication device, the port of an active main control board which is connected to the... Agent: Harness, Dickey & Pierce, P.L.C

20070038831 - Memory module and memory system: A memory module includes a plurality of semiconductor memory devices, a plurality of module tabs and a memory buffer. The plurality of the semiconductor memory devices stores first data, wherein at least one of the plurality of the semiconductor memory devices has a lower latency. The plurality of the module... Agent: Mills & Onello LLP

20070038833 - Storage controller: A primary controller operates to transmit write data and a write time to a secondary controller in the earlier sequence of the write times after reporting a completion of a request for write to a processing unit. The secondary controller stores the write data and the write time transmitted from... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070038830 - Storage system and storage control method: A controller existing on a level above a media drive issues a first read command specifying a plurality of data blocks to the media drive, and upon detecting a time-out for the first read command, generates a second read command specifying a portion of the data blocks among the plurality... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070038829 - Wait aware memory arbiter: A memory arbiter in a processor system which can generate system level wait state to temporarily stop the clock to a processor is disclosed. The processor system comprises a memory, a processor, a memory arbiter and a clock controller. The memory arbiter generates a wait signal when the memory is... Agent: David I. Roche Baker & Mckenzie LLP

20070038834 - Method and system for managing the sending of data packets over a data path: The present invention relates to a method, and a respective system, and computer program product for sending data packets along a predefined data path, wherein the receipt of a packet is acknowledged within a predefined time delay that was preset and tuned according to the duration of the send process... Agent: International Business Machines Corporation

20070038835 - Device for transmitting data and method for the same: Techniques for a simple file system for facilitating file transmission are disclosed. According to one aspect of the techniques, a storage device comprises a memory, a creation module, a status record module and a data reading/writing module. The creation module creates a parameter block, a file allocated table, a root... Agent: Silicon Valley Patent Agency

20070038836 - Simulating partition resource allocation: A method, apparatus, system, and signal-bearing medium that, in an embodiment, simulate allocation of a simulated resource to simulated partitions in a simulated logically-partitioned computer and determine whether the allocation conflicts. The simulation may include summing amounts of the simulated resource for the simulated partition in an order, where the... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070038840 - Avoiding silent data corruption and data leakage in a virtual environment with multiple guests: In an embodiment, an input/output memory management unit (IOMMU) is configured to receive a completion wait command defined to ensure that one or more preceding invalidation commands are completed by the IOMMU prior to a completion of the completion wait command. The IOMMU is configured to respond to the completion... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20070038839 - Controlling an i/o mmu: In an embodiment, a computer system comprises a processor; a memory management module comprising a plurality of instructions executable on the processor; a memory coupled to the processor; and an input/output memory management unit (IOMMU) coupled to the memory. The IOMMU is configured to implement address translation and memory protection... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20070038837 - Merging identical memory pages: Multiple virtual addresses map to the same physical location in memory if it has been determined that they are all intended to access the same data. In one embodiment, such virtual addresses are identified, and correspondence information (such as from a translation table) is changed in order to ensure that... Agent: Woodcock Washburn LLP (microsoft Corporation)

20070038838 - Novelty detection systems, methods and computer program products for real-time diagnostics/prognostics in complex physical systems: Sensors are configured to repeatedly monitor variables of a physical system during its operation. A novelty detection system is responsive to the sensors and is configured to repeatedly observe into an associative memory, states of associations among the variables that are repeatedly monitored, during a learning phase. The novelty detection... Agent: Myers Bigel Sibley & Sajovec

20070038841 - Handling data writes copied from a remote data storage device: Handling ordered writes to a data storage device includes receiving a first chunk of data into slots of a cache of the data storage device and using a hash table to provide a correlation between cache slots containing data from the first chunk of data and locations of a logical... Agent: Muirhead And Saturnelli, LLC

20070033318 - Alias management within a virtually indexed and physically tagged cache memory: A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12 can be mapped to the same physical address PA. Aliasing management logic 10 permits multiple copies of... Agent: Nixon & Vanderhye, PC

20070033319 - Information processing system and memory controller for controlling operation of memories: An information processing system includes a plurality of memories grouped into a first memory group and a second memory group, a data processor transmitting a data access request to the memories, and a memory controller controlling data transfer between the data processor and the plurality of memories. The memory controller... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070033320 - Crypto pass-through dangle: A crypto pass-through dangle that enables various memory devices with USB interface to be conveniently inserted into or removed from with encryption/decryption function, which comprising: a housing, having an upper housing and a lower cover that can be mutually engaged together for forming a space, wherein the housing further comprises... Agent: Dougherty & Troxell One Skyline Place

20070033321 - Quick pick apparatus and method for music selection: Systems and methods for quick song selection on any of a plurality of networked, digital jukeboxes is provided. The Quick Pick feature provides for efficient song selection for a jukebox user preferably using a set of the most popular songs on a particular jukebox machine. Preferably, the system and method... Agent: Dickstein Shapiro LLP

20070033327 - Enhanced host interface: A memory system that is compatible with hosts using different protocols includes protocol adapters for the different protocols. Protocol adapters allow a common backend system to be used for data that is provided in different formats. A protocol adapter generates responses to a host and generates commands for a backend... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070033326 - Enhanced host interfacing methods: A memory system that is compatible with hosts using different protocols includes protocol adapters for the different protocols. Protocol adapters allow a common backend system to be used for data that is provided in different formats. A protocol adapter generates responses to a host and generates commands for a backend... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070033323 - Interfacing systems operating through a logical address space and on a direct data file basis: A re-programmable non-volatile semiconductor memory, such as flash memory, operates to store files with logical addresses including a unique file identifier and offsets of data within the file, termed direct data file storage. Data files generated by a host may be stored directly in such a memory through a file... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070033328 - Management of memory blocks that directly store data files: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where... Agent: Parsons Hsue & De Runtz LLP

20070033329 - Memory system with management of memory blocks that directly store data files: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where... Agent: Parsons Hsue & De Runtz LLP

20070033322 - Method for firmware variable storage with eager compression, fail-safe extraction and restart time compression scan: Firmware-based conversion methods for storing converted firmware variables in a firmware storage device, such as flash memory. Under one method, “eager” compression of firmware is performed. In response to a storage request, a determination is made to whether a compressor is available. If it is, the firmware variable is stored... Agent: Blakely Sokoloff Taylor & Zafman

20070033332 - Methods of managing blocks in nonvolatile memory: In a nonvolatile memory system that includes a block-erasable memory array, records are individually maintained for certain classifications of blocks. One or more lists may be maintained for the blocks, an individual list ordered according to a descriptor value. Such ordered lists allow rapid identification of a block by descriptor... Agent: Parsons Hsue & De Runtz LLP

20070033334 - Non-volatile memory card and transfer interruption means: A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a... Agent: Miles & Stockbridge PC

20070033333 - Non-volatile memory device, and control method of non-volatile memory device: In a memory cell array, aside from a normal-data storing region, a control-information storing region is also allocated, and the control-information storing region is composed of a predetermined number of control-information storing memory cells in each bit of control information, and same bit data is stored in the predetermined number... Agent: James Hao, Esq. Wagner, Murabito & Hao

20070033325 - Non-volatile memory with scheduled reclaim operations: In a non-volatile memory array, scheduling of reclaim operations to occur before a shortage of erased blocks arises avoids extended periods of reclaim that could exceed a time limit. A memory controller uses information regarding the data stored in the memory array to estimate the additional host data that may... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070033331 - Nonvolatile memory with block management: In a nonvolatile memory system that includes a block-erasable memory array, records are individually maintained for certain classifications of blocks. One or more lists may be maintained for the blocks, an individual list ordered according to a descriptor value. Such ordered lists allow rapid identification of a block by descriptor... Agent: Parsons Hsue & De Runtz LLP

20070033330 - Reclaiming data storage capacity in flash memory systems: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where... Agent: Parsons Hsue & De Runtz LLP

20070033324 - Scheduling of reclaim operations in non-volatile memory: In a non-volatile memory array, scheduling of reclaim operations to occur before a shortage of erased blocks arises avoids extended periods of reclaim that could exceed a time limit. A memory controller uses information regarding the data stored in the memory array to estimate the additional host data that may... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070033335 - Semiconductor memory card access apparatus, a computer-readable recording medium, an initialization method, and a semiconductor memory card: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a... Agent: Wenderoth, Lind & Ponack L.L.P.

20070033336 - Shared interface semiconductor memories: A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of memory devices. The memory bus is configured to alternatively couple the memory controller to the first memory... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070033337 - Configurable high-speed memory interface subsystem: A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access... Agent: Lsi Logic Corporation

20070033338 - Memory with address-differentiated refresh rate to accommodate low-retention storage rows: In a dynamic random access memory device, receiving refresh commands via a signaling interface and, in response to the refresh commands, refreshing a first row of storage cells at a first refresh rate and refreshing a second row of storage cells at a second, faster refresh rate.... Agent: Shemwell Mahamedi LLP

20070033339 - Memory with refresh cycle donation to accommodate low-retention storage rows: In a dynamic random access memory device, refreshing each normal-retention row of storage cells once per refresh interval, refreshing each low-retention row of storage cells more than once per refresh interval and refreshing each high-retention row of storage cells that is associated with a low-retention row of storage cells once... Agent: Shemwell Mahamedi LLP

20070033340 - System and method for providing content based anticipative storage management: A hierarchical storage management (HSM) system and method. A system is provided comprising: a data usage monitor for extracting data object information from data objects in a hierarchical storage complex that is managed by a content management system; a data relationship repository for storing data object information, wherein the data... Agent: Hoffman, Warnick & D'alessandro LLC

20070033342 - Disk array device, method for controlling the disk array device and storage system: A disk array device is equipped with a plurality of input/output channels that receive data input/output requests from an external device, a plurality of cache memories provided for the corresponding respective input/output channels, each of the cache memories connected to each of the corresponding respective input/output channels, a disk drive... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070033341 - Storage system for controlling disk cache: To eliminate duplicated caching in a storage system with plural disk cache partitions, which are obtained by dividing a disk cache. A storage system includes non-volatile medium that stores data; a disk cache that temporarily stores data to be stored in the non-volatile medium; a control unit that controls input... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070033343 - Storage control system and method: A first storage control system comprises a CHN connected to a LAN CN. The CHN comprises a NAS processor and I/O processor. The I/O processor judges whether all or a portion of block level data is to be stored in either a first storage control system or a second storage... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070033344 - Information processing device, data processing method and program: An information processing device includes: an interface to/from which a recording medium is attachable/detachable; a data storage device that stores data; a data extractor that extracts data recorded on the recording medium connected through the interface, with the data maintained in a data configuration of the recording medium; and a... Agent: Harness, Dickey & Pierce, P.L.C

20070033345 - Processor, data processing system and method for synchronizing access to data in shared memory: A processing unit for a multiprocessor data processing system includes a processor core and a lower level cache including a reservation logic that records reservations of the processor core. The reservation logic passes or fails store-conditional operations received from the processor core based upon whether the processor core has reservations... Agent: Dillon & Yudell LLP

20070033346 - Associative matrix methods, systems and computer program products using bit plane representations of selected segments: Associative matrix compression methods, systems, computer program products and data structures compress an association matrix that contains counts that indicate associations among pairs of attributes. Selective bit plane representations of those selected segments of the association matrix that have at least one count is performed, to allow compression. More specifically,... Agent: Myers Bigel Sibley & Sajovec

20070033347 - Interconnect transaction translation technique: A technique to reduce and simplify interconnect traffic within a multi-core processor. At least one embodiment translates two or more system operations destined for a processor core within a multi-core processor into a fewer number of operations to be delivered to the processor core and translates a response from the... Agent: Blakely Sokoloff Taylor & Zafman

20070033348 - Dual-port semiconductor memories: A random access memory system has a first processor, a second processor, and a memory device. The first processor is configured with an address port and the second processor is also configured with an address port. The memory device is configured with a dual port to alternatively interface with the... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070033352 - Limited use data storing device: Embodiments of methods and systems for controlling access to information stored on memory or data storage devices are disclosed. In various embodiments, methods of retrieving information from a data storage device previously deactivated by modification or degradation of at least a portion of the data storage device are disclosed.... Agent: Searete LLC Clarence T. Tegreene

20070033353 - Memory hub and method for memory sequencing: A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter communicates with a memory sequencer that adjusts its operation... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070033349 - Multi-mode wireless processor interface: A system and method of interfacing two processors. The method can include generating a read/write request at a first processor for accessing a memory that is not directly accessible by the first processor, receiving the read/write request at a second processor that has direct access to the targeted memory, completing... Agent: Foley & Lardner LLP

20070033350 - Ruined storage area marking and accessing method and system: A ruined storage area marking and accessing method and system are proposed. The method and the system are for use with a data storage unit having a plurality of storage areas, for providing the data storage unit with a ruined storage area marking and accessing function to constantly inspect ruined... Agent: Edwards & Angell, LLP

20070033351 - Semiconductor memory module unit for point-to-point data interchange: The invention describes a semiconductor memory module unit for P2P data interchange with a memory controller. Memory chips having different data widths can be arranged on the semiconductor memory module unit in such a way as to enable a tree-like branching by signal data transmission from a node-like memory chip... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070033354 - Large scale data storage in sparse tables: Each of a plurality of data items is stored in a table data structure. A row identifier and column identifier are associated with each respective data item, and each respective item is stored at a logical location in the table data structure specified by its row identifier and column identifier.... Agent: Morgan, Lewis & Bockius, LLP.

20070033355 - Computer system and method of managing status thereof: There is disclosed a data storage system used in a computer environment where there are plural host computers and plural storage array controllers. When a remote copy is made while assuring the order of writing across plural storage array controllers, one of the host computers gains copy information about all... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070033357 - Method and apparatus for increasing an amount of memory on demand when monitoring remote mirroring performance: A method and storage system for increasing an amount of memory in a queuing area on. The storage system includes first and second storage subsystems connected to each other via a path. A primary volume in the first storage subsystem and a remote secondary volume in the second storage subsystem... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070033356 - System for enabling secure and automatic data backup and instant recovery: A host-based system for enhancing performance for a computing appliance has a central processing unit, an operating system, a long-term disk storage medium, and a persistent low latency memory (PLLM). Writes to disk storage at random addresses are first made to the PLLM, which also stores a memory map of... Agent: Central Coast Patent Agency, Inc

20070033360 - Copy protection apparatus and method: Recording control with additional information superposed on data and recording control in response to a type of a recording medium on which data are recorded are disclosed. A recording apparatus for recording data onto a recording medium includes an identification data detection section for detecting identification data for identification of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070033359 - Storage system and storage control method for access exclusion control of each storage area unit comprising storage area of storage device: The lock construction portion of a storage system receives, from a host 101 or SVP, the number of hosts which is the number of hosts 101 actually connected to the storage system, and the number of groups which is the number of storage device groups among a plurality of storage... Agent: Stanley P. Fisher Reed Smith LLP

20070033358 - Storage system, storage access restriction method and computer program product: Provided is a storage system having one or more logical devices mapped to a virtual device provided in a mapping destination storage system, and a storage controller for controlling the reading and writing of data from and to the logical devices. Upon receiving a reserve command from the mapping destination... Agent: Stanley P. Fisher Reed Smith LLP

20070033361 - Apparatus, system, and method for fastcopy target creation: An apparatus, system, and method are disclosed for autonomically creating a target volume in conjunction with a fastcopy data operation. The apparatus includes a selection module, a creation module, and a write module. The selection module selects a source volume from a source pool. The creation module creates a target... Agent: Kunzler & Associates

20070033362 - Mass data storage system: System and method for transferring data between a host system and a data storage system is provided. The system includes an interface that uses a file based protocol to transfer data between the data storage system and the host system, wherein the data storage system includes a first mass storage... Agent: Klein, O'neill & Singh, LLP

20070033363 - Method for reading while writing to a single partition flash memory: A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient time available to perform the requested operation. If there is sufficient time available and the device manager is in an exclusive mode, the state of... Agent: Leffert Jay & Polglaze, P.A.

20070033364 - Information recording medium, information recording medium accessing apparatus and accessing method: An information recording medium such as a semiconductor memory card includes a first semiconductor memory having a first recording area accessed by a relatively small access unit and storing file system management information, a second semiconductor memory having a second recording area accessed by a relatively large access unit and... Agent: Greenblum & Bernstein, P.L.C

20070033367 - Memory manager for heterogeneous memory control: Embodiments of a method and system for heterogeneous memory control are disclosed. The embodiments include components of a Memory Manager that receive usage information of a memory subsystem of a host system, the memory subsystem including internal memory and external memory. The Memory Manager also receives client information of one... Agent: Courtney Stanford & Gregory LLP C/o Intellevate

20070033365 - Method and apparatus for detecting memory leaks in computer systems: A system that identifies processes with a memory leak in a computer system. During operation, the system periodically samples memory usage for processes running on the computer system. The system then ranks the processes by memory usage and selects a specified number of processes with highest memory usage based on... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070033366 - Method, apparatus, and computer program product for reconfiguring a storage area network to support the execution of an application automatically upon execution of the application: A method, apparatus, and computer program product are disclosed for reconfiguring a storage area network (SAN) to support the execution of an application automatically upon execution of the application. A data set is generated for the application that identifies types of SAN devices that are necessary in order for the... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070033369 - Reconfigurable integrated circuit device: A reconfigurable integrated circuit device which is dynamically constructed to be an arbitrary operation status based on a configuration data, has a plurality of clusters including operation processor elements, a memory processor element, and an inter-processor element switch group for connecting the elements in an arbitrary status; an inter-cluster switch... Agent: Arent Fox PLLC

20070033368 - Storage resource management method for storage system: Provided is a computer system including a storage subsystem, a host computer, and a management computer for managing the storage subsystem and the host computer. The storage subsystem manages a storage extent by a group unit and creates storage extent configuration information. The management computer stores group management information, obtains... Agent: Townsend And Townsend And Crew, LLP

20070033370 - Continuous data protection: A method for continuous data protection in a storage system, including receiving a first write command to write first data to a partition of a logical volume and then generating a first partition descriptor record (PDR) having a first timestamp. The method further includes storing the first data at a... Agent: Katten Muchin Rosenman LLP

20070033371 - Method and apparatus for establishing a cache footprint for shared processor logical partitions: A computer implemented method, apparatus, and computer usable code for managing cache information in a logical partitioned data processing system. A determination is made as to whether a unique identifier in a tag associated with a cache entry in a cache matches a previous unique identifier for a currently executing... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070033372 - Windowing external block translations: A buffer of block addresses for use by a client for read and write operations in a client-server system is maintained. Block addresses are maintained in the buffer and are streamed to the client in response to a request for the addresses to support a read or write operation. The... Agent: Lieberman & Brandsdorfer, LLC

20070033376 - Data consolidation and garbage collection in direct data file storage memories: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where... Agent: Parsons Hsue & De Runtz LLP

20070033377 - Data operations in flash memories utilizing direct data file storage: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where... Agent: Parsons Hsue & De Runtz LLP

20070033378 - Flash memory systems utilizing direct data file storage: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where... Agent: Parsons Hsue & De Runtz LLP

20070033375 - Indexing of file data in reprogrammable non-volatile memories that directly store data files: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where... Agent: Parsons Hsue & De Runtz LLP

20070033373 - Method and system for dual mode access for storage devices: A method and system for reading data from a non-volatile mass storage device is provided. The method includes, performing logical configuration for the non-volatile mass storage device, wherein file data is allocated addresses in a virtual logical address space; and data identified by virtual logical addresses is read by a... Agent: Klein, O'neill & Singh, LLP

20070033374 - Reprogrammable non-volatile memory systems with indexing of directly stored data files: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where... Agent: Parsons Hsue & De Runtz LLP

20070028026 - Digital multimedia transfer rate controlling: An apparatus that includes a controller to regulate a rate of transfer of MPEG transport stream packets from a first storage device to a second storage device based on transfer rate control information derived from at least some of the MPEG transport stream packets. For example, the transfer rate control... Agent: Fish & Richardson PC

20070028027 - Memory device and method having separate write data and read data buses: A synchronous dynamic random access memory (“SDRAM”) device includes several banks of memory cell coupled to a read data path and a write data path. The read data path includes a read latch that stores a relatively large number of read data bits received in parallel from a bank of... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070028028 - Semiconductor memory chip and memory system: In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070028030 - Device for transmitting data between memories: An apparatus for data transmission between memories has a memory controller as well as a memory protocol controller. In one embodiment, a first memory controller is operatively connected to a first memory, and a memory protocol controller is operatively connected between the first memory controller and a second memory, wherein... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070028029 - Method and apparatus for data transfer: A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second... Agent: Ati Technologies, Inc. C/o Vedder Price Kaufman & Kammholz, P.C.

20070028034 - Computer system: A computer system is provided, wherein a storage device having a flash memory as the main medium is given a cache memory with a high hit rate even in a small capacity and less access overheads, high-speed writing to the flash memory is attained, and the number of rewriting is... Agent: Rader Fishman & Grauer PLLC

20070028033 - Method for identifying data characteristics for flash memory: A highly efficient data characteristic identification method for flash memory is provided, including the steps of: (a) based on the LBA corresponding to the write request to the flash memory, finding K corresponding counters in the hash table through K hash functions; (b) determining whether to perform decay period computation... Agent: Rosenberg, Klein & Lee

20070028032 - Nonvolatile memory and electronic device for use therewith: A nonvolatile memory may include a count data region provided in a memory region which is counted up according to an updating data and a fiat number of times managing region provided in a memory region which manages the full-counted number of times of the count data region. The nonvolatile... Agent: Reed Smith, LLP Attn: Patent Records Department

20070028035 - Storage device, computer system, and storage system: A storage device enabling realization of a new storage configuration enabling apparent elimination of the overhead and enabling high speed access all the time particularly when constructing a high parallel configured high speed flash memory system, that is, a storage device having a flash memory as a main storage and... Agent: Rader Fishman & Grauer PLLC

20070028036 - Top/bottom symmetrical protection scheme for flash: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can comprise an array of memory cells having N addressable sectors, and control circuitry to control erase or write operations on the array... Agent: Leffert Jay & Polglaze, P.A.

20070028031 - Universal nonvolatile memory boot mode: In accordance with a universal nonvolatile memory boot mode, one or more portions of boot code are obtained from a nonvolatile memory component. These one or more portions are obtained without knowing a row size used by the nonvolatile memory component, a column address strobe (CAS) latency used by the... Agent: Lee & Hayes, PLLC C/o Portfolioip

20070028037 - Memory system with automatic dual-buffering: A memory device having a dual buffering scheme between a host and a memory core may include an address generator to automatically generate first and second addresses in response to an initial buffer-sector address. The host may access the dual buffer in response to the first address, while the memory... Agent: Marger Johnson & Mccollom, P.C.

20070028038 - Data processing system: The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a... Agent: Philips Intellectual Property & Standards

20070028039 - Controlling a searchable range within a network search engine: Controlling a searchable range within a network search engine. A CAM array is provided within the network search engine to store data values in entries having respective addresses and to compare the data values with a search key. First address and a second addresses that define a range of the... Agent: Shemwell Mahamedi LLP

20070028040 - Mass storage accelerator: A data storage device is provided. A disk device is combined with a non-volatile memory device to provide much shorter write access time and much higher data write speed than can be achieved with a disk device alone. Interleaving bursts of sector writes between the two storage devices can effectively... Agent: Beyer Weaver & Thomas, LLP

20070028041 - Extended failure analysis in raid environments: Systems, apparatuses, and methods are described for performing diagnostic testing in a RAID environment in response to a failed memory access request to determine if a hard drive within the RAID failed.... Agent: Lsi Logic Corporation

20070028043 - Method for creating a large-scale storage array system out of multiple mid-range storage arrays: Disclosed is a method for creating a large-scale storage array by combining multiple mid-range storage arrays via a host based aggregation engine software application. Each mid-range storage array, also call a storage building block, consists of one or more RAID volumes. Each mid-range storage array has equivalent configuration and property... Agent: Lsi Logic Corporation

20070028045 - Method for improving writing data efficiency and storage subsystem and system implementing the same: The invention relates to a method, a storage subsystem and system for improving data writing efficiency. When writing data, if a predetermined N number of data or fewer than the predetermined N number of data are yet written after waiting a specific time period, the data writing I/O request is... Agent: Birch Stewart Kolasch & Birch

20070028042 - Methods and structure for improved import/export of raid level 6 volumes: Methods and structure for improved import/export of RAID level 6 logical volumes in subsystems supporting RAID level 5 but not level 6. When a RAID level 6 logical volume is imported into a RAID level 5 storage subsystem, features and aspects hereof re-map the logical volume for use as a... Agent: Lsi Logic Corporation

20070028044 - Methods and structure for improved import/export of raid level 6 volumes: Methods and structure for improved import of RAID level 6 logical volumes into subsystems devoid of RAID level 6 hardware support. When a RAID level 6 logical volume is exported from a first storage subsystem and imported into a second storage subsystem devoid of RAID level 6 hardware support, features... Agent: Lsi Logic Corporation

20070028046 - Flash device to external storage adapter: Embodiments of the present invention provide an adapter that allows a Universal Serial Bus (USB) storage device to be connected into a port designed for a flash memory device. The adapter may connect to the USB storage device via a wired or wireless connection.... Agent: Min, Hsieh & Hack LLP C/o Portfolioip

20070028047 - Correction of incorrect cache accesses: The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store... Agent: Nixon & Vanderhye, PC

20070028048 - Early data return indication mechanism: One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests from instruction sources, schedules the requests, and then passes the requests on to an execution unit having... Agent: Intel/blakely

20070028049 - Id anti-collision method using data structure applied to rfid system: An identification (ID) anti-collision method using a data structure to be applied to a radio frequency identification (RFID) system, includes transmitting an ID transmission request command from the reader to the tags using a predetermined request value; determining whether the IDs of the tags collide with one another, based on... Agent: Sughrue Mion, PLLC

20070028050 - Instruction cache having fixed number of variable length instructions: A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each instruction in the line, and hence the span of memory the instructions occupy, is not known, the address of the next following... Agent: Qualcomm Incorporated

20070028051 - Time and power reduction in cache accesses: The application discloses a data processor operable to process data, said data processor comprising: a cache having a data item storage location identified by an address; a hash value generator operable to generate a hash value from at least some of said bits of said address said hash value having... Agent: Nixon & Vanderhye, PC

20070028052 - Method and apparatus for maintaining cached state data for one or more shared devices in a logically partitioned computer system: A logically partitions computer system maintains a respective window for each of multiple cached state values which are subject to change. Where an individual change to a cached state value does not cause it to stray outside its window, then the change is made only to the cached state value,... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070028053 - System and method for dynamically adjusting the caching characteristics for each logical unit of a storage array: A system and method is disclosed for the adaptive and dynamic adjustment of the characteristics of a cache on a basis that is specific the operation of each logical unit. A storage controller may include a cache. The cache is subdivided so that a portion of the cache is associated... Agent: Roger Fulghum Baker Botts L.L.P.

20070028054 - Method and system for time-weighted cache management: Disclosed is a technique for managing memory items in a cache. An “age-lock” parameter is set to protect the newer memory items. When an incoming memory item (such as a history block header) is to be added to the cache, the amount of free space in the cache is checked.... Agent: Leydig Voit & Mayer, Ltd

20070028055 - Cache memory and cache memory control method: A cache memory of the present invention includes: for each cache entry, way 0 to way 3 which hold use flags U indicating whether or not the use flags U have been accessed; and a control unit which: updates, when a cache entry is hit, a use flag U corresponding... Agent: Greenblum & Bernstein, P.L.C

20070028056 - Direct-update software transactional memory: A transactional memory programming interface allows a thread to directly and safely access one or more shared memory locations within a transaction while maintaining control structures to manage memory accesses to those same locations by one or more other concurrent threads. Each memory location accessed by the thread is associated... Agent: Microsoft Corporation Attn: Patent Group Docketing Department

20070028057 - Logical unit security for clustered storage area networks: A system is described in which a plurality of host computers are coupled to a storage system for storing and retrieving data in the storage system. The storage system includes individually addressable units of storage such as volumes or logical unit numbers. A security management system controls access to each... Agent: Townsend And Townsend And Crew, LLP

20070028060 - Low power memory device: In a memory device having a memory core and a signal interface, receiving a command that specifies at least a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data between the signaling interface and an external... Agent: Shemwell Mahamedi LLP

20070028059 - Method of operating a memory device, memory module, and a memory device comprising the memory module: There is provided a method of operating a memory device comprising at least one memory module, a corresponding memory module and a memory device comprising the at least one memory module. It is proposed that in the memory module (100a, 100b, 100c, 100d) a command and write data signal (CA,... Agent: Maginot, Moore & Beck Bank One Tower

20070028058 - System for determining the position of an element in memory: A system for determining a position of an element in memory comprising a memory queue with a plurality of separate entries and propagate and generate logic in communication with said memory queue such that said propagate and generate logic is operable to inspect each said separate entry in said memory... Agent: Hewlett Packard Company

20070028061 - Data processing device having a maintenance counter function: A data processing device with maintenance counters reliably stores the maintenance counter values. A data processing device such as a printer has RAM for storing the maintenance counter values, EEPROM segmented into a nonvolatile maintenance counter area and a temporary maintenance counter storage area, and a CPU for updating the... Agent: Edwards & Angell, LLP

20070028062 - Ripple queuing algorithm for a sas wide-port raid controller: In an operation sequence queue, a single headpointer is used with two tailpointers to identify operations to be passed to SAS engines in a wide-port environment. The order of execution of commands is preserved despite being performed in an SAS wide-port RAID controller having multiple SAS engines.... Agent: Oppedahl & Olson LLP

20070028063 - Device for restoring at least one of files, directories and application oriented files in a computer to a previous state: A device (1) for restoring items such as files, directories and application-oriented files in a computer to a previous state is disclosed. The device comprises a processor (3), a memory (5), input/output means (7). The memory (5) comprises a storage area (9), backup area (11), an attribute area (13), an... Agent: Dickstein Shapiro LLP

20070028066 - Method for controlling storage device controller, storage device controller, and program: Disclosed herein is a method for controlling a storage device controller connected to a storage device provided with a plurality of storage volumes for storing data respectively and an information processing apparatus for requesting an input/output of data so as to receive an input/output request from the information processing apparatus... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070028064 - Method for suspending mirrored writes during large data transfers: A method for mirroring file data includes receiving a data file and determining whether the data file exceeds a predetermined file size. The method further includes sending a mirror suspend notification to at least one mirrored drive and tracking at least one changed disk block, while maintaining read and write... Agent: Ibm Corp. (clg) C/o Cardinal Law Group

20070028065 - Method, system and program for forming a consistency group: Provided are a method, system, and program for forming a consistency group of data. Information is provided on a consistency group relationship indicating a plurality of slave controllers and, for each indicated slave controller, a slave storage unit managed by the slave controller. A command is transmitted to each slave... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20070028067 - Apparatus, system, and method for data protection by a storage device: An apparatus, system, and method are disclosed for utilizing data protection by a storage device to minimize loss of sensitive data on a storage medium. The apparatus includes a monitor module, a verification module, and a process module. The monitor module recognizes a write-type command from a host connected to... Agent: Kunzler & Associates

20070028069 - System and method for automatically relating components of a storage area network in a volume container: A volume container system automatically relates components of a storage area network in membership association of a volume container. The volume container is an abstract entity that maps a relationship between servers and storage devices. The entity captures network access control between servers and storage subsystems such as, for example,... Agent: Samuel A. Kassatly Law Office

20070028068 - System and method for managing resources in a distributed storage system: A resource management system uses a virtual resource pool distributed across a set of storage devices to manage resources in a distributed storage system. The storage devices dedicate a resource in an allocation pool available to the virtual resource pool. The virtual resource pool is a virtual storage server in... Agent: Samuel A. Kassatly Law Office

20070028070 - Method and system for time-weighted history block management: Disclosed is a technique for managing items in a memory store. A “free-space size threshold” is set for the memory store. An age parameter is also set. When the amount of free space in the store decreases below the threshold, space in the store is freed up by removing memory... Agent: Leydig Voit & Mayer, Ltd

20070028071 - Memory device: A memory device that can handle various transmission-source devices and transmission-destination devices without modifying the hardware configuration. The memory device is used to transmit and receive data, and includes a data buffer for storing data output from a data-transmission source and outputting the data to a data-transmission destination serving as... Agent: Arent Fox PLLC

20070028073 - Storage system, formatting method and computer program product: Provided is a storage system having a first storage controller and a second storage controller. An actual device of the second storage controller is mapped to a virtual device of the first storage controller. The first storage controller has a port for transmitting control cylinder information to be written in... Agent: Stanley P. Fisher Reed Smith LLP

20070028072 - System and method for alias mapping of address space: Mapping of address space by providing real storage including first and second address spaces. The second address space is smaller than and contained within the first address space. Provided within virtual storage is a system execution space. Providing within the system execution space is a system execution area having a... Agent: Shelley M. Beckstrand Patent Attorney

20070028074 - Maintaining shadow page tables in a sequestered memory region: Provided are a method, system, program and device for maintaining shadow page tables in a sequestered memory region. A first processor executing an application invokes a second processor to create a shadow page table used for address translation for the application in a sequestered memory region non-alterable by processes controlled... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20070028075 - System and method for testing for memory address aliasing errors: Aliasing errors, occasioned by including extra or missing bits, wrong addressing mode, or wrong address context, are detected by providing a storage configuration including gaps in valid addresses. An exception is thrown responsive to an address reference to a gap. Gaps are configured at complementary address ranges to facilitate detection... Agent: Shelley M. Beckstrand Patent Attorney