Electrical computers and digital processing systems: memory inventions 08/06

20060195649 - Heap memory management: A method, apparatus, and article of manufacture provide the ability to efficiently and effectively manage memory. A tri-linked list/tree of deallocated memory units available for use by a heap are used. A first link points to units smaller than a current block size, a second link points to units equal...

20060195648 - Managing checkpoint queues in a multiple node system: Techniques are provided for managing caches in a system with multiple caches that may contain different copies of the same data item. Specifically, techniques are provided for coordinating the write-to-disk operations performed on such data items to ensure that older versions of the data item are not written over newer...

20060195646 - System and method for classifying and storing well data: Embodiments of systems and methods for classification and storage of acquired well data according to the invention are disclosed. In one embodiment of the invention a system for handling information generally includes, but is not limited to, a sensor associated with a well and a memory coupled to receive data...

20060195647 - System and method for memory hub-based expansion bus: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a...

20060195651 - Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user...

20060195650 - Method to detect nand-flash parameters by hardware automatically: A method for automatically detecting a plurality of parameters for a NAND-Flash memory. A first step of the method may include generating a plurality of address cycles for the NAND-Flash memory. A second step may set an address number parameter of the parameters based on (i) a first number of...

20060195652 - Boot techniques involving tape media: In at least some embodiments, a system comprises a computer configured to boot using at least one of a plurality of boot techniques involving tape media. The system further comprises a tape drive coupled to the computer and a tape that is readable by the tape drive, wherein the tape...

20060195654 - Hard disk drive with write-only region: The invention partitions the HDD into three areas, namely, no access, write-only, and the conventional read/write. Sensitive data (antivirus programs, back up data, etc.) is written into write-only areas, which thereafter become designated “no access” by appropriately changing their designation a data structure known as “logical block address” or “LBA”....

20060195653 - Switchable mass storage system: Switching apparatus is used in combination with a multiplicity of mass storage units to provide a user of a digital computer with privacy from other local users and from users on a connected network. When the computer is connected to the network, the private files are protected from computer viruses,...

20060195655 - Command stack management in a disk drive: An intelligent disk drive is described which includes means for prioritizing execution of command by maintaining an associated priority with each command in a pending command list and executing the highest priority commands first. The command structure according to the invention includes a field in which the host specifies the...

20060195656 - Virtual ordered writes for multiple storage devices: Ordering data writes includes at least some of a group of primary storage devices receiving a first plurality of data writes, causing a cycle switch for the group of primary storage devices where the first plurality of data writes are associated with a particular cycle on each primary storage device...

20060195658 - Computer and disk management method for computer: According to one embodiment, a computer includes: a plurality of hard disk drives; a RAID driver that configures a RAID system using the hard disk drives; and a disk managing unit that manages the hard disk drives by partitioning a storage area of each of the hard disk drives into...

20060195657 - Expandable raid method and device: The present invention relates to RAID arrays with one or more dedicated parity disks. In particular, it relates to expandable RAID arrays. An expansion disk can be added to a RAID array without the need of redistributing striped data among disks....

20060195659 - Method for managing volume groups considering storage tiers: A tiered storage system according to the present invention provides for the management of migration groups. When a migration group is defined, a reference tier position is determined and the relative tier position of each constituent logical device is determined. Movement of a migration group involves migrating data in its...

20060195660 - System and method for performing entity tag and cache control of a dynamically generated object not identified as cacheable in a network: The present invention is directed towards a method and system for modifying by a cache responses from a server that do not identify a dynamically generated object as cacheable to identify the dynamically generated object to a client as cacheable in the response. In some embodiments, such as an embodiment...

20060195661 - Caching of dynamic arrays: Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment, the device includes a plurality of memory cells and at least one register for storing access information to access at...

20060195662 - Method for deterministic cache partitioning: A method is provided for partitioning a data cache for a plurality of applications. The method includes loading the data cache with a first data in a first frame, and loading the data cache with a second data within the first frame after loading the data cache with the first...

20060195663 - Virtualized i/o adapter for a multi-processor data processing system: An enhanced SCSI storage adapter with multiple queues for use by different server processors or partitions. For a non-partitioned server, the operating system (OS) owns the SCSI storage adapter, controls the adapter queues, both creation of and changes to the queues, and updates the queue table(s) in the storage adapter...

20060195665 - Access control device, method for changing memory addresses, and memory system: A memory control device detects memory accesses and communicates with a plurality of memory modules that are serially connected. The memory control device changes the allocation of addresses for the plurality of memory modules in accordance with the detection of memory accesses in the detection step....

20060195664 - Terminal for use in a system interfacing with storage media: A method is adopted in a control apparatus for controlling ID information stored in a storage medium in conjunction with a terminal for reading the ID information from the storage medium and used to catalog information for the storage medium into a memory employed in the control apparatus. In an...

20060195670 - Multi-site remote-copy system: Two storage areas are created in a first storage subsystem, a synchronous remote copy is performed from a first storage area included in the first storage subsystem to a storage area included in a second storage subsystem, and an asynchronous remote copy is performed from a second storage area included...

20060195667 - Remote copy for a storage controller with consistent write order: Two data centers located in the vicinity are connected using a synchronous transfer copy function, and one of the data centers is coupled with a third data center disposed at a remote location by an asynchronous remote copying function. The order whereat a storage sub-system located in the vicinity has...

20060195668 - Remote copy for a storage controller with reduced data size: Two data centers located in the vicinity are connected using a synchronous transfer copy function, and one of the data centers is coupled with a third data center disposed at a remote location by an asynchronous remote copying function. The order whereat a storage sub-system located in the vicinity has...

20060195669 - Storage system and storage control device: A first storage control device is provided with a virtual LU for showing a logical volume possessed by a second storage control device as if it were its own volume. When data processing requested from a host device is, for example, a specific processing of large load (such as direct...

20060195666 - Switching method of data replication mode: In remote data replication between storage systems, there are cases where the storage extent capacity used as the temporary storage extent in the storage system will incur waste. In a system having a management computer, a host computer, a first storage system, and a second storage system, when maintaining the...

20060195671 - Control system: A control system configured to control a predetermined unit by using a control program running on a general-purpose OS. The control system includes an auxiliary storage device configured to store the general-purpose OS, the control program, and various data items required for the control program to run, and a main...

20060195672 - Information recording medium and region management method thereof: A region management method for an information recording medium capable of maintaining data interchangeability among devices and preventing malfunction when one information recording medium shared among devices different in type or number of file systems that can be interpreted by devices is provided. A recording region of the information recording...

20060195673 - Method, apparatus, and computer program product for coordinating error reporting and reset utilizing an i/o adapter that supports virtualization: A method, apparatus, and computer program product are disclosed in a shared processor data processing system for coordinating error reporting for and resetting of a physical I/O adapter that supports virtualization. The physical I/O adapter is virtualized by generating virtual I/O adapters that each represent a portion of the physical...

20060195674 - System and method for managing metrics table per virtual port in a logically partitioned data processing system: A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to track performance and reliability statistics per virtual upstream and downstream port, thereby allowing a system and network management to be performed at finer granularity...

20060195675 - Association of host translations that are associated to an access control level on a pci bridge that supports virtualization: A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a...

20060195676 - Virtualization controller and data transfer control method: Embodiments of the present invention are directed to systems and methods of controlling data transfer between a host system and a plurality of storage devices. One embodiment is directed to a virtualization controller for controlling data transfer between a host system and a plurality of storage devices. The virtualization controller...

20060195677 - Bank conflict avoidance in a multi-banked cache system: A cache system comprises a plurality of cache banks, a translation look-aside buffer (TLB), and a scheduler. The TLB is used to translate a virtual address (VA) to a physical address (PA). The scheduler, before the VA has been completely translated to the PA, uses a subset of the VA's...

20060190669 - Wireless hard disk drive: A wireless hard disk drive is disclosed. The wireless hard disk drive includes a microprocessor, a Synchronous Dynamic Random Access Memory (SDRAM), a hard disk, a wireless chip, an antenna, and an Ethernet communication unit. The microprocessor has an SDRAM controller, a wireless chip controller and an Ethernet controller. The...

20060190671 - Memory device and method having multiple internal data buses and memory bank interleaving: A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of internal read data buses. A...

20060190670 - Semiconductor memory device, controller, and read/write control method thereof: A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address...

20060190672 - Semiconductor memory device and writing method thereof: To provide a semiconductor memory device comprising a phase-change memory and having high compatibility with DRAM interface. The memory cell array 18 comprises a memory cell that includes a phase-change element provided at the intersection of a bit line and word line. A write address and data accompanying a write...

20060190673 - Head suspension: The head suspension has a load beam to apply load to a head (21) that writes and reads data to and from a hard disk, a flexure (7) made of a conductive thin substrate attached to the load beam and supporting the head, an insulating base layer (35) made of...

20060190674 - Hub chip for connecting one or more memory chips: The invention relates to a hub chip for connecting one or more memory chips via a respective memory chip interface, having an address input for connecting the hub chip to an address bus and having an address output for connection to a further address bus, having an address decoder unit...

20060190675 - Control apparatus: A control apparatus includes an RAM capable of rewriting data; a data writing unit that writes a predetermined length of data output to the RAM in an arbitrary area of the RAM on the basis of an address signal for designating an address of the RAM and an effective area...

20060190677 - Sequential nibble burst ordering for data: A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode circuit is further responsive to a second portion of the address information for identifying an...

20060190676 - Static random access memory (sram) compatible, high availability memory array and method employing synchronous dynamic random access memory (dram) in conjunction with a data cache and separate read and write registers and tag blocks: A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to...

20060190678 - Static random access memory (sram) compatible, high availability memory array and method employing synchronous dynamic random access memory (dram) in conjunction with a single dram cache and tag: A static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag provides a memory architecture comprising low cost DRAM memory cells that is available for system accesses 100% of the time and...

20060190679 - Content addressable memory supporting multiple width searches: One embodiment disclosed relates to a content addressable memory (CAM) supporting multiple width entries. The CAM includes a plurality of rows for storing bits in an array, and at least one width bit reserved in every row to indicate a width of an entry. At least two comparand registers are...

20060190680 - Virtual storage system: The invention concerns a system for saving data derived from a mainframe characterized in that it comprises a computer equipment including an input/output interface for exchanging data with the guest computer, said interface comprising a backup document reader/inscriber emulator, at least one intermediate storage device and a tape document reader/inscriber,...

20060190681 - Scheduler for a disc drive apparatus: A scheduler (10) for a user appliance (1) and a user appliance comprising such scheduler are provided, for cooperation with a disc storage device (20). The scheduler is designed to record or read user data into or from storage space of the disc storage device, at storage locations where the...

20060190683 - Disk array apparatus and backup method of data: A disk array apparatus includes first and second RAID (Redundant Arrays of Inexpensive Disks) groups; and a disk array controller. The first RAID groups includes a first data disk group of a first disk group and a second disk group which store first and second data, respectively; and a first...

20060190682 - Storage system, method for processing, and program: In a storage system, a plurality of RAID devices are connected to a network, and data is multiplexed to primary data and secondary data by being mirrored among the RAID devices. When a failure of a disk device that can be recovered within the devices owing to the RAID configuration...

20060190684 - Reverse value attribute extraction: An attribute manager extracts attribute values from formatted data. The attribute manager maintains information concerning a plurality of attributes, such as matching names and values for attributes. Formatted data is parsed into a plurality of elements comprising a canonical representation of the data, independent of the data format. The formatted...

20060190685 - Method and apparatus for invalidating entries within a translation control entry (tce) cache: A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a...

20060190686 - Cache circuit: In the cache circuit, an instruction cache hit counter counts the number of cache hits, and an instruction memory access counter counts the number of times of instruction access. An instruction cache hit rate computation/entry disabling control circuit computes the ratio of the cache hit count to the instruction access...

20060190687 - Implementing memory evacuation using copy-on-write: A method for evacuating a source memory page. The method includes ascertaining a first set of processes, the first set of processes representing processes currently accessing the source memory page. The method also includes manipulating parameters associated with the source memory page to enable at least one copy-on-write procedure to...

20060190688 - Data processing system with prefetching means: The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is...

20060190689 - Method of addressing data in a shared memory by means of an offset: This invention relates to a first method of referencing a first number for data (29) to be stored and a second method of referencing a first address for data to be retrieved. Said data is shared among a producer and a consumer. Said first method comprising the steps of computing...

20060190690 - Content-on-demand memory key with positive access evidence feature: A method, system and apparatus for identifying unauthorized access to memory locations in a multi-element data storage device. The invention includes a restrictive key that is physically coupled to at least one inaccessible memory element in the data storage device. The key prevents the user from accessing the data in...

20060190691 - Die-to-die interconnect interface and protocol for stacked semiconductor dies: A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit (IC) package comprising a first semiconductor die that includes an interface to a memory-mapped device, a second semiconductor die that does not include an interface to a memory...

20060190692 - Method and apparatus for backup and recovery using storage based journaling: A storage system maintains a journal of journal entries and at lease one snapshot of one or more data volumes. By assigning a unique sequence number to journal and snapshot, it is easy to find a journal which can be applied to the snapshot. A technique is described for detecting...

20060190693 - Computer system, managing computer, host computer, and volume management method: A volume management system, a managing computer, a host, and a volume management method being capable of regulating the authorities of users and avoiding misoperations are provided. The volume management system comprises a storage having volumes served as a storage region, a managing computer, and a plurality of hosts used...

20060190694 - Disk array apparatus and control method for disk array apparatus: A disk array apparatus capable of effecting saving and operation of data through a simple construction. When a host computer sets “write inhibit” or “read/write inhibit” for an LDEV which is set on a first storage device, this setting is registered in an access attribute management table and is also...

20060190695 - Method and system for controlling access in memory devices, computer program product therefor: A system for providing controlled access to a memory area storing code and data, includes a processor cooperating with the memory area. The processor is configured for marking the instructions processed with a field describing the origin of the code being executed, and enabling data access in the memory area...

20060190696 - Security for logical unit in storage subsystem: Mapping tables are for stipulating information for primarily identifying computers, information for identifying a group of the computers and a logical unit number permitting access from the host computer inside storage subsystem, in accordance with arbitrary operation method by a user, and for giving them to host computer. The invention...

20060190697 - A lock-free memory allocator with delayed coalescing: A method is disclosed for dynamic memory allocation in computer programs. The invention uses free-lists stored in a table. A method of delayed coalescing is disclosed, whereby blocks are not coalesced immediately they are deallocated. Coalescing is performed by storing block-pointers in an array, sorting the array, and scanning the...

20060190698 - Network system and method for setting volume group in the network system: Disclosed is a method for setting virtual volume groups in a storage network system. The system includes a lower storage apparatus, host computers, an upper storage apparatus, and an administrative server. The method for setting virtual volume groups, executed by the administrative server, includes the steps of acquiring information on...

20060190699 - Method, medium, and apparatus transforming addresses of discs in a disc drive: A method, medium, and apparatus transforming a logical address of a disc. The method includes mapping a plurality of physical addresses to a plurality of logical addresses with reference to the data transmission speeds of the heads so that a physical address for a head having a higher data transmission...

20060184713 - Method for operating a virtual machine computer system running guest operating systems on a central processing means virtualized by a host system having register stack engine functionality: A method for operating a virtual machine computer system running computer guest operating system processes on a central processing means in a virtualized manner includes the steps of checking the virtual TLB entry for the backing store address of the register stack engine (RSE) by the VMM and in case...

20060184714 - Intelligent system health indicator: A method, apparatus, and computer instructions for handling updates. A database is queried to determine an effect of the update on the data processing system in response to detecting an update for the data processing system. A configuration of the data processing system is used in querying the database. A...

20060184715 - Method and system for exchanging description data between projects: Method and system for exchanging description data between projects The invention relates to a system and a method for exchanging application-oriented description data between projects, in particular between engineering projects in the field of automation. It makes it possible to exchange description data, in particular application-oriented engineering data, between sub-projects...

20060184721 - Configurable flash memory controller and method of use: A FLASH memory controller is disclosed. The controller comprises a microcontroller. The microcontroller including firmware for providing different mappings for different types of FLASH memory chips. The controller also includes FLASH control logic for communicating with the microcontroller and adapted to communicate via a FLASH data bus to at least...

20060184719 - Direct data file storage implementation techniques in flash memories: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where...

20060184722 - Direct data file storage implementation techniques in flash memories: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where...

20060184720 - Direct data file storage in flash memories: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where...

20060184718 - Direct file data programming and deletion in flash memories: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where...

20060184723 - Direct file data programming and deletion in flash memories: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where...

20060184717 - Integrated circuit capable of flash memory storage management: A method according to one embodiment may include creating a reserved portion on a storage device. The method of this embodiment may also include receiving at least one data write request to write data to a flash memory comprised in a host system. The method of this embodiment may also...

20060184724 - Nand flash memory system architecture: A data storage device includes a NAND flash memory, an executable interface and a controller for receiving, from a host, via the executable interface, an instruction to access the NAND flash memory at a virtual address and for translating the virtual address to a physical address of the volatile memory....

20060184716 - Non-volatile memory device and control method thereof: The present invention provides a non-volatile memory device and a control method thereof. The memory device comprises a memory controller and a multi-die memory. Since a first and a second non-volatile memory dies in the multi-die memory are enabled at different times by a first and a second chip enable...

20060184725 - Scratch control memory array in a flash memory device: A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array stores an instruction sequence for execution by the memory device's controller circuit. The sequence can include instructions for testing of the memory device. The...

20060184726 - Flexible access and control of dynamic random access memory: The invention relates in general to a method for accessing data stored in a dynamic random access memory. To enable flexible use of different types of memory modules, the invention provides addressing data through at least one address bus, controlling at least data flow to and from the dynamic random...

20060184727 - Information recording medium, information recording method, information recording apparatus, information reproduction method, and information reproduction apparatus: According to a recording method for a conventional rewritable disc, the latest data is recorded by rewriting data in an identical area. In the case of a disc of which the number of times of data rewrite is limited, this causes a problem that a defect block is easily generated....

20060184728 - Remote copy system: A remote copy system includes a first storage system including a first storage controller and a first data volume. The first storage controller is configured to control data access requests to the first data volume. The first storage system is configured to store write data in the first data volume...

20060184729 - Device, method, and computer product for disk management: A disk management device manages writing of data in a plurality of disks. The disk management device includes an application and a buffer. A plurality of storing units temporarily stores therein the same data that is present in the buffer, and a writing unit writes the data present in the...

20060184730 - Drive based sector initialization: A data storage system includes a host computer, a data storage device, and a communication bus connecting the host computer to the data storage device. The host computer is adapted to issue a specialized initiation command, such as a format command with a unique parameter or a unique send diagnostic...

20060184733 - Apparatus and method for reallocating logical to physical disk devices using a storage controller, with access frequency and sequential access ratio calculations and display: A storage controller calculates an access frequency of each logical disk; that is selects a first logical disk device of which the access frequency exceeds a first predetermined value, the first logical disk device being allocated to a first physical disk device; selects a second logical disk device which has...

20060184731 - Data placement technique for striping data containers across volumes of a storage system cluster: A technique places content, such as data, of one or more data containers on volumes of a striped volume set (SVS). The placement of data across the volumes of the SVS allows specification of a deterministic pattern of fixed length. That is, the pattern determines a placement of data of...

20060184732 - Disk device control program, disk device control method and disk device control system: A disk device control program, a disk device control method, and a disk device control system which can build a disk device having a plurality of disk units and facilitate the preventive replacement of the disk device are provided. A disk device control program for allowing a computer to execute...

20060184736 - Apparatus, system, and method for storing modified data: An apparatus, system and method are disclosed for storing modified data. The apparatus includes a battery source for supplying backup power. The apparatus also includes a memory module for storing data. The memory module includes a backup portion and a non-backup portion. Only the backup portion is backed up by...

20060184737 - Data stream generation method for enabling high-speed memory access: An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit determination sections determine that the data stored in the allocated addresses does not exist in...

20060184734 - Method and apparatus for efficiently accessing both aligned and unaligned data from a memory: A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one...

20060184735 - Methodology for effectively utilizing processor cache in an electronic system: A system and method for efficiently performing processing operations includes a processor configured to control processing operations in an electronic apparatus, and a memory coupled to the electronic apparatus for storing electronic information. A cache is provided for locally storing cache data copied by the processor from target data in...

20060184738 - Unaligned memory access prediction: In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The additional micro-operation accesses the memory falling across a predetermined address boundary. Predicting the...

20060184739 - Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch: A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit...

20060184740 - Storage system: An object of the present invention is to provide a storage system which is shared by a plurality of application programs, wherein optimum performance tuning for a cache memory can be performed for each of the individual application programs. The storage system of the present invention comprises a storage device...

20060184741 - Method, apparatus, and computer program product for sharing data in a cache among threads in an smt processor: A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The SMT processor executes multiple threads concurrently during each clock cycle. The cache is dynamically allocated for use among the multiple...

20060184743 - Cache memory direct intervention: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache...

20060184742 - Victim cache using direct intervention: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache...

20060184744 - Method and apparatus for implementing a combined data/coherency cache: A method and apparatus for implementing a combined data/coherency cache for a shared memory multi-processor. The combined data/coherency cache includes a system cache with a number of entries. The method includes building a system cache directory with a number of entries equal to the number of entries of the system...

20060184745 - Organization of dirty bits for a write-back cache: A cache system is constructed in accordance with an architecture that comprises a tag array into which tags are stored that are used to determine whether a hit or a miss into the cache system has occurred. Further, the cache system comprises a data array into which cache lines of...

20060184747 - Bandwidth of a cache directory by slicing the cache directory into two smaller cache directories and replicating snooping logic for each sliced cache directory: A cache, system and method for improving the snoop bandwidth of a cache directory. A cache directory may be sliced into two smaller cache directories each with its own snooping logic. By having two cache directories that can be accessed simultaneously, the bandwidth can be essentially doubled. Furthermore, a “frequency...

20060184746 - Reducing number of rejected snoop requests by extending time to respond to snoop request: A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the...

20060184748 - Reducing number of rejected snoop requests by extending time to respond to snoop request: A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop...

20060184749 - Reducing number of rejected snoop requests by extending time to respond to snoop request: A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon...

20060184750 - Coherency management for a \"switchless\" distributed shared memory computer system: A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A...

20060184751 - Implementation of integrated status of a protection register word in a protection register array: A protection register array in which the lock status of the protection register is stored outside of the array. An initial verify function is used to read lock status....

20060184753 - Full access to memory interfaces via remote request: A system and method for enabling a processor to access a memory not directly coupled to the processor. A memory request, including a request identifier field, is issued by a processor to a local memory management unit (MMU). Using the request identifier field, the local MMU determines whether the memory...

20060184752 - Memory controller and memory control system predicting non-contiguous access: A memory controller for controlling operation of a memory accessed by a processor, includes an access information storage circuit storing history information of non-contiguous access of non-contiguous addresses of data accessed by the processor, a prediction circuit predicting a non-contiguous access based on the history information of non-contiguous access, an...

20060184757 - Data memory controller that supports data bus invert: The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces...

20060184754 - Method and apparatus to avoid collisions between row activate and column read or column write commands: A method and apparatus to avoid collisions between row activate and column read or column write commands is presented. A memory controller includes control logic, activate allowed logic, and last column counter logic. The control logic sends particular values to the activate allowed logic and the last column counter logic...

20060184755 - Semiconductor memory device and memory system using same: There is provided a semiconductor memory device and a memory system using the same. The semiconductor memory device includes an input data delay time adjustor for varying an input delay time, selecting one bit of a n-bit input data, delaying the selected one bit by the input delay time and...

20060184756 - Semiconductor memory module for improvement of signal integrity: A semiconductor memory module has a module board on both sides of which semiconductor memory components are arranged and on an upper face of which a control component is arranged. The control component is connected to the semiconductor memory components via a module bus and bus spurs. The bus is...

20060184758 - Storage device: A storage device includes a plurality of memories storing data; and a controller controlling the memories, the controller performing in parallel in a number of the memories, the number being specified by a supplied specifying signal, one of a data writing process for writing data supplied from a connection destination...

20060184761 - Identification information diagnosis method and input and output apparatus: An identification information diagnosis method is used in an input and output apparatus in which first identification information unique to each storage unit is written in each storage unit that is inserted into a corresponding slot of each device enclosure, and a physical address of each storage unit is obtained...

20060184762 - Memory management for a mobile multimedia processor: Certain embodiments of the invention may be found in a method for memory management for a mobile multimedia processor. The method may comprise receiving within a mobile multimedia processor chip a plurality of memory requests. The plurality of memory requests may be handled by allocating memory from at least one...

20060184759 - Permanent pool memory management method and system: A method, system, and computer program manager for a computing system memory in the operation of a computing process. At least one memory segment provides memory resources for the computing process. The memory segment includes a plurality of memory objects, each of the memory objects includes an equal number of...

20060184760 - Storage controlling unit: Provided is a storage controller capable of changing a system configuration with scalability. A storage controller blade of the storage controller includes: interface units that each connect to one of a host computer and a disk device; a processor unit that controls a configuration of the storage controller and data...

20060184763 - System and method for updating firmware in a non-volatile memory without using a processor: A processing system connected to an apparatus includes a non-volatile memory (NVM) for storing firmware needed by the processing system; and an NVM control interface capable of writing and reading data stored in the NVM; wherein the NVM control interface reads a previous piece of data being already written into...

20060184764 - Method of assuring data integrity on storage volumes: A method for assuring the integrity of stored data in a storage system is provided. At a specified time at which further writes to a desired portion of the stored data are to be precluded, a hash value is calculated for the desired portion of stored data. At a later...

20060174053 - Method and apparatus for supporting address translation in a virtual machine environment: In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM. The determination is made based on metadata extracted from a...

20060174054 - File management apparatus and its control method: A new filename after change is generated based on rules set using a filename setting menu (301), extension format selection menu (302), basic setting menu (303), and format setting menu (304), and is displayed on a new filename list display window (306). In this case, if the new filename is...

20060174055 - System and method for reducing memory requirements of firmware: A mechanism for making increased amounts of firmware available to a computer pre-boot is discussed. To increase the amount of firmware available pre-boot, a design decision is made during the build process as to which segments of the firmware need to be placed on the ROM part and which segments...

20060174057 - Apparatus and related method for accessing page mode flash memory: A method of controlling an access time for accessing a flash memory comprises comparing a target address of the flash memory with an address of the flash memory that was previously accessed; setting the access time for the flash memory to be a first access time if the target address...

20060174056 - Universal memory device having a profil storage unit: A universal memory device is presented that provides adaptability to existing hardware and software environments. The memory can “mimic” existing memory technology combining the advantages of integration all memory capacity in to one single technology and still providing the implicit protections and access characteristics known from the different existing memory...

20060174058 - Recirculation buffer for semantic processor: A system and method comprising a buffer configured to receive a data stream, a parser configured to parse the data stream from the buffer, and one or more processing units configured to co-process the data stream from the buffer responsive to the parsing by the parser, and then provide at...

20060174059 - Speculative data loading using circular addressing or simulated circular addressing: This invention prevents illegal memory address faults on speculative data loads. Circular addressing of the address pointer limits memory access to a range of addresses including all addresses used by the address pointer and not including any invalid addresses. The invention uses circular addressing hardware, if available on the data...

20060174061 - Disk array system and cache control method: Disclosed is a disk array system that can be expanded effectively in scale by increasing the number of input/output channels and disk adapters and improved in such performance as the number of input/output operations per second, data transfer rate. The disk array system is provided with input/output channels to be...

20060174060 - Information processing apparatus and method for controlling disk device: An information processing apparatus includes: a main body; a first disk device that is built into the main body; an attachment portion to which a device is detachably attached, the attachment portion being disposed in the main body; a disk controller that controls the first disk device and a second...

20060174064 - Method and arrangement for manipulation of the content of a data memory: In a method and arrangement for manipulation of the contents of a data memory with which a processing device can be connected to manipulate (in at least one manipulation step at least one first memory range of the data memory, the processing device monitors a monitoring range of the first...

20060174062 - Method and system for cache utilization by limiting number of pending cache line requests: System and method for memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a new cache line-sized memory request, determining whether a number of pending requests is less than a fetch limit that is equal to or less than a number...

20060174063 - Method of cooperative caching for distributed storage system: An embodiment of a method of cooperative caching for a distributed storage system begins with a step of requesting data from storage devices which hold the data. The method continues with a step of receiving any cached blocks and expected response times for providing non-cached blocks from the storage devices....

20060174065 - System and method for annotating an ultrasound image: A system and method are provided for annotating data displayed on a display device. The system includes a processing unit for processing data and providing the processed data to the display device for displaying a portion thereof, and further generating a cursor for display by the display device and accessing...

20060174066 - Fractional-word writable architected register for direct accumulation of misaligned data: One or more architected registers in a processor are fractional-word writable, and data from plural misaligned memory access operations are assembled directly in an architected register, without first assembling the data in a fractional-word writable, non-architected register and then transferring it to the architected register. In embodiments where a general-purpose...

20060174067 - Method of caching data: An embodiment of a method of caching data writes data units into a write cache for eventual flushing to storage. The method sets a copy-to-read-cache flag for each particular data unit that is read from the write cache. Upon flushing each data unit to the storage, the method copies the...

20060174068 - Method and bus prefetching mechanism for implementing enhanced buffer control: A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. The master generates a continue bus signal...

20060174069 - System and method for snooping cache information using a directory crossbar: A system and method for maintaining coherency in a symmetric multiprocessing (SMP) system are disclosed. Briefly described, in architecture, one exemplary embodiment comprises a first crossbar coupled to a plurality of local processors; a second crossbar coupled to at least one remote processor; and at least one crossbar directory that...

20060174070 - Memory hub bypass circuit and method: A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurality of memory devices....

20060174072 - Electronic control unit analysis: A system for acquiring information on the operation of an electronic control unit (ECU) includes a controller and a non-volatile memory. The controller is coupled to address and data buses of a central processing unit (CPU), which is located within an electronic control unit (ECU). The controller includes a register...

20060174071 - System and method for handling status commands directed to partitioned media library: Embodiments of the present invention provide a method and system for handling status commands directed to a partitioned media library. A controller (e.g., storage router or other device) that controls access to the physical media library can receive a status command and determine whether it should respond to the status...

20060174073 - Priority initialization system: A computer storage system includes a supervisor algorithm to detect a host computer's initiator logging in. The supervisor algorithm identifies data storage devices associated with the newly logged-on initiator and tags logical unit number control blocks (“LUNCBs”) as having priority in an initiation process. The supervisor algorithm assigns a task...

20060174076 - Data processing system including storage systems: A data processing system includes a first storage system including a first host and a first storage subsystem. The first host has access to a first copy manager that is operable to manage a data replication operation. A second storage system includes a second host and a second storage subsystem....

20060174075 - Method for creating and preserving snapshots in a storage system: The reduction of the volume capacity necessary to copy the snapshot can be achieved. When an operation volume is updated, the data before the update is saved in a difference storing volume, and the data of the two volumes, that is, the operation volume and the difference storing volume are...

20060174074 - Point-in-time copy operation: A method and service creates and maintains a virtual point-in-time copy of source data stored within a source storage unit. The method/service receives at least one request to create a point-in-time copy of the source data. However, instead of creating a copy of the source data, the invention creates a...

20060174079 - Computer system: A technology for allowing the smooth acquisition of required data when a processor switches working modes in a computer system is provided. According to one aspect of the present invention, the present invention can provide a computer system including a processor having a plurality of working modes, each having a...

20060174077 - Software memory access control: Software memory access control is provided by associating instruction areas with memory areas such that instruction areas are not permitted to access memory areas with which they are not associated. Checks may be inserted in the instruction areas to ensure that data provided by a memory group is provided by...

20060174078 - System and method for executing a process on a microprocessor-enabled device: The invention provides a system and a method for controlling a request for a resource from a process operating on a microprocessor-enabled machine is provided. The method comprises regulating access of the process to the resource associated with the machine via a parent process when the process initiates the request...

20060174080 - Apparatus and method to selectively provide information to one or more computing devices: A method is disclosed to selectively provide information to one or more remote computing devices. The method provides an information storage and retrieval system comprising first information, a first logical partition, and a second logical partition, where the first information is disposed in the first logical partition. The method further...

20060174081 - Memory interface and method of interfacing between functional entities: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of...

20060174082 - Method and apparatus for managing write-to-read turnarounds in an early read after write memory system: A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation...

20060174083 - Method of load/store dependencies detection with dynamically changing address length: A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline and the queues to avoid address conflicts. Overall, the present...

20060174085 - Storage enclosure and method for the automated configuration of a storage enclosure: An architecture and a method for the automated configuration of a storage enclosure are disclosed. The disclosed storage enclosure includes an internal communications link between the storage controllers of the storage enclosure. The storage enclosure is operable to determine if the storage enclosure is a terminal storage enclosure or if...

20060174084 - Storage system configuration validation: A method, of validating the configuration of a storage system (SS) via comparison of a snapshot thereof (SSshot) against a desired storage system architecture (SS-architecture) where the storage system includes an interconnected plurality of devices, may include: providing a database representing the desired SS-architecture, the database including a first listing...

20060174086 - Storage-system-portion sufficiency determination: A method, for determining sufficiency of a given set of portions included within a storage system (SS) to accommodate one or more flows of data anticipated as flowing therethrough, may include: configuring the given set to include at least one of following portions, a given stable of one or more...

20060174087 - Computer system, computer, storage system, and control terminal: To manage physical paths between a server system and a storage system and information about routing between virtual machines and virtual storage systems in an integrated fashion. A computer system of the present invention includes: a computer and a storage system that stores data, in which the computer includes first...

20060174088 - Method and system for presenting contiguous element addresses for a partitioned media library: According to one embodiment of the present invention, a controller that partitions a media library for multiple host applications can, for each partition, assign a base element address for an element type and associate physical element addresses for elements of an element type with an index value. For a partition,...