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Electrical computers and digital data processing systems: input/output January USPTO class patent listing 01/07Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/25/2007 > 20 patent applications in 13 patent subcategories. USPTO class patent listing
20070022220 - Bus system having a transmission control module and a transmission interface: A bus system having a transmission interface and a transmission control module built in a processor is provided. The transmission interface receives instruction signals output from the transmission control module and executes a corresponding data transmission process such that fast data transmission between storage unit of the processor and a... Agent: Edwards & Angell, LLP
20070022221 - Programmable control device: A programmable control device includes an input unit, a memory unit, an execution unit, a monitor unit and an output unit. The input unit has at least one input terminal for receiving an input signal. The memory unit defines plural feature tables for corresponding functional units, the feature table defining... Agent: Bacon & Thomas, PLLC
20070022222 - Memory device and associated method: A memory device and an associated operating method are provided to implement a customized function of the memory device by using a specially designed command packet. In one embodiment, a manufacture reserved command defined by a standard protocol is used and a corresponding customized command argument is configured, so as... Agent: Raymond Sun
20070022223 - Electronic apparatus and method for implementing an intelligent sleep mode: A method for implementing an intelligent sleep mode on an electronic apparatus includes the steps of: tracking an elapsed time where no operational input is received; decreasing output volume when the tracked time is equal to a predetermined time period if the output volume is greater than a predetermined volume;... Agent: North America Intellectual Property Corporation
20070022226 - Direct memory access system for iscsi: The invention relates to a direct memory access system for iSCSI. The direct memory access system comprises: a first bus interface, a second bus interface, a FIFO memory, an iSCSI CRC module and a direct memory access controller. According to the invention, the iSCSI CRC module is mounted in the... Agent: Volentine Francos, & Whitt PLLC
20070022224 - Memory data transfer method and system: A method and apparatus are disclosed for providing a DMA process. Accordingly, a DMA process is initiated for moving data from contiguous first locations to contiguous second locations and to a third location or third locations. Within the DMA process the data from each of the contiguous first locations is... Agent: Freedman & Associates
20070022225 - Memory dma interface with checksum: A system and method comprising a direct memory access (DMA) circuit configured to directly access a memory, and a checksum adder configured to determine a checksum for data transferred between the DMA circuit and the memory.... Agent: Marger Johnson & Mccollom, P.C.
20070022227 - Path control device, system, cluster, cluster system, method and computer readable medium embodying program: A path control device that controls first and second paths for accessing a peripheral subsystem, includes a command substituting unit that substitutes a first reserve command that allows an access through the first path, with a second reserve command that allows both of accesses through both of the first path... Agent: Mcginn Intellectual Property Law Group, PLLC
20070022229 - Computer system and computer system control method: In the system which connects an operation apparatus and a standby apparatus through a bus, the operation apparatus includes a controller which controls the operation of the operation apparatus, operation manager, and the switch. The operation manager monitors the operation of the controller and notifies the standby apparatus through the... Agent: Mcginn Intellectual Property Law Group, PLLC
20070022228 - Method to create expandable storage using serial ata hdd: An external SATA hard disk drive is modified to contain a port multiplier having at least one additional external device physical layer which permits multiple external hard disk drives to be connected to a single external SATA port on a set top box, television receiver or personal computer.... Agent: Texas Instruments Incorporated
20070022231 - Method and system for transferring a stream of data: The present invention relates to a method and system for transferring a stream of data from a first higher-speed subsystem of a computer to a plurality of lower speed subsystems, wherein the stream is structured in a sequence of blocks of different bit length, and a block is to be... Agent: International Business Machines Corporation
20070022230 - Spread spectrum receiver, apparatus and method of a circular buffer for multirate data: An apparatus, spread spectrum receiver, and method of controlling a circular buffer, comprising a circular buffer and a controller coupled thereto. The circular buffer receives first data at a first data rate and second data at a second data rate. The controller determines a first range in the circular buffer... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20070022232 - Cellular telephone with integrated usb port engagement device that provides access to multimedia card as a solid-state device: A cellular telephone includes a multimedia card (MMC) having storage capacity for computer data files. An engagement device for a data transfer interface (e.g., a universal serial bus (USB) interface) is permanently mounted to the housing of the cellular telephone. The engagement device is movable from a nonobstructing home position... Agent: Jerry Turner Sewell
20070022234 - Devices and methods for signal switching and processing: A device for signal switching and processing. A plurality of control signal output terminals are connected to a plurality of computers. A control signal input terminal receives control signals from an input device. A signal processor determines a control signal output terminal to output the control signals, thus, the User... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20070022233 - Document processing device with usb drive: A printing device operable to perform a plurality of document processing functions. The printing device includes a housing, a USB port positioned on the housing, a user interface and a controller. The USB port is configured to receive a portable data storage device having memory for storing data. The user... Agent: Lexmark International, Inc. Intellectual Property Law Department
20070022235 - Non-volatile storage device with thin display unit: A non-volatile storage device with a thin display unit is described. The non-volatile storage device has a thin display unit, a non-volatile storage unit, a connection interface, and a package unit. Therein, the non-volatile storage unit further has a controller and a non-volatile storage medium. The thin display unit further... Agent: Rosenberg, Klein & Lee
20070022236 - Computer keyboard integrated with internet phone service: A computer keyboard integrated with Internet phone service includes a keyboard controller, a USB hub and an audio controller. The keyboard controller receives an input command from the keyboard. The USB hub relays the signal of the keyboard controller to the computer, and relays the digital signal of the computer... Agent: Hdsl
20070022237 - Hybrid data distribution systems: A hybrid data distribution system includes a modulator coupled to an analog device, one or more processors coupled to the modulator, and a database coupled to the one or more processors. The database is configured to store encoded data. The system also includes an Ethernet switch for transmitting the encoded... Agent: Baker & Botts L.L.P.
20070022238 - Pci arbiter: A bus arbiter that ensures high priority transfers complete and allows high-priority data transfers with specific latency requirements, such as 802.11 requirements, to be prioritized above data transfers with lower latency requirements. As an example, the arbiter closely manages all transactions and guarantees sufficient latencies by pre-empting lower-priority data transfers... Agent: Tucker, Ellis & West LLP
20070022239 - Apparatus and method for ordering transaction beats in a data transfer: A microprocessor including a cache memory and bus interface logic. The bus interface logic is interfaced with request signals and data signals and includes a request interface and a response interface. The request interface provides a request via the request signals for a data transaction in which the request specifies... Agent: Huffman Law Group, P.C.01/18/2007 > 18 patent applications in 15 patent subcategories. USPTO class patent listing
20070016698 - Memory channel response scheduling: A memory agent schedules local and pass-through responses according to an identifier for each response. A response file may be large enough to store responses for a maximum number of requests that may be outstanding on a memory channel. A request file may be large enough to store requests for... Agent: Marger Johnson & Mccollom, P.C.
20070016699 - Memory control apparatus and method: A flower arrangement that appears to be a cake. A piece of foam, shaped in the shape of a cake, having flowers inserted into the foam, and then placed on a cake plate or platter, and then placed in a cake box.... Agent: Fitzpatrick Cella Harper & Scinto
20070016700 - Integrated circuit device and electronic instrument: An integrated circuit device has a data memory including a memory cell array which includes a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells, and a memory output circuit. The data read order in the memory cell array corresponding to the arrangement of the bitlines... Agent: Oliff & Berridge, PLC
20070016702 - Data flow control and bridging architecture enhancing performance of removable data storage systems: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit.... Agent: Law Office Of Mark J. Spolyar
20070016701 - Method and apparatus for providing redundant i/o adapters in machine and process controllers: Methods and apparatus for redundancy in machine or process control systems provide redundant communication adapters located with the groups of I/O modules, so that if the first communication adapter faults or becomes unavailable, a second communication adapter will perform all of the necessary functions of the first adapter. The adapters... Agent: Rockwell Automation, Inc./(qb)
20070016703 - Method for generatimg and playing back a media file: The invention relates to a method for playing back a media file in a playback unit, comprising the retrieval of the executable instructions contained in the media file by the playback unit, the execution of the instructions for decoding and/or decompressing a media data flow that is stored in the... Agent: Siemens Corporation Intellectual Property Department
20070016704 - Removable mother/daughter peripheral card: A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash... Agent: Parsons Hsue & De Runtz LLP
20070016705 - Method and apparatus for protocol and code converter: Apparatus and method for converting protocol and code for use with a Human Interface Device (HID)-compliant keyboard device comprises a Universal Serial Bus (USB) interface, non-USB interface and a converter. The USB interface receives standard USB data from an USB host or hub and provides responses required by an USB... Agent: Fulbright & Jaworski, LLP
20070016706 - Reduced bus turnaround time in a multiprocessor architecture: Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus handoff. The method may also include bypassing data from recovery latches and instead receiving data from pipeline latches... Agent: Hewlett Packard Company
20070016707 - Configuration connector for information handling system circuit boards: The present invention provides a configuration jumper that allows the main system board of an information handling system to be configured for a plurality of population options, including on-board PCI-E integrated circuits and PCI-E integrated circuits on expansion circuit boards that are connected to the main system board by an... Agent: Hamilton & Terrile, LLP
20070016708 - Communication system with switchable connection: A communication system is provided, including a first master device to operate as a master of a communication according to a first protocol, a second master device to operate as a master of a communication according to a second protocol, a common slave device to operate as a slave of... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.
20070016709 - Bus control system and a method thereof: A bus control system includes a plurality of bus masters commonly connected to a bus, a bus arbiter for arbitrating use of the bus between the plurality of bus masters according to any one of a plurality of predetermined arbitration algorithms, and an arbitration algorithm control unit for switching the... Agent: Young & Thompson
20070016710 - Interrupt controller and method for handling interrupts: An interrupt controller and method are provided for handling interrupt requests generated by a plurality of interrupt sources. Th interrupt controller comprises pend logic for receiving interrupt requests generated by the plurality of interrupt sources, and for each interrupt request determining whether to accept that interrupt request for handling by... Agent: Nixon & Vanderhye, PC
20070016711 - Interfacing structure for multiple graphic: An interfacing structure for a computer motherboard is provided herein, which is specifically designed to simply the installation of multiple graphic adaptors compliant with Scalable Link Interface (SLI) standards. The interfacing structure contains at least three PCI Express x16 slots, two of which are for the installation of the SLI-compliant... Agent: Leong C Lei
20070016713 - Method and system for multi-channel transfer of data and control: A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips are connected to a bridge bus. A bridge is connected to the bridge bus and to a system bus. In addition, a memory is connected to the bridge.... Agent: Brake Hughes PLC C/o Portfolioip
20070016712 - Multi-port bridge device: A bridge device electrically connected to a first AGP bus, a second AGP bus, and a PCI bus is provided. The bridge device has a first bridge, a second bridge, and a controller. The first bridge is electrically connected between the first AGP bus and the second AGP bus. The... Agent: Birch Stewart Kolasch & Birch
20070016714 - Multi-use usb host to ethernet adapter: A multi-use adapter configured to provide network connectivity for a serial bus client is provided. The adapter includes: a serial interface for coupling with the serial bus client; a network interface for interfacing the adapter with a network; and host control logic configured to interface a plurality of types of... Agent: Macpherson Kwok Chen & Heid LLP
20070016715 - Modular broadband bi-directional programmable switch with hot-swappable modules: A programmable switch for broadband signals having a modular design in which input cards, bridging cards and output cards are interconnected through a common backplane to form a switching matrix having a Clos architecture. All connections between cards are made through the backplane to decrease the complexity of the switch... Agent: Dennis M. Carleton, Esquire Buchanan Ingersoll PC01/11/2007 > 18 patent applications in 15 patent subcategories. USPTO class patent listing
20070011360 - Hardware oriented target-side native command queuing tag management: Methods and apparatus for target-side SATA NCQ tag management are disclosed. In one aspect, an apparatus may include a status memory and a status manager circuit in communication with the status memory. The status memory may store status information for each of a plurality of commands that have been queued... Agent: Blakely Sokoloff Taylor & Zafman
20070011361 - Storage management system: Conventionally, it has been impossible to choose storage subsystems for selective implementation of I/O delay to prevent buffer from overflowing during remote copy. According to this invention, in a management computer that manages serially connected plural storage subsystems in a computer system, the computer system having a host computer to... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20070011362 - Information processing device, line concentrator, network infromation processing system having the line concentrator, information processing program and storage medium: There is provided a mediation section (34) for switching between an active status in which data transmitted to a specific address is registered and processed and a non-active status other than the active status. When the mediation section (34) judges that unprocessed data stored in a data storage section (31)... Agent: Birch Stewart Kolasch & Birch
20070011364 - Direct memory access controller supporting non-contiguous addressing and data reformatting: A direct memory access controller is provided that is operable to perform a data transfer to transfer target data from a source to a destination. The direct memory access controller comprises an address generator having a set of iterators comprising a sample iterator, at least one frame iterator and at... Agent: Nixon & Vanderhye, PC
20070011363 - Dual frequency first-in-first-out structure: Techniques and circuitry for transferring data from memory arrays of a memory device to output pins via a FIFO structure are provided. Input and output stages of the FIFO structure may be operated independently, allowing data to be loaded into the FIFO structure at a first frequency and unloaded from... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies
20070011365 - Electric field device: The invention relates to an electric field device (1) comprising a computer-controlled least one input/output module (3a-3f) data inputs and/or data outputs. The central control module (2) and the at least one input/output module (3a-3f) are connected to one another via a data bus (4). In order to design a... Agent: Lerner Greenberg Stemer LLP
20070011366 - Bus system and data transfer method: A bus system which transfers data from a first device to a second device includes a holding unit which holds data input from the first device, and a selecting unit which selects whether to output the data from the first device to the second device by holding the data by... Agent: Fitzpatrick Cella Harper & Scinto
20070011367 - System and method for automatically responding to a received communication: A device and a method of responding to a received interrupt event received by a communication device is provided. The method comprises accessing data associated with a calendar application and/or a location application to determine a current state of availability of a user of the device using data; determining whether... Agent: Mccarthy Tetrault LLP
20070011368 - Digital phase relationship lock loop: In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20070011369 - Low overhead serial interface: An interface for an integrated circuit chip is provided. The interface includes a first port configured to receive a command signal indicating whether command information or data is being transferred to the integrated circuit chip. The interface further includes a second port configured to receive the command information and the... Agent: Epson Research And Development Inc Intellectual Property Dept
20070011370 - Multiple data rates in programmable logic device serial interface: A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably... Agent: Fish & NeaveIPGroup
20070011372 - Signal adapter: A signal adapter for signally connecting a USB storage card and a USB port of an electronic apparatus is disclosed. The signal adapter comprises a casing, a slot for inserting the USB storage card therein, a bridge disposed in the casing and electrically coupled to the USB storage card for... Agent: Bacon & Thomas, PLLC
20070011371 - Storage control system: The network channel adapter (CHN) 8 that processes file access requests is divided into a CHN-NAS portion 3 that performs processing to convert a file access request to a block access request and a CHN-IO portion 5 that outputs the block access request. Part 3 where the CHN-NAS portion 3... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20070011373 - System and method for identifying inoperable connection points in a storage enclosure: A system and method is disclosed for encoding a set of configuration data for a given expander and at some later point comparing the configuration data to a discovered configuration derived from an attempt to discover the operability of each phy or connection point of the storage system. The configuration... Agent: Roger Fulghum Baker Botts L.L.P.
20070011374 - Method and system for universal serial bus (usb) re-direct (usb-r) over a network: Certain aspects of a method and system for universal serial bus (USB) re-direct (USB-R) over a network may comprise receiving at a local client device via a network, remote client device detection data corresponding to a remote client device that is plugged into a remote system. The local client device... Agent: Mcandrews Held & Malloy, Ltd
20070011375 - Method and system for hardware based implementation of usb 1.1 over a high speed link: Certain aspects of a method and system for a hardware-based implementation of USB 1.1 over a high-speed link may comprise translating at a client side of a client server communication system, USB protocol messages comprising a first USB standard to corresponding encapsulated USB protocol messages, wherein the USB protocol messages... Agent: Mcandrews Held & Malloy, Ltd
20070011378 - Apparatus and method for quad-pumped address bus: A microprocessor interface system including a system bus with a bus clock and a quad-pumped address signal group, and including multiple devices coupled to the system bus. Each device is configured to perform a quad-pumped transaction on the system bus in which multiple request packets are sequentially transferred via the... Agent: Huffman Law Group, P.C.
20070011377 - Microprocessor apparatus and method for enabling variable width data transfers: A microprocessor including processor logic and sparse write logic which asserts address signals and request signals to provide an address and a request for a cache line memory write transaction, which provides one of multiple sparse memory write transactions on the request signals and which provides corresponding enable bits on... Agent: Huffman Law Group, P.C.
20070011376 - Target readiness protocol for contiguous write: A method of performing contiguous write transactions on a processor bus according to an embodiment of the present invention includes detecting, by a bus agent, a request for a write cycle, asserting, by the bus agent, a target ready signal for one clock cycle in response to the write cycle... Agent: Huffman Law Group, P.C.
20070011379 - I/o energy reduction using previous bus state and i/o inversion bit for bus inversion: A bus inversion method and system for capturing a previous state of a bus and its corresponding inversion bit prior to transmitting new information over the bus. The new information, state of the bus and associated inversion bit are used to determine whether the new information should be inverted before... Agent: Dickstein Shapiro LLP
20070011380 - Bus system, bus manager device, node device, and program for bus manager device: In a bus system, in accordance with reservations of transfers of isochronous blocks of data and with requests by the node devices for transfers of ones of the isochronous blocks of data and regular blocks of data, a bus manager generates a schedule of the operating rate of a bus... Agent: Arent Fox PLLC
20070011381 - Control method and control circuit for bus system: A control method of the present invention comprises: a step for predetermining a priority level for accessing a slave via a bus with respect to a plurality of bus masters, as a basic priority; a step for determining a reference access frequency with respect to the plurality of bus masters,... Agent: Nixon Peabody, LLP
20070011382 - Hierarchical memory access via pipelining with deferred arbitration: A circuit arrangement and method utilize a hierarchical pipelined memory-access structure incorporating deferred arbitration logic. A multi-stage pipelined network defines at least one pipeline between a plurality of initiators and a shared resource. The multi-stage pipelined network includes first and second stages, where the first stage is disposed intermediate the... Agent: Philips Electronics North America Corporation Intellectual Property & Standards
20070011384 - Computer expansion slot and design method thereof: A slot is configured as one of a first slot or a second slot. The slot includes a primary slot. The primary slot includes a series of pads. At least one pad has two branches. When the pad which has two branches is connected to one branch the slot performs... Agent: Morris Manning Martin LLP
20070011383 - System and method for configuring expansion bus links to generate a double-bandwidth link slot: A system and method for configuring expansion bus links to generate a double-bandwidth link slot are disclosed. An information handling system includes a central processing unit (CPU) and memory operable to store program instructions executable by the CPU. A chip set operably couples the CPU and the memory to a... Agent: Baker Botts, LLP
20070011385 - Multifunction semiconductor storage device and a method for booting-up computer host: A semiconductor storage device connected to the host system through the general purpose interface, including a semiconductor storage media module (1) and a controller module (2), in which the controller module (2) consists of a general purpose interface control module (21), a microprocessor and control module (22). Various device class... Agent: Qun Liu
20070011386 - Usb host controller with memory for transfer descriptors: An electronic device, operating as a USB host, has an embedded processor and a system memory, connected by a memory bus. A host controller integrated circuit does not need to master the system memory, but instead acts purely as a slave. The embedded processor is then adapted to write the... Agent: Philips Intellectual Property & Standards
20070011388 - Dual port memory with asymmetric inputs and outputs, device, system: An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory interface further includes an asymmetric write data interface having a write bus width configured to transfer data from the memory... Agent: Trask Britt
20070011387 - Flexible width data protocol: A microprocessor interface system including a system bus with a bus clock and a data signal group in which multiple devices are coupled to the system bus. Each device is configured to perform a half-width data transaction on the system bus in which a doubleword is transferred for each of... Agent: Huffman Law Group, P.C.
20070011389 - Arbitration method and device: In an arbitration device, the entire transfer efficiency is improved without increasing the operating frequency and the number of pins. An overflow monitor mechanism generates an alarm once detecting a danger of occurrence of an overflow in an internal buffer group. An arbiter dynamically changes the priority order of arbitration... Agent: Mcdermott Will & Emery LLP
20070011390 - Method and related apparatus for controlling a peripheral device to transfer data to a bus: A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus... Agent: North America Intellectual Property Corporation
20070011391 - Transmitting data of a telematics terminal: Data of a telematics terminal is transmitted through an apparatus including a multimedia player, an audio interface, an embedded system, and a switch operatively connected between the audio interface and the embedded system. The multimedia player is configured to generate audio data, and the audio interface is configured to output... Agent: Fish & Richardson P.C.01/04/2007 > 18 patent applications in 15 patent subcategories. USPTO class patent listing
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