Electrical computers and digital data processing systems: input/output inventions 08/06

20060195618 - Data processing system, method, and computer program product for creation and initialization of a virtual adapter on a physical adapter that supports virtual adapter level virtualization: A method, computer program product, and distributed data processing system for directly sharing an I/O adapter that directly supports adapter virtualization and does not require an LPAR manager or other intermediary to be invoked on every I/O transaction is provided. The present invention also provides a method, computer program product,...

20060195617 - Method and system for native virtualization on a partially trusted adapter using adapter bus, device and function number for identification: A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to use a PCI adapter identifier to associate its resources to a system image and isolate them from other system images thereby providing I/O virtualization...

20060195621 - Signaling to a peripheral via irregular read operations: A peripheral communicates with a host according to a protocol such as USB. In case a user of the host is restricted by an operating system of the host from sending certain information to the peripheral, a pattern of protocol commands that includes one or more read commands is defined...

20060195619 - System and method for destroying virtual resources in a logically partitioned data processing system: A method, computer program product, and distributed data processing system for directly destroying one or more virtual resources that reside within a physical adapter and that are associated with a virtual host. Specifically, the present invention is directed to a mechanism for sharing conventional Peripheral Component Interconnect (PCI) I/O adapters,...

20060195620 - System and method for virtual resource initialization on a physical adapter that supports virtual resources: A method, computer program product, and distributed data processing system for directly sharing a network stack offload I/O adapter that directly supports resource virtualization and does not require a LPAR manager or other intermediary to be invoked on every I/O transaction is provided. The present invention also provides a method,...

20060195622 - Data input device, information equipment, information equipment control method, and computer program: A data input device transmits an input signal according to the position touched by an operating finger and an operation performed by the finger. The data input device includes a finger rest unit on which the finger is placed; a finger position sensor capable of detecting one of three positions,...

20060195624 - Disk array apparatus: A disk array apparatus using an SAS can transfer data without lowering a transfer efficiency of data even if rates of a plurality of physical links connected to a controller and storage device are different. A plurality of HDDs are connected to a controller through an expander. Data are transferred...

20060195623 - Native virtualization on a partially trusted adapter using pci host memory mapped input/output memory address for identification: A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to associate its resources to a system image and isolate them from other system images, thereby providing I/O virtualization is provided. Specifically, the present invention...

20060195625 - Unified usb otg controller: A USB (Universal Serial Bus) OTG (On-The-Go) controller device and more generally a serial bus control circuit chip are provided which have improved port handler implementations. In one example, different port handler units may be provided which selectively support host and device functionality at the respective ports. In another example,...

20060195626 - System and method for host initialization for an adapter that supports virtualization: A method, computer program product, and distributed data processing system that enables host software or firmware to map PCI adapter virtual resources to PCI bus addresses that are associated with a system image is provided. Virtual addresses maintained in a protection table segment assigned to a system image are mapped...

20060195627 - Detecting whether video source device is coupled to video display device: A video display device detects whether an output port of a video source device is communicatively coupled to an input port of the video display device, based on detecting a resistance at the output port of the video source device. In response to detecting that the output port of the...

20060195628 - System and method for dma transfer between fifos: A system for DMA transfer includes a CPU core having a DMA function, a first macro including a FIFO having a first bit width, and a second macro including a FIFO having a second bit width narrower than the first bit width, wherein an address signal fixing circuit is provided,...

20060195630 - Endianness independent data structures: Embedding endianness information within data and sending and receiving data with the embedded endianness information. Data may be contained in a data structure. To embed endianness information in a data structure, unused bits in a data structure are identified. A number of the unused bits are then selected based on...

20060195629 - Method of repeating data transmission between network devices: A method is provided for transmitting data from a transmitting device (121) to a receiving device (125). The transmitting device transmits a first data frame (200) to a receiving device a first time (3100). Then it consecutively transmits the first data frame to the receiving device second through Nth times...

20060195631 - Memory buffers for merging local data from memory modules: An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The...

20060195633 - Disk driver cluster management of time shift buffer: A file allocation system for a hard disk drive includes a memory with driver logic and a processor configured with the driver logic to receive a request to allocate hard disk space of a defined size for a buffer file. In some embodiments, the processor is configured with the driver...

20060195632 - Reliable management communications path algorithm using in-band signaling and high priority context processing: Disclosed herein is a highly reliable management communication path to the CPU of a network device using in-band signaling by periodically servicing the Ethernet MAC, such as during system tick and/or watchdog timer refresh interrupts. The servicing selectively processes frames that are uniquely destined to or originating from a managing...

20060195635 - Appliance with communication protocol emulation: An appliance includes a physical interface for communication according to a broad protocol and two functional components. The first functional component communicates via the physical interface. The second functional component includes a functional module adapted to communicate according to a narrow protocol and an emulation module that transforms between the...

20060195634 - System and method for modification of virtual adapter resources in a logically partitioned data processing system: A mechanism for modifying resources in a logically partitioned data processing system is provided. A request to modify resources associated with a virtual adapter allocated on a physical adapter is invoked. The resources associated with the virtual adapter comprise a subset of the physical adapter resources. The request to modify...

20060195636 - Large volume data management: In memory (memory-resident) compression tools are used to manage large volumes of data. Large volume data is transported in a compressed format. In memory compression software reads the data in its compressed format and then uncompresses the data in memory for data processing. After the data is uncompressed and aggregated...

20060195637 - Television with integrated signal switch for console and peripheral devices: A television with integrated signal switch (100) for sharing a television screen (14), a plurality of console devices compliant with an industry standard (16, 18) and at least one peripheral devices (20) with any computer system in a plurality of computer systems (12), is provided comprising a CPU (30); a...

20060195638 - Peripheral device: According to one embodiment, a peripheral device including a bus controller which controls input of transmission data from a host system via a bus and output of reception data to the host system via the bus, a communication controller which receives the transmission data from the bus controller to transfer...

20060195639 - System and method for dynamically allocating inter integrated circuits addresses to multiple slaves: A system for dynamically allocating inter integrated circuits (I2C) addresses to multiple slave includes a host (1), a plurality of slaves (2) and an I2C bus (3). Each slave includes a processor (20) for performing an I2C address allocating program (200), which includes a signal setting module (201), a delay...

20060195640 - Memory mapped i/o bus selection: A mechanism and method for redefining an application specific integrated circuit's I/O bus structure in real-time. The mechanism includes an address map block, a state machine block, and a bus arbitration block. At initialization, the address map is configured to divide the address space into regions and type of bus...

20060195641 - Method and apparatus for assigning bus grant requests: Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an identity and priority that...

20060195643 - Method for designing an initiatior in an integrated circuit: A method for designing an integrated circuit where the integrated circuit includes a plurality of modules and where each module includes an initiator port and a target port coupled to a distributed routing network. The initiator port is implemented by configuring whether the initiator or the distributed routing network is...

20060195642 - Method, system and program product for differentiating between virtual hosts on bus transactions and associating allowable memory access for an input/output adapter that supports virtualization: A method, system and computer program product that allows a System Image within a multiple System Image Virtual Server to maintain isolation from the other system images while directly exposing a portion, or all, of its associated System Memory to a shared PCI Adapter without the need for each I/O...

20060195645 - Interface for prototyping integrated systems: An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the...

20060195644 - Interrupt mechanism on an io adapter that supports virtualization: A mechanism for handling event notifications or interrupts in a logically partitioned computing system having IO adapters that support adapter virtualization are provided. A virtual adapter associated with a physical IO adapter detects an event, identifies a logical partition associated with the event, and writes an event notification entry in...

20060190629 - Method of automatically selecting channel to receive stream transmitted in ieee 1394 network: A method and system of automatically selecting a channel to receive a stream transmitted in an IEEE 1394 network is provided. The method and system include the steps of: a predetermined IEEE 1394 device belonging to the IEEE 1394 network, selecting a predetermined channel number by changing the channel number...

20060190630 - Apparatus and method to pass through data in a storage area network: An auxiliary controller is interposable intermediate a data source (such as one or more computers or one or more mass storage devices) and a data sink (such as one or more mass storage devices or one or more computers) to provide additional operations on s the data as desired without...

20060190631 - Method for configuring an input device and input device used therein: A method for configuring an input device that includes a housing, a plurality of user operable members installed on the housing, a calculating unit installed in the housing and coupled to the user operable members, and a memory installed in the housing and coupled to the calculating unit, includes the...

20060190634 - Computer chip set having on board wireless on board wireless interfaces to support parallel communication: A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized...

20060190633 - Display device featuring a reduced amount of time for detecting video input signals: A display device includes a plurality of video input interfaces. The display device also includes a display controller coupled to the plurality of video input interfaces. The display controller determines a sequence in which the plurality of video input interfaces are scanned for a video signal. The display controller makes...

20060190635 - Information processing apparatus and state control method of the same apparatus: According to a state control method used for an information processing apparatus of the present invention, an OS transits each device state of predetermined devices configuring the system of a computer to a state D3. Devices capable of transiting to D3hot are transited to a state D3hot, on the other...

20060190632 - Method for detecting dvi off-line mode and associated dvi receiver: A method for detecting the DVI off-line mode and associated DVI receiver are provided. The DVI receiver comprises a plurality of receiving channels, a clock channel, and an off-line mode detector. Each receiving channel receives a video signal and the clock channel receives a clock signal. Each receiving channel comprises...

20060190637 - Control apparatus, information processing apparatus, and data transferring method: A control apparatus has a memory, a processor, an input/output controller, and an interrupt controller. The processor is accessible to the memory. The input/output controller starts to transfer data from an input/output device to write the data to a given area in the memory not through the processor, reads data...

20060190636 - Method and apparatus for invalidating cache lines during direct memory access (dma) write operations: A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not...

20060190638 - Asynchronous jitter reduction technique: The amount of jitter incurred when reading data written into a FIFO can be reduced by clocking the FIFO with Read Clock pulses at a frequency χ ƒn where χ is a whole integer and ƒn is the frequency at which the memory is clocked to write data. Read Addresses...

20060190639 - Automatic adjustment of time a consumer waits to access data from a queue during a waiting phase and transmission phase at the queue: Provided are a method, system, and program automatic adjustment of time a consumer waits to access data from a queue during a waiting phase and transmission phase at the queue. A determination is made as to whether a queue is in a waiting phase or a transmission phase for data...

20060190641 - Buffer management in packet switched fabric devices: A buffer management system for cooperating with a packet based switching system is proposed. The purpose of this system is to reduce traffic congestion, ameliorate its effects, provide fairness to each data source, and to increase functionality while respecting advantageous system characteristics. Fabric output buffers include an arbitration function, a...

20060190640 - Data transfer system and data transfer method: A buffer memory temporarily stores data sequentially outputted to a data using apparatus. A memory is accessed by at least one memory access circuit via a bus. A data transfer circuit performs a data transfer from the memory to the buffer memory via the bus. The data transfer circuit performs...

20060190642 - Method and apparatus for testing, characterizing and monitoring a chip interface using a second data path: A data receiver circuit in a receiving chip provides the capability to characterize an interface, which includes one or more inter-chip communication lines, between a transmitting chip and the receiving chip by transmitting the data across a primary data path and a secondary data path, latching the data in the...

20060190644 - Data storewidth accelerator: Data storage controllers and data storage devices employing lossless or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth. In one embodiment of the invention, a composite disk controller provides data storage and retrieval acceleration using multiple caches for data pipelining and increased throughput. In another...

20060190643 - Method and system for compression of data for block mode access storage: A method and system for creating, reading and writing compressed data for use with a block mode access storage. The compressed data are packed into plurality of compressed units and stored in a storage logical unit (LU). One or more corresponding compressed units may be read and/or updated with no...

20060190645 - Methods for transmitting non-scsi commands via scsi commands: The present invention provides a method for transmitting a non-SCSI command via a SCSI command. A CDB for the SCSI command is provided. The CDB includes bytes byte—0, byte—1, byte—2, . . . , byte_n, in which byte —0 includes an opcode for the SCSI command. An opcode for the...

20060190646 - Motherboard having a non-volatile memory which is reprogrammable through a video display port: A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video signals to the video display port. A wired-OR circuit connects the graphics controller circuit to the controller to the port. Thus,...

20060190648 - Secure local network: A local network comprises at least one master and a plurality of slaves which can be controlled by the master via a data bus, with at least one slave being arranged in an unprotected region and at least one slave being arranged in n protected region. In this connection, data...

20060190647 - System and method for facilitating communication between devices on a bus using tags: Systems and methods for enabling a slave device to generate a tag that is an index into a buffer where the slave device stores information related to an active transaction such as a write command received by a master device. The tag is sent to the master device with a...

20060190649 - Plural bus arbitrations per cycle via higher-frequency arbiter: An arbiter in a bus system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or more arbitration operations in a single bus frequency clock cycle with one instance of arbitration logic. The...

20060190650 - Intergrated circuit with dynamic communication service selection: An integrated circuit comprising a plurality of modules (M1 to M5, CPU) for processing applications, a global memory (GM), which can be shared by said plurality of modules (M1 to M5, CPU), an interconnect means (IM) for interconnecting said modules (M1 to M5, CPU) and said global memory (GM) based...

20060190651 - Method and system for ordering requests at a bus interface: A bus bridge for coupling between a first bus and a second bus includes: multiple ticket registers; a ticket dispenser counter; and a ticket call counter. The ticket dispenser counter dispenses a ticket value to a request received at the bridge from the first bus for access to the second...

20060190652 - Mobile device expansion system: An expansion device is provided for expanding the functionality of a mobile electronic device while in a mobile mode and/or in a desktop mode. The expansion device may be a media slice that provides multimedia functionality to a mobile electronic device. The media slice may be configured to receive an...

20060190653 - Trusted lpc docking interface for docking notebook computers to a docking station: A method and apparatus for operating a portable computer configured for docking to a docking station is disclosed. In one embodiment, a portable computer system includes a docking interface having a bus switch and a bus monitoring circuit, and a bus coupled to the docking interface. With the computer coupled...

20060190654 - Method and apparatus for providing quality-of-service delivery facilities over a bus: The invention provides quality-of-service (QoS) delivery services over a computer bus having isochronous data transfer capabilities. A transmitting node on the bus transmits a message to an intended recipient indicating a requested bandwidth for a connection. If the intended recipient has sufficient resources, it allocates an isochronous data channel on...

20060190655 - Apparatus and method for transaction tag mapping between bus domains: An apparatus and method to provide tag mapping between bus domains across a bus bridge. The preferred embodiments provide a simple tag mapping design while maintaining unique IDs for all outstanding transactions for an overall increase in computer system performance. The preferred embodiment is a bus bridge between a GPUL...

20060190657 - Bus communication apparatus for programmable logic devices and associated methods: A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry and the programmable logic circuitry. The bridge circuitry further includes an information...

20060190656 - Flexible processing hardware architecture: A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and...

20060190658 - Amba modular memory controller: A system comprising a plurality of controller circuits, a plurality of line buffer circuits and an arbiter. The plurality of control circuits may each be configured to store data. The plurality of line buffer circuits may each be configured to transfer data between an accessed one of the controller circuits...

20060190659 - Computer system bus bridge: A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a...

20060190660 - Data ordering translation between linear and interleaved domains at a bus interface: A bus bridge for coupling between a first bus and a second includes: at least one data buffer; data load logic and data unload logic. The data load logic places received data in the at least one data buffer, wherein the data is received at the bus bridge from across...

20060190661 - Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer abvailability: A bus bridge for coupling between a first bus and a second bus includes: a number of data buffers for a particular request type; a counter for monitoring a number of requests of the particular type received at the bus bridge from the first bus for access to the second...

20060190662 - Transaction flow control mechanism for a bus bridge: A transaction flow control mechanism is disclosed for a bus bridge in a high speed computer system with a high speed interface for a graphics processor. A preferred embodiment provides a flow control mechanism for the bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business...

20060190663 - Chipset capable of supporting video cards of different specifications: The present invention provides a chipset comprising a north bridge with a PCI Express interface for coupling to a PCI Express video card and a south bridge with an AGP interface for coupling to an AGP video card, so as to enable the motherboard corresponding to the chipset to support...

20060190666 - Computer system and control method of the same: A computer system includes an information processing apparatus configured to incorporate a SCSI (Small Computer System Interface) command into a CBW (Command Block Wrapper), and transmits the CBW based on USB (Universal Serial Bus) protocol; and a peripheral apparatus configured to receive the CBW transmitted from the information processing apparatus,...

20060190665 - Data transfer control device and electronic equipment: A data transfer control device for data transfer through a bus including a state execution circuit conducting each state process of first-Nth states in order to perform a state control of the data transfer control device, a transfer controller performing a control for the data transfer based on a result...

20060190664 - Portable multi-purpose universal serial bus structure: The present invention is a portable multi-purpose universal serial bus (USB) structure, which refers to a storage unit that can be provided inside a casing and has a USB connector exposed out of one end of the casing. The casing can be a casing for a key, a vehicle anti-theft...

20060190668 - Computer system architecture: A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module....

20060190667 - Pipeline bit handling circuit and method for a bus bridge: A circuit and method to provide pipeline bit handling across a bus bridge between two different buses. In a preferred embodiment, the pipeline bit handling circuit provides rule enforcement for a P-bit address modifier across a bus bridge between two different buses with different rules for the P-bit address modifier....

20060184699 - Expansion apparatus for a vehicle display device: An expansion apparatus for a vehicle display device aims to upgrade and expand the function of a car ceiling display device without changing the original video and audio playing system. The expansion apparatus includes a body which houses a built-in multimedia processing equipment. The body has one side fastened to...

20060184701 - Position changing apparatus: The present invention provides a position changing apparatus for moving a vehicle body or a vehicle part that includes a jig base, a guide unit forming a slanted guide surface, a driving block, an actuator, and an attaching unit. In addition, all components of the position changing apparatus are simplified,...

20060184700 - System and method for sharing a device across operating systems: A system for sharing a device across a plurality of operating systems is provided. The system includes a sharable bit in the namespace for identifying whether the device is sharable. The system further includes one or more operating systems that are adapted to recognize the sharable bit....

20060184702 - Apparatus and related method for sharing address and data pins of a cryptocard module and external memory: A digital television (DTV) system comprises a front-end circuit comprises a demodulator circuit for producing a non-decrypted transport stream signal; a back-end circuit for decoding transport stream data; an external memory coupled to the back-end circuit; an address bus and a data bus to which the external memory is coupled...

20060184703 - Information communication device and condition setting method: A multifunctional device extracts identification information items from received device-cloning file data items and determines whether a data restoration process is a backup process or a cloning process based on whether or not a serial number in the identification information items is identical with a serial number in a multifunctional...

20060184704 - Balanced technology extended (btx) motherboard assembly: A Balanced Technology Extended (BTX) motherboard assembly includes a motherboard, first and second expansion slots provided on the motherboard, and a riser card. The motherboard complies with the Balanced Technology Extended (BTX) specification. The first expansion slot complies with the Peripheral Component Interconnect Express (PCIE) specification. The second expansion slot...

20060184705 - Communication system, digital camera and docking apparatus: Wireless communications between a digital camera and a printer dock are established in a simple manner. A processor (10f) of a digital camera (10) detects a printer dock (12) within communication range via a communications circuit (10e) and its ID is acquired. The processor (10f) uses the acquired ID to...

20060184706 - Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip link: The present invention, a multiprocessor chip pervasive command interface, collects different types of pervasive commands into individual queues for each command type. As permitted by various grouping rules, valid commands are grouped together into one single command and placed on a functional interchip communications bus. This grouping of commands maximizes...

20060184707 - Error injection: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but...

20060184708 - Host controller device and method: A host controller (400) for interfacing one or more electronic devices (410, 411) to a packet-based timeshared bus, such as a system bus (402) or a universal serial bus (409), is disclosed. The host controller (400) comprises a first memory device (413) storing a sequence of predetermined transaction descriptors (TD)...

20060184709 - Usb memory storage apparatus: An integrated semiconductor memory device for use within an integrated USB memory apparatus has a controller, a flash memory in communication with the controller, a USB interface circuit in communication with the memory controller, and an integrated circuit package for maintaining at least one of the controller, the flash memory,...

20060184710 - Bridge between a single channel high speed bus and a multiple channel low speed bus: An apparatus for enabling communication between components in a network device includes a network processor providing data signals based on a PLx format; a multiport I/O controller having an IX bus interface and a plurality of MAC layer interfaces; and a bridge for bi-directionally converting the streaming data from the...

20060184712 - Switch architecture independent of media: A network device for handling data and a method for handling data in a network device are disclosed. The network device includes at least one media port and at least one high speed docking station, communicating with the at least one media port. At least one master is provided in...

20060184711 - Switching apparatus and method for providing shared i/o within a load-store fabric: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains (OSDs)...

20060174040 - Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism: A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver,...

20060174041 - Information providing apparatus for performing data processing in accordance with order from user: This invention is a photosite which allows access from a cell phone to provide user-friendlier services. The photosite creates an ID (S6501) and creates a character string Str from the ID by combining numerals and alphabetical characters by using a storage unit which stores buttons 0 to 9 of the...

20060174042 - Method, device and system for the exchange of data via a bus system: A method is described for exchanging data in messages between at least two stations connected via a bus system, the messages containing the data being transmitted by the stations over the bus system and the messages being controlled over time by a first station in such a manner that the...

20060174043 - Apparatus and method for usb data transmission in hybrid terminal including two cpus: An apparatus and a method for sharing an USB port and transmitting data in a hybrid terminal including both two CPUs and memories corresponding to the two CPUs are disclosed. In the apparatus and the method, an external apparatus, for which the hybrid terminal performs USB data transmission/reception, recognizes the...

20060174044 - Multiple master inter integrated circuit bus system: A multiple-master Inter Integrated Circuit (“I2C) bus system includes a first master device including a first processing device within a first power boundary and a second master device including a second processing device within a second power boundary connected through a single I2C bus to one or more slave devices....

20060174045 - Bus arbitration method and semiconductor apparatus: An access priority in bus arbitration is changed based on a cache hit ratio so as to perform the bus arbitration. In order to perform the bus arbitration, a cache hit ratio measuring device investigates a status of a cache access by a bus master. A bus arbitration managing device...

20060174046 - Slot device: A PC card slot device for an ExpressCard affords a smooth insertion of the ExpressCard into a slot for the PC card slot device, without the height of the slot being increased. A lower chassis ceiling wall defines the lower face side of a card storage space, and also includes...

20060174048 - Apparatus for interconnecting a plurality of process nodes by serial bus: Before the link of each port of a switch provide with a plurality of ports for interconnecting a plurality of process nodes by a serial bus is established, it is checked whether each process node is mounted. Then, of the plurality of ports, a port to which one of mounted...

20060174047 - Dual use modular pci/pci express interface: Techniques where PCIe is implemented using connectors that are compatable with Cardbus/MPCl connectors. One technique implements PCIe on unused pins on Cardbus/MPCl connectors. An advantage of this implementation is that it provides a single, smaller connection point than utilizing separate connectors. Another technique is to add additional pins to a...

20060174049 - Usb to sata bridge system: A bridge system for heter-serial interfaces, which is connected to a host. The bridge system includes a host interface controller, a memory, a controller and a device interface controller. The controller controls the host interface controller and the device interface controller such that the data or commands sent by the...

20060174050 - Internal data bus interconnection mechanism utilizing shared buffers supporting communication among multiple functional components of an integrated circuit chip: An integrated circuit chip includes multiple functional components and a central interconnect module providing communication among the functional components. The central interconnect module includes a buffer which is shared by the sending and receiving components. Preferably, some components perform different functions and communicate with the central interconnect via a common...

20060174051 - Method and apparatus for a redundancy approach in a processor based controller design: A system for handling data of a process with a primary controller and a redundant controller. The primary controller includes a primary processor that is operable to perform tracking data tasks by using a low speed bus to cooperate with a tracker controller for storage of tracking data in a...

20060174052 - Integrated circuit and information processing device: In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by a transferring buffer which is provided on a...