Electrical computers: arithmetic processing and calculating inventions

20090271461 - Semiconductor integrated circuit: There is provided a semiconductor integrated circuit including: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks inputting data of a first bit width and performing computation; a first network connecting the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality... Agent: Arent Fox LLP

20090271462 - Keyed pseudo-random number generator: A method and apparatus for client authentication using a pseudo-random number generation system. The pseudo-random number generation utilizes a secret key as well as state information as input into the hash function to generate a pseudo-random number. The state information that is part of the input can be any number... Agent: Red Hat/bstz Blakely Sokoloff Taylor & Zafman LLP

20090271463 - Pseudorandom number generator and data communication apparatus: The present invention is directed to improve leak analysis resistance by improving randomness of a pseudorandom number. A pseudorandom number generator as a representative embodiment of the invention includes a shift resistor obtained by coupling a plurality of flip flop circuits and can generate a pseudorandom number by shifting signals... Agent: Miles & Stockbridge PC

20090271464 - Arithmetic or logical operation tree computation: A method of computing at least a first and a second tree of arithmetic or logical operations on a microprocessor comprising at least n parallel processing elements. The method comprises: a) executing (in 48) n arithmetic or logical operations of a first iteration of the first tree in parallel using... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090271465 - Configurable hybrid adder circuitry: Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be... Agent: Treyz Law Group

20090265404 - Fast singular value decomposition for expediting computer analysis system and application thereof: The present invention uses a computer analysis system of a fast singular value decomposition to overcome the bottleneck of a traditional singular value decomposition that takes much computing time for decomposing a huge number of objects, and the invention can also process a matrix in any form without being limited... Agent: Wpat, PC Intellectual Property Attorneys

20090265405 - Adder for obtaining maximum accumulated value of correlation for mode detection in communication system and adding method using the adder: Disclosed are an adder for obtaining a maximum accumulated value of correlation for mode detection in a communication system, and an adding method using the adder. According to the present disclosure, an adder for obtaining a maximum accumulated value of correlation values used to detect a mode in an orthogonal... Agent: Fish & Richardson, PC

20090265406 - Decision feedback equalizer having parallel processing architecture: An integrated circuit includes a decision feedback equalizer (DFE) including a first and second digital equalizer logic including circuitry to compensate first and second bits in a received stream and to provide first and second sign bits. The second equalizer logic can run concurrently and can be connected in parallel... Agent: Texas Instruments Incorporated

20090265407 - Method and system for determining altitude, longitude, and lattitude from earth orthogonal coordinate system: A method and system for a method and system is provided for transforming geocentric, rectangular coordinates to geodetic coordinates. A meridian plane containing a given point reckoned in geocentric rectangular coordinates is determined, and a line though the given point and normal to a reference ellipsoid of a geodetic coordinate... Agent: Honeywell International Inc. Patent Services

20090265408 - Methods and apparatus for performing calculations using reduced-width data: Methods, apparatus, and articles of manufacture for performing calculations using reduced-width data are disclosed. In particular, an example method determines reduced-width data values associated with generating and evaluating functions. Some of the reduced-width data values are stored within instructions in an instruction memory during a compile phase and retrieved from... Agent: Brinks Hofer Gilson & Lione/marvell

20090265409 - Processor for performing multiply-add operations on packed data: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090265410 - Packed add-subtract operation in a microprocessor: A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word... Agent: Schwegman, Lundberg & Woessner / Atmel

20090265411 - Cryptographic authentication apparatus, systems and methods: Apparatus, systems, and methods send an interrogation command from an interrogation and timing apparatus to a timed identification (TID) apparatus. The TID apparatus receives the interrogation command, performs a series of logical operations to calculate a response, and returns the response within a maximum length of time established by the... Agent: Schwegman, Lundberg & Woessner, P.A.

20090259703 - Handling mask and range constraints: Handling mask and range constraints. For example, a method of handling range and mask constraints, may include determining whether or not to utilize a mask constraint and a range constraint by determining whether or not the range and mask constraints are satisfiable. Other embodiments are described and claimed.... Agent: Ibm Corporation, T.j. Watson Research Center

20090259704 - Generating a number based on mask and range constraints: Generating a number based on mask and range constraints. For example, a method of generating a pseudo random number satisfying a range constraint and a mask constraint may include determining a number of possible solutions satisfying the range constraint and the mask constraint; selecting an index representing a solution of... Agent: Ibm Corporation, T.j. Watson Research Center

20090259705 - Method and structure for provably fair random number generator: A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.... Agent: Mcginn Intellectual Property Law Group, PLLC

20090259706 - Method for establishing a simulating signal suitable for estimating a complex exponential signal: A method for establishing a simulating signal suitable for estimating a complex exponential signal includes the following computer-implemented steps: sampling a time domain signal of a physical system to obtain a sampling signal; transforming the sampling signal to a frequency domain signal using Fast Fourier Transform; determining parameters of the... Agent: Townsend And Townsend And Crew, LLP

20090259707 - Method and device for fast correlation calculation: The field of the invention is that of the reception of a radionavigation signal originating from a satellite positioning system such as the GPS system. The present invention concerns a method for calculating correlations between a first sequence and a second sequence, said first sequence and said second sequence having... Agent: Lowe Hauptman Ham & Berner, LLP

20090259708 - Apparatus and method for optimizing the performance of x87 floating point addition instructions in a microprocessor: A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and generates a sum from its addends. The FPU determines whether any conditions exist in the addends with respect to their contribution... Agent: Huffman Law Group, P.C.

20090259709 - Method and apparatus for adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control: Various components of the present invention are collectively designated as Adaptive Real-Time Embodiments for Multivariate Investigation of Signals (ARTEMIS). It is a method, processes, and apparatus for measurement and analysis of variables of different type and origin. In this invention, different features of a variable can be quantified either locally... Agent: Frank B. Flink, Jr, Esq. Griffin, Flink, And Watson, LLC

20090254597 - Programmable calculator having guided calculation mode: A programmable calculator includes: a display unit; a calculation processing section configured to perform calculation processing; a calculation screen display control section configured to control the display unit to display a calculation screen; a base state setting section configured to set, as a base state, a calculation state; a base... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090254598 - Folding of input data values to a transform function: A method of processing a set of input data values comprises the steps of providing said input data values serially to circuitry comprising a number of memory elements; and performing in said circuitry a transform function to obtain a set of transformed data values. The method further comprises the steps... Agent: Potomac Patent Group PLLC