|Electrical computers: arithmetic processing and calculating patents - Monitor Patents|
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Electrical computers: arithmetic processing and calculatingBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/16/2013 > 9 patent applications in 7 patent subcategories.
20130124587 - Circuit for a radio system, use and method for operation: A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock... Agent:
20130124586 - Method and apparatus for evaluation of mathematical functions: An aspect includes an apparatus for evaluating a mathematical function at an input value. The apparatus includes a selector for selecting a mathematical function, an input for a value at which to evaluate the function, an identifier for identifying an interval containing the input value. The interval is described by... Agent: Imagination Technologies Limited
20130124589 - Compression and decompression of numerical data: The invention relates to a computer-implemented method for compressing numerical data comprising a structured set of floating point actual values. A floating point value is defined by a sign, an exponent and a mantissa. The method comprises computing a floating point predicted value related to a target actual value of... Agent: Dassault Systemes
20130124588 - Encoding densely packed decimals: According to one aspect of the present disclosure, a method and technique for encoding densely packed decimals is disclosed. The method includes: executing a floating point instruction configured to perform a floating point operation on decimal data in a binary coded decimal (BCD) format; determining whether a result of the... Agent: International Business Machines Corporation
20130124590 - Reconfigurable cyclic shifter arrangement: In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4×4... Agent: Lsi Corporation
20130124591 - Random number generation using switching regulators: Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from... Agent:
20130124592 - Operand-optimized asynchronous floating-point units and method of use thereof: Asynchronous arithmetic units including an asynchronous IEEE 754 compliant floating-point adder and an asynchronous floating point multiplier component. Arithmetic units optimized for lower power consumption and methods for optimization are disclosed.... Agent: Cornell University
20130124593 - Quantifying mehtod for intrinsic data transfer rate of algorithms: The quantifying method for intrinsic data transfer rate of algorithms is provided. The provided quantifying method for an intrinsic data transfer rate includes steps of: detecting whether or not a datum is used; providing a dataflow graph G including n vertices and m edges, and a Laplacian matrix L having... Agent: National Cheng Kung University
20130124594 - Divider circuitry with quotient prediction based on estimated partial remainder: An integrated circuit comprises divider circuitry configured to perform a division operation. The divider circuitry may be part of an arithmetic logic unit or other computational unit of a microprocessor, digital signal processor, or other type of processor. The divider circuitry iteratively determines bits of a quotient over multiple stages... Agent: Lsi Corporation05/09/2013 > 5 patent applications in 5 patent subcategories.
20130117341 - Decimal elementary functions computation: A method for executing a decimal elementary function (DEF) computation from multiple decimal floating-point operands, including: extracting mantissae and exponents from the operands; generating normalized mantissae by shifting the mantissae based on the number of leading zeros; calculating a plurality of approximations for a logarithm of the first normalized mantissa;... Agent: Silminds, LLC, Egypt
20130117342 - Combined rf equalizer and i/q imbalance correction: Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction;... Agent: Lsi Corporation
20130117343 - Unified forward and inverse transform architecture: Multiple transform sizes improve video coding efficiency, but also increase the implementation complexity. Furthermore, both forward and inverse transforms need to be supported in various consumer devices. Embodiments provide a unified forward and inverse transform architecture that supports computation of both forward and inverse transforms for multiple transforms sizes using... Agent: Texas Instruments Incorporated
20130117344 - Methods and systems for decoding polar codes: Coding within noisy communications channels is essential but a theoretical maximum rate defines the rate at which information can be reliably transmitted on this noisy channel. Capacity-achieving codes with an explicit construction eluded researchers until polar codes were proposed. However, whilst asymptotically reaching channel capacity these require increasing code lengths,... Agent:
20130117345 - Parallel self-timer adder (pasta): A parallel self-timed adder (PASTA) is disclosed. It is based on recursive formulation and uses only half adders for performing multi-bit binary addition. Theoretically the operation is parallel for those bits that do not need any carry chain propagation. Thus the new approach attains logarithmic performance without any special speed-up... Agent: University Of Malaya05/02/2013 > 5 patent applications in 5 patent subcategories.
20130110895 - Systems and methods employing unique device for generating random signals and metering and addressing, e.g., unusual deviations in said random signals: According to some embodiments, a system comprises a generator of a truly random signal is connected to an input and feedback device for the purpose of providing a user with real time feedback on the random signal. The user observes a representation of the signal in the process of an... Agent: Psyleron, Inc.
20130110896 - Logarithmic/inverse-logarithmic conversion circuit: A logarithmic conversion circuit comprises: an operation amplifier; an input resistor connected at a preceding stage of an inverting input terminal, of the operation amplifier, to which a current signal is inputted; and a logarithmic conversion device and a current feedback device connected in series between the inverting input terminal... Agent: Mitsubishi Electric Corporation
20130110897 - Digital filter having improved attenuation characteristics: A digital filter having improved attenuation characteristics is disclosed. The disclosed performs upsampling of model filter response by applying a sampling kernel scaled by a sampling constant. The disclosed filter has good attenuation characteristics with small number of taps and pass bands of the digital filter can be changed with... Agent: Industry-university Cooperation Foundation Hanyang University
20130110898 - Apparatus for signal processing: A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one... Agent: Stmicroelectronics International Nv
20130110899 - Distributed processing system and method for discrete logarithm calculation: Distributed processing system and method for discrete logarithm calculation. The speed and resource efficiency of discrete logarithm calculation may be improved by allowing a plurality of operation agents to distributively process an operation of generating a modulo multiplication auxiliary table, an operation of generating a pre-calculation table, and an operation... Agent: Samsung Sds Co., Ltd.04/25/2013 > 4 patent applications in 4 patent subcategories.
20130103730 - Microprocessor shifter circuits utilizing butterfly and inverse butterfly routing circuits, and control circuits therefor: Microprocessor shifter circuits utilizing butterfly and inverse butterfly circuits, and control circuits therefor, are provided. The same shifter circuits can also perform complex bit manipulations at high speeds, including butterfly and inverse butterfly operations, parallel extract and deposit operations, group operations, mix operations, permutation operations, as well as instructions executed... Agent: Teleputers, LLC
20130103731 - Systems and methods for efficient data channel testing: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a pseudo-random sequence generator circuit, a decoder circuit, and a pseudo-random sequence reconstitution circuit. The data detector circuit is operable to apply a... Agent: Lsi Corporation
20130103732 - Circular floating-point number generator and a circular floating-point number adder: One aspect of the present invention will provide a circular floating-point number generator (400) for generating, from an input fixed-point number, a circular floating-point number including sign-bit field (S), exponent field (E), and circular-mantissa field (M). The generator assigns the input bits in the fixed-point number to a plurality of... Agent: Telefonaktiebolaget Lm Ericsson (publ)
20130103733 - Method and apparatus for use in the design and manufacture of integrated circuits: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using... Agent: Imagination Technologies LimitedPrevious industry: Data processing: database and file management or data structures
Next industry: Electrical computers and digital processing systems: multicomputer data transferring or plural processor synchronization
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