Electrical computers: arithmetic processing and calculating patents  Monitor Patents 

USPTO Class 708  Browse by Industry: Previous  Next  All 07/2010  Recent  14: Sep  Aug  Jul  Jun  May  Apr  Mar  Feb  Jan  13: Dec  Nov  Oct  Sep  Aug  Jul  Jun  May  Apr  Mar  Feb  Jan  12: Dec  Nov  Oct  Sep  Aug  July  June  May  April  Mar  Feb  Jan  11: Dec  Nov  Oct  Sep  Aug  Jul  Jun  May  Apr  Mar  Feb  Jan  10: Dec  Nov  Oct  Sep  Aug  Jul  Jun  May  Apr  Mar  Feb  Jan   09: Dec  Nov  Oct  Sep  Aug  Jl  Jn  May  Apr  Mar  Fb  Jn   2008  2007  Electrical computers: arithmetic processing and calculating July category listing 07/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/29/2010 > patent applications in patent subcategories. category listing 20100191786  Digital signal processing block with preadder stage: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a... Agent: Xilinx, Inc Attn: Legal Department 20100191788  Multiplier with shifter: A digital system has a memory configured to hold operands and a multiplyshift unit coupled to the memory and configured to receive a first operand and a second operand from the memory in parallel, wherein the first operand includes a concatenated encoded shift amount. The multiplyshift unit includes a multiplier... Agent: Texas Instruments Incorporated 20100191787  Sequential multiplier: A sequential multiplier for multiplying a binary multiplier and a binary multiplicand to produce a final product. A first logic circuit generates a control signal based on the multiplier. A second logic circuit generates a partial product based on the control signal and the multiplicand. A full adder generates a... Agent: Henneman & Associates, PLC 20100191789  Method for regulating an actual value of a variable characterizing a position of an actuator, computer program product, computer program, and recording medium: A method is provided for regulating an actual value of a variable, which characterizes a position of an actuator, to a setpoint value using a regulator, which method makes it possible to optimize regulation in terms of bandwidth, stability, accuracy, and sturdiness. A predefined time characteristic of the setpoint value... Agent: Kenyon & Kenyon LLP 20100191790  System and method for correlation scoring of signals: Systems, methods and computer readable storage media are provided for identifying, in a signal of interest, signal segments matching a reference signal segment. A processor coupled to memory is adapted to perform operations including: converting the reference signal segment to a first vector characterized by n pairs of data points,... Agent: Agilent Technologies Inc. 20100191791  Method and apparatus for evaluation of multidimensional discrete fourier transforms: A device and method for evaluating multidimensional discrete Fourier transforms (DFT) by eliminating transpose operations by transforming every dimension concurrently. At least one computing node is enabled to evaluate a DFT of one of a multidimensional input data set and a subgroup of the input data set, wherein the subgroup... Agent: Perry + Currier Inc. 20100191792  Signal processing with fast stransforms: The ability to examine the frequency content of a signal is critical in a variety of fields, and many techniques have been proposed to fill this need, including the Fourier and wavelet family of transforms. One of these, the Stransform, is a Fourier based transform that provides simultaneous time and... Agent: Fulbright & Jaworski L.L.P. 20100191793  Symbolic computation using treestructured mathematical expressions: A method for performing symbolic computations on a mathematical expression. The mathematical expression may be converted to a tree structure having one or more parent nodes and one or more child nodes. Each parent node may be a mathematical operation. Each child node may be a mathematical expression on which... Agent: Microsoft Corporation 07/22/2010 > patent applications in patent subcategories. category listing20100185715  Method and device for transform computation: A method of operating a dataprocessing unit to produce a transform comprises calculating first and second output data values based at least on first and second input data values. The method comprises reading the first and second input data values from locations of a first buffer, the locations being determined... Agent: Potomac Patent Group PLLC 20100185716  Eigenvalue decomposition apparatus and eigenvalue decomposition method: The present invention provides an eigenvalue decomposition apparatus that can perform processing in parallel at high speed and high accuracy. The eigenvalue decomposition apparatus comprises a matrix dividing portion 14 that repeatedly divides a symmetric tridiagonal matrix T into two symmetric tridiagonal matrices, an eigenvalue decomposition portion 15 that performs... Agent: Kenealy Vaidya LLP 07/15/2010 > patent applications in patent subcategories. category listing20100179974  Signal processing method for hierarchical empirical mode decomposition and apparatus therefor: A signal processing method for performing hierarchical empirical mode decomposition (HEMD) and an apparatus therefor are provided. In an embodiment, when empirical mode decomposition is performed on an input signal, an artificial assisting signal and the input signal are combined to assist the search for extrema and frequency reduction is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP 20100179975  Method for decomposing barrel shifter, decomposed circuit and control method thereof: A method for decomposing a barrel shifter decomposes N, the number of digits of input word, into N1 to Nm, and utilizes m layers of shifter circuit layer, which are composed of a plurality of barrel shifters, such that each barrel shifter performs a shifting procedure to obtain the desired... Agent: Hamre, Schumann, Mueller & Larson, P.C. 20100179976  Semiconductor device performing operational processing: A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand,... Agent: Mcdermott Will & Emery LLP 20100179977  Sampled filter with finite impulse response: According to the invention, there is proposed an FIR filter comprising a transconductance amplifier with controllable gain (AGM), at least one sampling capacitor (CE) intended to receive an output current (di) from the amplifier and to periodically accumulate the charges produced by N successive samples of this current, and means... Agent: Lariviere, Grubman & Payne, LLP 20100179978  Fftbased parallel system with memory reuse scheme: A method may include storing N number of Fast Fourier Transform (FFT) data points into xmemories, N and x being integers greater than one, and the xmemories having a total memory capacity equivalent to store the N number of FFT data points, and reading K FFT data points of the... Agent: Harrity & Harrity, LLP 07/08/2010 > patent applications in patent subcategories. category listing20100174764  Reuse of rounder for fixed conversion of log instructions: A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is... Agent: Cantor Colburn LLP  IBM Tuscon Division 20100174765  Performing variable and/or bitwise shift operation for a shift instruction that does not provide a variable or bitwise shift option: Some embodiments present a method of performing a variable shift operation. This method can be used by a microprocessor that does not allow variable shift operation for certain operand sizes. The method simulates a shift instruction that shifts an operand by a shift count. The method identifies a first shift... Agent: Adeli & Tollen, LLP 20100174766  Magnetic precession based true random number generator: A method and apparatus for generating a random logic bit value. In some embodiments, a spin polarized current is created by flowing a pulse current through a spin polarizing material. The spin polarized current is injected in a free layer of a magnetic tunneling junction and a random logical bit... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC) 20100174767  Efficient filtering with a complex modulated filterbank: A filter apparatus for filtering a time domain input signal to obtain a time domain output signal, which is a representation of the time domain input signal filtered using a filter characteristic having an nonuniform amplitude/frequency characteristic, comprises a complex analysis filter bank for generating a plurality of complex subband... Agent: Glenn Patent Group 20100174768  Digital signal processing circuit and method comprising band selection: A digital signal processing circuit comprises a band selector (14) for selecting at least one subband from a frequency spectrum of a digital sampled input signal. The band selector (14) comprises a plurality of processing branches corresponding to respective phases and an adder (28a, 28b) for adding branch signals from... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing 20100174769  Inplace fast fourier transform processor: An Npoint Fast Fourier Transform (FFT) using mixed radix stages with inplace data sample storage may be performed by decomposing N into a product of R sequential mixed radix stages of radixr(i). N data samples are partitioned into at least B memory banks, where B is equal to a largest... Agent: Texas Instruments Incorporated 07/01/2010 > patent applications in patent subcategories. category listing20100169396  Efficient computation for eigenvalue decomposition and singular value decomposition of matrices: For eigenvalue decomposition, a first set of at least one variable is derived based on a first matrix being decomposed and using Coordinate Rotational Digital Computer (CORDIC) computation. A second set of at least one variable is derived based on the first matrix and using a lookup table. A second... Agent: Qualcomm Incorporated 20100169397  Mobile terminal and unit converting method thereof: A mobile terminal and its unit conversion method are disclosed. When a unit conversion function is selected through a menu manipulation by a user, the selected unit conversion function is executed, and then, when a unit conversion factor for a unit conversion is selected, a reference unit related to the... Agent: Ked & Associates, LLP 20100169398  Method and apparatus having a measured value input for applying a measured value: The invention pertains to a device such as a sensor, operator device, communication device, or a liquid level metering device, with a measured value input to apply a measured value. The device includes at least a first memory region to provide for an adjustment factor, and a computer, which is... Agent: Lackenbach Siegel, LLP 20100169400  Partially random permutation sequence generator: Embodiments of the present disclosure provide methods, systems, and apparatuses related to a partially random permutation sequence generator. Other embodiments may be described and claimed.... Agent: Schwabe, Williamson & Wyatt, P.C. 20100169399  Personal identification number (pin) generation between two devices in a network: A method of generating a Personal Identification Number (PIN) between a first device and a second device in a network is provided. The method includes securely receiving information of input choices of the second device and random numbers assigned to the input choices at the first device. At the first... Agent: Motorola, Inc. Law Department 20100169401  Filter for network intrusion and virus detection: Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an... Agent: Larry Mennemeier C/o Intellevate, LLC 20100169402  Fast fourier transform processor: An FFT processor is disclosed, which includes a first multipipelined MDC unit, a second multipipelined MDC unit and a switching network. The first multipipelined MDC unit and the second multipipelined MDC unit respectively employ a plurality of MDC circuits to change the positions of the delayers thereof in parallel way.... Agent: Jianq Chyun Intellectual Property Office 20100169403  System for matrix partitioning in largescale sparse matrix linear solvers: A system for solving largescale matrix equations comprises a plurality of field programmable gate arrays (FPGAs), a plurality of memory elements, a plurality of memory element controllers, and a plurality of processing elements. The FPGAs may include a plurality of configurable logic elements and a plurality of configurable storage elements.... Agent: Hovey Williams LLP 20100169404  Flexible accumulator in digital signal processing circuitry: A multiplieraccumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiplyandaccumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs)... Agent: Ropes & Gray LLP Previous industry: Data processing: database and file management or data structuresNext industry: Electrical computers and digital processing systems: multicomputer data transferring or plural processor synchronization ###### RSS FEED for 20140904: Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates. For more info, read this article. ###### Thank you for viewing Electrical computers: arithmetic processing and calculating patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers: arithmetic processing and calculating patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers: arithmetic processing and calculating patents we recommend signing up for free keyword monitoring by email. Results in 0.26391 seconds 
PATENT INFO 