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Electrical computers: arithmetic processing and calculating December patent applications/inventions, industry category 12/09

20090327378 - Instruction-based parallel median filtering: An instruction-based parallel median filtering processor and method sorts in parallel each combination of pairs of inputs into greater and lesser values; determines from that sorting the minimum, maximum and median filter values of the inputs; processes one of those values and provides the processed value as an input; and... Agent: Goodwin Procter LLP Patent Administrator

20090327379 - Random number generating device: A random number generating device includes: a pulse voltage generator configured to generate a pulse voltage having an amplitude of 26 mV or more; a random noise generating element including source and drain regions formed at a distance from each other on a semiconductor substrate, a tunnel insulating film formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090327380 - Circuit and method of generating a random number using a phass-locked-loop circuit: A circuit that generates a random number includes a phase-locked loop circuit and a sampling circuit. The phase-locked loop circuit generates an internal clock signal that is synchronized with a reference signal in which the internal clock has a random noise. The sampling circuit samples the reference signal in response... Agent: Mills & Onello LLP

20090327382 - Pseudo-random number generation device, stream encryption device and program: A pseudo-random number generation device having a resistance against attack methods that use the number of operations of an LFSR, a stream encryption device, and a program are provided. The stream encryption device has: means (delay means 811 to 81N) which exclusively operate with each LFSR (801 to 80N) in... Agent: Sughrue Mion, PLLC

20090327381 - True random number generator: The present invention relates to an apparatus for generating a true random number comprising: (a) one or more decoupled oscillator(s), for generating a first set of one or more random bit(s); (b) one or more clock sampler(s), for generating a second set of one or more random bit(s); (c) a... Agent: Kevin D. Mccarthy Roach Brown Mccarthy & Gruber, P.C.

20090327383 - Sinusoidal wave generation circuit: There are provided a coefficient ROM 1 for storing coefficients representing angular frequencies corresponding to a desired frequency and a sampling frequency, that is, two types of coefficients for a single desired frequency, an accumulated addition calculating portion 2 for using one of the coefficients until an accumulated addition value... Agent: Connolly Bove Lodge & Hutz LLP

20090327384 - System and method for active diplexers: The present invention relates to methods and systems for signal filtering in electronic devices and more particularly, some embodiments related to methods and systems for filtering of radio frequency (RF) signals. In some embodiments, a filter circuit may comprise a down-converter, a filter, coupled to the down-converter and configured to... Agent: Sheppard Mullin Richter & Hampton LLP

20090327385 - Filter structure and method for filtering an input signal: The invention relates to a method and filter structure for filtering an input signal, which is applied to an input (1) of the filter structure, having a symbol rate. The input signal is guided to multiple parallel branches of the filter structure connected to the input (1), in which at... Agent: Central Coast Patent Agency, Inc

20090327386 - Combined deblocking and denoising filter: An apparatus, a computer readable medium to instruct a process to implement a method, and a method of reducing blocking artifacts and/or noise in an image that has been compressed by a block-based encoding process. The method includes deblocking the image using overlapped forward directional transforms, the overlapped forward directional... Agent: Dov Rosenfeld

20090327387 - Digital generation of an accelerated or decelerated chaotic numerical sequence: A method for generating an accelerated and/or decelerated chaotic sequence. The method involves selecting a plurality of polynomial equations constructed from an acc-dec variable v. The method also involves selecting a value for the acc-dec variable v for advancing or stepping back a chaotic sequence generation by at least one... Agent: Harris Corporation C/o Darby & Darby PC

20090327388 - Static logic ling adder: In general, in one aspect, the disclosure describes a prefix tree adder. The adder may be used to add two strings of bits or multiply a string of bits by 3. First group carry generate and propagate signals are calculated directly from inputs to the adder using Ling equations and... Agent: RyderIPLaw C/o Cpa Global

20090319589 - Using fractional exponents to reduce the computational complexity of numerical operations: Technologies are described herein for using efficient log-linear transformations to reduce the complexity of numerical computations. Efficient transforms can convert between linear fixed point values and log space values in about ten processor cycles per sample. A fractional exponent and an integer exponent may be combined together into a log... Agent: Microsoft Corporation

20090319591 - Embedded data dna sequence security system: An embedded data DNA sequence security system which utilizes an embedded data DNA sequence to differentiate each of a plurality of identifiable objects.... Agent: Cr Miles, P.C. Craig R. Miles

20090319590 - Method and device for generating a psuedorandom sequence: A method of generating a pseudorandom sequence of terms belonging to a finite body K of cardinal q≧2 intended to be used in a cryptographic procedure, said method comprising the iterative calculation, from an initialization n-tuple X(0)=(X(0)1, X(0)2, . . . , X(0)n), where n≧2, of elements of K, of... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090319592 - Parallel processing method of tridiagonalization of real symmetric matrix for shared memory scalar parallel computer: When a real symmetric matrix is tridiagonalized using a shared memory scalar parallel computer, the matrix is divided into threads to be updated. In the updating, the data of the lower triangular portion is for the calculation utilizing the symmetry in the matrix. The lower triangular matrix portion is divided... Agent: Greer, Burns & Crain

20090313313 - Digital filter device, phase detection device, position detection device, ad conversion device, zero cross detection device, and digital filter program: A digital filter device capable of removing the effect of noise such as chattering from a zero crossing signal is provided. A digital filter device 4 filtering a binary digital signal DIN and outputting a binary digital signal DOUT is provided with a toggle flip-flop 12 which switches a signal... Agent: Dla Piper LLP Us

20090313314 - Techniques for performing discrete fourier transforms on radix-2 platforms: A technique for performing a discrete Fourier transform (DFT) includes storing, in a single-port memory, multiple signal points. A first group of consecutive ones of the multiple signal points are fetched (from a first line of the single-port memory) to a first input register associated with a processor that includes... Agent: Dillon & Yudell LLP

20090313315 - N-digit subtraction unit, n-digit subtraction module, n-digit addition unit and n-digit addition module: Provided are N-digit addition and subtraction units and N-digit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and modules, an output pattern of results of addition and subtraction is predicted based on a relation between an augend and... Agent: Foley & Lardner LLP

20090307293 - Method for determining an optimum sampling frequency, and a power analyzer performing the method: A method for determining an optimum sampling frequency to be performed by a power analyzer includes the following computer-implemented steps: sampling a time domain signal to obtain a sampling signal according to a predetermined sampling frequency; obtaining two reference sampling signals using higher and lower sampling frequencies compared to the... Agent: Lowe Hauptman Ham & Berner, LLP

20090307294 - Conversion between sub-band field representations for time-varying filter banks: Conversion between sub-band field representations for time-dependent filter banks. The invention relates to a transcoding processing operation between different sub-band fields, aiming to compact the application of a first vector representing the signal in a first sub-band field to a synthesis filter bank, and then to an analysis filter bank,... Agent: Mckenna Long & Aldridge LLP

20090300087 - Computation processor, information processor, and computing method: A computation processor outputs whether a carry-out is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes a computing unit that performs the computation; a shift amount calculating unit that calculates a shift amount of the result of... Agent: Staas & Halsey LLP

20090300088 - Sine/cosine generator: A method (30°) for generating a sine and cosine of an input angle (Ø102). The method involves decomposing Ø102 to an octant or quadrant, a coarse angle (A), and a fine angle (B), determining cos(A), and determining sin(A). The method also involves decomposing cos(A) and sin(A) to a most significant... Agent: Harris Corporation C/o Darby & Darby PC

20090300090 - Apparatus and method for determining resolver angle: The invention concerns a method and apparatus (28) for determining an angle (9) by means of a resolver (3). In the method, an excitation signal (29) of constant frequency is supplied to the resolver (3), the resolver response signals (13, 14) are measured, successive (16) measurements of each response signal... Agent: Birch Stewart Kolasch & Birch

20090300089 - Finite impulse response filter and method: An N-order finite impulse response (FIR) filter with a symmetric coefficient set is provided. An input device receives a serial of input signals according to a sampling frequency and stores the received data into the first and second memories by turns. A first calculating device reads the N successively received... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090300091 - Reducing bandwidth requirements for matrix multiplication: A block matrix multiplication mechanism is provided for reversing the visitation order of blocks at corner turns when performing a block matrix multiplication operation in a data processing system. The mechanism increases block size and divides each block into sub-blocks. By reversing the visitation order, the mechanism eliminates a sub-block... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.