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Electrical computers: arithmetic processing and calculating November recently filed with US Patent Office 11/09

20090292750 - Methods and apparatus for automatic accuracy- sustaining scaling of block-floating-point operands: A computer-implemented method performs an operation on a set of at least one BFP operands to generate a BFP result. The method is designed to reduce the risks of overflow and loss of accuracy attributable to the operation. The method performs an analysis to determine respective shift values for each... Agent: Stoel Rives LLP - Pdx

20090292752 - Mechanism for generating pseudorandom number sequences: In one embodiment, a mechanism for generating pseudo-random number sequences is disclosed. In one embodiment, a method includes receiving seed values for a pseudorandom number generator (PRNG) in a computing system, the seed values being polynomials. The method further includes running the PRNG using the seed values as initialization parameters,... Agent: Red Hat/bstz Blakely Sokoloff Taylor & Zafman LLP

20090292751 - Non-linear mixing of pseudo-random number generator output: A method and apparatus for a pseudo-random number generation system. The pseudo-random number generation mixes the output of two or more pseudo-random number generators to create a new pseudo-random number or sequence. The process operates on pseudo-random numbers with a bit size k, multiplies the numbers and then performs modulo... Agent: Red Hat/bstz Blakely Sokoloff Taylor & Zafman LLP

20090292753 - Fir filter apparatus, audio apparatus and fir filter program: A coefficient compensating unit 33 calculates based on a loop point and a cross-fade point of impulse response coefficient data renewed compensation impulse response coefficients specified for a cross-fade period defined between the cross-fade point and an end point of the impulse response coefficient data, and stores the calculated impulse... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090292754 - Method and system for avoiding underflow in a floating-point operation: Methods and systems for detecting underflow in a floating-point operation are disclosed. In accordance with an example disclosed method a plurality of comparator circuits and a plurality of logic devices coupled to the plurality of comparator circuits are operated to determine whether performing a floating-point operation using a floating-point hardware... Agent: Hanley, Flight & Zimmerman, LLC

20090292755 - Methods and apparatus for signature prediction and feature level fusion: A method for signature prediction and feature-level fusion of a target according to various aspects of the present invention includes generating a first manifold by developing a connected graph of data from a first sensing modality using a first k-orthogonal spanning tree, generating a second manifold by developing a second... Agent: Ingrassia Fisher & Lorenz, P.C. (raytheon)

20090292756 - Large-factor multiplication in an array of processors: A processor to calculate a product-component having fewer digits than an entire product of a multiplication of a multiplicand and a multiplier. A memory holds at least one multiplicand-component having fewer digits than the multiplicand and at least one multiplier-component having fewer digits than the multiplier. A logic then calculates... Agent: Henneman & Associates, PLC

20090292757 - Method and apparatus for zero prediction: A zero prediction method and apparatus for use in a reduced instruction set computer. The zero predictor 115 in use is connected by a controller 110 to an arithmetic unit 120. Different embodiments of the invention for use in addition include inverters 205 connected via incrementers 220 to comparators 235... Agent: Henneman & Associates, PLC

20090292758 - Optimized corner turns for local storage and bandwidth reduction: A block matrix multiplication mechanism is provided for reversing the visitation order of blocks at corner turns when performing a block matrix multiplication operation in a data processing system. By reversing the visitation order, the mechanism eliminates a block load at the corner turns. In accordance with the illustrative embodiment,... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090287753 - Parallel efficiency calculation method and apparatus: P

20090287754 - Systems and methods for step discontinuity removal in real-time pcr fluorescence data: Systems and methods for removing jump discontinuities in PCR or growth data. A first approximation to a curve that fits a received data set is determined by applying a non-linear regression process to a non-linear function that models the data set to determine parameters, including a step discontinuity parameter, of... Agent: Townsend And Townsend And Crew, LLP

20090287755 - Sequence similarity measuring apparatus and control method thereof: Disclosed is a sequence similarity measuring apparatus and a method of controlling the same. The sequence similarity measuring apparatus using dynamic programming includes: a matrix generating unit for generating a matrix based on the dynamic programming by using two sequences; a normalization unit for calculating a similarity reference value by... Agent: Renner Otto Boisselle & Sklar, LLP

20090287756 - Computing modular polynomials modulo large primes: Systems and methods for computing modular polynomials modulo large primes are described. In one aspect, the systems and methods generate l-isogenous elliptic curves. A modular polynomial modulo a large prime p is then computed as a function of l-isogenous elliptic curves modulo p.... Agent: Lee & Hayes, PLLC

20090287757 - Leading zero estimation modification for unfused rounding catastrophic cancellation: Modifying a leading zero estimation during an unfused multiply add operation of (A*B)+C. A plurality of terms x and y may be received, and each may be based on truncated terms s and t (e.g., in performing the unfused multiply add operation) and the shifted C term. A first leading... Agent: Mhkkg/sun