Electrical computers: arithmetic processing and calculating inventions 10/09

20090248767 - System and method for statistically separating and characterizing noise which is added to a signal of a machine or a system: Method for finding the probability density function type and the variance properties of the noise component N of a raw signal S of a machine or a system, said raw signal S being combined of a pure signal component P and said noise component N, the method comprising: (a) defining... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090248768 - Road shape estimating device, road shape estimating method and program: A road shape estimating device has a data obtaining processing unit for obtaining interpolation point data for shape interpolation points, a radius calculation processing unit for calculating a radius of curvature at each of the shape interpolation points based on the interpolation point data, a corner detection processing unit for... Agent: Bacon & Thomas, Pllc

20090248770 - Methods and apparatus for reducing or avoiding use of non-shift based divisions in a communications device: Methods and apparatus which reduce or completely eliminate non-shift based divisions as part of estimating transmitted symbols and/or generating slicing parameters corresponding to two symbol transmission streams in a wireless communication system are described. A linear least squares error estimation filtering module performs symbol estimations and/or slicing parameter generation while... Agent: Qualcomm Incorporated

20090248769 - Multiply and accumulate digital filter operations: A multiply and accumulate engine may implement a digital filter. In some embodiments, the number of coefficients that are stored may be equal to only half of the number of filter taps that are implemented. This may be done by doing multiplications operand by operand within two data registers in... Agent: Trop, Pruner & Hu, P.c.

20090248771 - True random number generator: True random number generation circuitry utilizes a pair of oscillators driving a pair of linear feedback shift registers, with their output being combined to generate random numbers. At least one of the oscillators is programmable with a variable frequency. One embodiment controls the variable frequency of oscillators with output from... Agent: Schwegman, Lundberg & Woessner / Atmel

20090248772 - Single-level parallel-gated carry/majority circuits and systems therefrom: A carry/majority circuit, comprising a plurality of differential transistor pairs coupled in parallel and forming a pair of output nodes, with a single parallel gated level. Current is steered through a leg of the transistor pair having a higher input voltage.... Agent: Bae Systems

20090248773 - Method and apparatus for signal transformation for positioning systems: A method and apparatus for signal transformation for positioning control in positioning systems is provided. The positioning involves performing a signal transformation by determining a transform and an inverse transform between a triangular reference signal and a model reference signal with less frequency content, for transforming the triangular reference signal... Agent: Ibm-acc-washington C/o Myers Dawes Andras & Sherman, LLP

20090248775 - Apparatus and method for area and speed efficient fast fourier transform (fft) processoring with runtime and static programmability of number of points: An apparatus and method for area and speed efficient fast Fourier transform (FFT) processing comprising mapping a one-dimensional DFT to a multi-dimensional representation; re-indexing the multi-dimensional representation as a radix 23 decimation architecture; simplifying the radix 23 decimation architecture to obtain a nested butterfly architecture; acquiring N samples of a... Agent: Qualcomm Incorporated

20090248774 - Reuse engine with task list for fast fourier transform and method of using the same: An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is... Agent: Qualcomm Incorporated

20090248776 - Advance trip count computation in a concurrent processing environment: A method for computing a trip count for a loop in advance of the execution of the loop is provided. The method comprises identifying the elements of a loop; returning infinity, if a first index value satisfies a first condition and that a first step size is equal to zero;... Agent: Century Ip Group, Inc. [intel]

20090248777 - Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root: Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root operations. Exemplary embodiments include a method including receiving a first microcoded instruction in the pipeline, decoding the first microcoded instruction in a decode stage of the pipeline, initiating a microcode engine coupled to... Agent: Cantor Colburn LLP - Ibm Rochester Division

20090248778 - Systems and methods for a combined matrix-vector and matrix transpose vector multiply for a block-sparse matrix: Systems and methods for combined matrix-vector and matrix-transpose vector multiply for block sparse matrices. Exemplary embodiments include a method of updating a simulation of physical objects in an interactive computer, including generating a set of representations of objects in the interactive computer environment, partitioning the set of representations into a... Agent: Cantor Colburn LLP-ibm Burlington

20090248779 - Processor which implements fused and unfused multiply-add instructions in a pipelined manner: Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the... Agent: Mhkkg/sun

20090248780 - Polynomial data processing operation: A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a polynomial division operation. The denominator polynomial is represented by a denominator value stored within a register with an assumption that the highest... Agent: Nixon & Vanderhye P.c.

20090248781 - Method and device for dynamically verifying a processor architecture: A method and device may be useful for dynamically verifying a processor architecture at runtime. The checker may more efficiently and cheaply verify at least some of the functionality provided by the execution unit of the processor architecture. The checker may verify operations such as addition, subtraction, multiplication, and division.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP