Electrical computers: arithmetic processing and calculating inventions 08/09

20090216819 - Stairway dimensions comparative calculator: An electronic spreadsheet or hand user calculator consists of an array of cells some containing formulas some into which a user enters stair dimension values such as total rise and run. After the user has entered such values the formulas proceed to other stair dimension calculations; then results are displayed... Agent: Eric Gobeil C/o Paul Biron

20090216820 - Fast computation of compact poset isomorphism certificates: Two methods and systems for fast construction of poset isomorphism certificates are provided. Posets (partially-ordered sets) generalize graphs. The invented certificates are number sequences such that two posets are isomorphic if and only if their corresponding certificates coincide. The first method yields the (Omicron,Iota) poset isomorphism certificate. The minimal Phi-isomorphism... Agent: Oppenheimer Wolff & Donnelly LLP

20090216821 - Singular value decomposition apparatus and singular value decomposition method: The present invention provides a singular value decomposition apparatus that can perform processing in parallel at high speed and high accuracy. The singular value decomposition apparatus comprises a matrix dividing portion 14 that repeatedly divides a bidiagonal matrix B into two bidiagonal matrices, a singular value decomposition portion 15 that... Agent: Rader Fishman & Grauer Pllc

20090216822 - Method, system and computer program product for verifying floating point square root operation results: A method, system and computer program product for verifying a result of a floating point square root operation is provided. The method includes: receiving a result of a floating point square root operation for an operand; performing a comparison of a magnitude of a least significant bit (LSB) of the... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216824 - Method, system and computer program product for determining required precision in fixed-point divide operations: A method, computer program product and a system for controlling a fixed point division operation are provided. The method includes: receiving an instruction to perform a division operation for a dividend and a divisor, the operation comprising a maximum number of iterations to produce a quotient having a maximum precision;... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216823 - Method, system and computer program product for verifying floating point divide operation results: A method, system and computer program product for verifying a result of a floating point division operation are provided. The method includes: receiving a result of a floating point division operation for a dividend and a divisor; performing a comparison of a magnitude of a least significant bit (LSB) of... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216825 - Method, system and computer program product for detecting errors in fixed point division operation results: A method, computer program product and a system for detecting errors in a result of a fixed-point division operation are provided. The method includes: receiving a result of a fixed-point division operation for a dividend and a divisor; performing a first comparison of the divisor and a remainder of the... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090216826 - Generalized programmable counter arrays: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry... Agent: Seyfarth Shaw LLP

20090210466 - Electronic calculator with a formula display function: When the intake input mode is set and a 2D function key, such as “√{square root over ( )}” or “a/b,” is operated in a state where the cursor has been moved to an arbitrary position on the formula displayed on the display unit of an electronic calculator, the range... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090210467 - Ascii to binary floating point conversion of decimal real numbers on a vector processor: The present invention provides a system, method, and apparatus for converting a decimal real number in ASCII format to a decimal real number in floating point binary decimal format in a vector processor.... Agent: Prtsi, Inc

20090210468 - Generation of thermal agitation noise according to a predetermined histogram: e

20090210469 - Methods and devices for filtering and coding a digital signal:

20090210470 - Apparatus and methods for lossless compression of numerical attributes in rule based systems: Disclosed are apparatus and methods for compressing a set of numerical values for a set of feature values, which can be utilized by a rule based or decision tree system. In certain embodiments, the numerical values are transformed into a subset of integer values based on how they are to... Agent: Weaver Austin Villeneuve & Sampson - Yahoo!

20090210471 - Method for transforming data stream and communication system thereof: A method for transforming a data stream and a communication system thereof are provided. In a second communication terminal, a padding data of the data stream of a first communication terminal is checked whether it corresponds to a default value so as to determine whether a first bit order used... Agent: J C Patents, Inc.

20090210472 - Method, system and computer program product for identifying decimal floating point addition operations that do not require alignment, normalization or rounding: A method, computer program product and a system for identifying decimal floating point addition operations that guarantee operand alignment and do not require alignment, normalization or rounding are provided. The method includes: receiving an instruction to perform an addition of a first operand and a second operand; extracting a first... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204655 - System and method for determining a grouping of segments within a market: A method for determining a grouping of segments within a market. The method includes forming a bias mitigated square matrix from a square matrix populated with second choice data, and forming a compressed matrix from the bias mitigated square matrix. Each different segment is initially associated with a row of... Agent: Pepper Hamilton LLP

20090204656 - Pseudo random number generator and method for generating a pseudo random number bit sequence: A pseudo random number generator including a plurality of non-singular feedback shift registers each configured to output a bit-sequence. At least a first of the plurality of non-singular feedback shift registers has one or more first cycles of a length less than or equal to two, and a second of... Agent: Dickstein Shapiro LLP

20090204657 - Hybrid random number generator: A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently... Agent: Dickstein Shapiro LLP

20090204658 - Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium: A decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in a calculation instruction, includes a multidigit memory section which stores values with greater numbers of digits than the number of digits of a predetermined digit unit in a plurality of memory areas, a... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090204659 - N-bit adder and corresponding addition method: An adder is provided for adding input signals including first and second binary input numbers, with N bits each. The adder includes a determination circuit capable of determining the bits of the sum of the input signals. The determination circuit includes an estimating circuit including estimating blocks connected in series,... Agent: Westman Champlin & Kelly, P.A.

20090204655 - System and method for determining a grouping of segments within a market: A method for determining a grouping of segments within a market. The method includes forming a bias mitigated square matrix from a square matrix populated with second choice data, and forming a compressed matrix from the bias mitigated square matrix. Each different segment is initially associated with a row of... Agent: Pepper Hamilton LLP

20090204656 - Pseudo random number generator and method for generating a pseudo random number bit sequence: A pseudo random number generator including a plurality of non-singular feedback shift registers each configured to output a bit-sequence. At least a first of the plurality of non-singular feedback shift registers has one or more first cycles of a length less than or equal to two, and a second of... Agent: Dickstein Shapiro LLP

20090204657 - Hybrid random number generator: A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently... Agent: Dickstein Shapiro LLP

20090204658 - Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium: A decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in a calculation instruction, includes a multidigit memory section which stores values with greater numbers of digits than the number of digits of a predetermined digit unit in a plurality of memory areas, a... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090204659 - N-bit adder and corresponding addition method: An adder is provided for adding input signals including first and second binary input numbers, with N bits each. The adder includes a determination circuit capable of determining the bits of the sum of the input signals. The determination circuit includes an estimating circuit including estimating blocks connected in series,... Agent: Westman Champlin & Kelly, P.A.

20090198750 - Sound control calculator device: A sound control calculator device is described. The sound control calculator device has a long case. The case at least has a sound hole, a key hole, and a window disposed at the periphery thereof and a circuit board disposed therein. The circuit board at least includes a microphone, a... Agent: Rabin & Berdo, PC

20090198751 - Method and apparatus for controlling functionalities of computer system: A method and an apparatus for controlling functionalities of a computer system are provided. The apparatus comprises a key, a serial input unit, and a processing unit. The key is used for enabling an adjustment function of a computer system. The serial input unit is used for generating an adjustment... Agent: Jianq Chyun Intellectual Property Office

20090198752 - Ascii to binary decimal integer conversion in a vector processor: A system, method, and apparatus for the constant time, branchless conversion of decimal integers of varying size in ASCII format to a decimal integer in binary decimal format in a vector processor.... Agent: Prtsi, Inc

20090198753 - Data processing method by passage between different sub-band domains: The invention concerns data processing by passage between different subband domains, of a first number L to a second number M of subband components. After determining a third number K, least common multiple between the first number L and the second number M: a) if K is different from L,... Agent: Mckenna Long & Aldridge LLP

20090198754 - Order adaptive finite impulse response filter and operating method thereof: A device for allocating a number of taps of a designated finite impulse response filter is disclosed. The device comprises a plurality of designated finite impulse response filters having fixed number of taps, a plurality of allocation finite impulse response filters having fixed number of taps, a control unit and... Agent: Tung & Associates / Randy W. Tung, Esq.

20090198755 - Scaled signal processing elements for reduced filter tap noise: An adaptive transversal filter having tap weights Wj which are products of corresponding tap coefficients Cj and tap gains Mj is provided. A filter control loop controls all of the tap coefficients Cj such that an error signal derived from the filter output is minimized. One or more tap control... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090198756 - Representation of data transformation processes for parallelization: One or more operations are defined to be used against a repository of one or more items. One or more associations between each of the one or more items are also defined. A classification is associated with the one or more operations for an execution environment within a transformation graph,... Agent: Fish & Richardson, P.C.

20090198757 - Method and device for avoiding rounding errors after performing an inverse discrete cosine transformation: The present invention provides a method for avoiding rounding errors during rounding of values after performing an inverse discrete cosine transformation. In a first step a) coefficient values of a plurality of coefficients are summed up, wherein the coefficients belong to a block of coefficients. In a second step b),... Agent: John D. Titus The Cavanagh Law Firm

20090198758 - Method for sign-extension in a multi-precision multiplier: A method for implementing sign extension within a multi-precision multiplier is described. The method includes receiving a first input within a multiplier core of the multiplier, receiving a second input within the multiplier core, and creating partial products in the multiplier core using the first and second inputs. The method... Agent: Cantor Colburn LLP-ibm Yorktown

20090198759 - Circuits for computational set theory: m