Electrical computers: arithmetic processing and calculating inventions 07/09

20090193065 - Deterministic random number generator for cryptography and digital watermarking: P

20090193066 - Communication apparatus, method of checking received data size, multiple determining circuit, and multiple determination method: A dividing unit sets an actual packet length transferred from a packet receiving section to a variable U, and then sets 2α to a variable V. If a positive number determining section determines that a subtraction result of subtracting a remainder N0 from a quotient M0, both found by dividing... Agent: Fujitsu Patent Center C/o Cpa Global

20090193067 - Server-based recalculation of vector graphics: Technologies are described herein for recalculating data-bound vector graphics on a server computer. A drawing program allows formulas to define how external data is utilized modify the attributes of a shape. When a request is received to publish a drawing to a server computer, any formulas are converted to server-optimized... Agent: Microsoft Corporation

20090187615 - Digital filter: Provided is a digital filter for radio communication processing capable of dynamically modifying the characteristic and simultaneously processing a plurality of systems. In the digital filter, calculation core groups (1010-1017) capable of modifying function are arranged and connected to one another by an input interface unit (102) and an output... Agent: Dickinson Wright PLLC James E. Ledbetter, Esq.

20090187616 - Method for representing complex numbers in a communication system: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the... Agent: Lee & Hayes, PLLC

20090187617 - Carry look-ahead circuit and carry look-ahead method: A carry look-ahead circuit generates a generate output for generating a carry, from a plurality of inverted generate inputs and a plurality of inverted propagate inputs to peer bits of a first operand and a second operand including a plurality of bits. The carry look-ahead circuit includes a circuit that... Agent: Staas & Halsey LLP

20090182795 - Method and system for performing calculations using fixed point microprocessor hardware: A method and system are described for performing an arithmetic operation such as multiplication or division of a fixed point variable measured at runtime by a floating point constant known at compile-time. The floating point constant is converted into a mantissa and a base-2 exponent at compile-time. The mantissa and... Agent: Marlin Knight

20090182796 - Sample generation method and system for digital simulation processes: A method for generating a set of random numbers with statistics represented by a cumulative density function includes generating a set of uniformly spaced samples between an upper limit and a lower limit. Each of the uniformly spaced samples are then mapped to a corresponding value on a cumulative density... Agent: The Directv Group, Inc. Patent Docket Administration

20090182797 - Consistent contingency table release: Techniques for contingency table release provide an accurate and consistent set of tables while guaranteeing that privacy is preserved. A positive and integral database is constructed that corresponds to these tables. Therefore, a database can be generated that preserves low-order marginals up to a small error. Moreover, a gracefully degrading... Agent: Microsoft Corporation

20090177722 - Arithmetic processing apparatus: In a graphing scientific electronic calculator 10, when a graphing mode is selected from an application list 12a, a function expression entering screen is displayed on a display unit 16. When an function expression is entered and EXE key 15e is operated, an appropriate graph is drawn in accordance with... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090177723 - Method and apparatus for approximating an upper-bound limit for an absolute value of a complex number or norm of a two-element vector: A method for approximating an upper bound limit for the absolute value of a complex number or the norm of a two-element vector is disclosed. An upper bound approximation algorithm is used to minimize software implementation efforts and make the hardware implementation less expensive. The hardware implementation of the upper... Agent: Baker & Mckenzie LLP Patent Department

20090177724 - Processor and method of determining a normalization count: In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the... Agent: Qualcomm Incorporated

20090177725 - Random number generation device: It is made possible to provide a random number generation device which generates a physical random number with as little power dissipation as possible. A random number generation device includes: a ring oscillator having at least one set, each set comprising a current noise source and a Schmitt inverter configured... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090177726 - Method for processing a digital input signal in a digital domain and digital filter circuit for processing a digital input signal: The invention relates to a method for processing a digital input signal (x(i)) in a digital domain, comprising: -sampling a wideband of input frequencies of said digital input signal (x(i)) with a sampling frequency (fs), which decimates with a decimation factor (D), -linear shaping said sampled input frequencies with a... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090172052 - Tiled architecture for stationary-method iterative linear solvers: A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the... Agent: Hovey Williams LLP

20090172053 - Arithmetic apparatus for multi-function unit and method: An arithmetic apparatus for a multi-function unit and a method integrates all operations which are necessary to the GPU (graphics processing unit) with one operational device to decrease the area and power of the hardware and to control all operations except a matrix-vector multiplication to achieve a single-cycle throughput and... Agent: Pryor Cashman, LLP

20090172054 - Efficient leading zero anticipator: Embodiments of the present invention provide a system that estimates the location of the leading zero or the leading one in the result of an addition of floating-point numbers A and B. The system includes a half-adder circuit associated with each separate bit position i in A and B. The... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090172055 - Random number generator: The invention concerns a random number generator comprising a n-bit LSFR at least one oscillator having at least one delay element introducing a variable delay in the counter feedback loop, and at least one sampling/holding device having at least one input coupled to an output of the oscillator, and at... Agent: Miller, Matthias & Hull

20090172056 - Random number generator: Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, said integrated circuit including a true random number generator having an analog... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Cpa Global

20090172057 - Computer system for predicting the evolution of a chronological set of numerical values: The invention relates to a computer system for assisting prediction of the future of a chronological set (J) of numerical values which are stored in the memory (H) of a computer (O), such as to enable the generation of a topological structure, which can be displayed (V), using an algorithm-based... Agent: Christie, Parker & Hale, LLP

20090172059 - Computing time-decayed aggregates in data streams: Aggregates are calculated from a data stream in which data is sent in a sequence of tuples, in which each tuple comprises an item identifier and a timestamp indicating when the tuple was transmitted. The tuples may arrive out-of-order, that is, the sequence in which the tuples arrive are not... Agent: At & T Legal Department - Ws Attn: Patent Docketing

20090172058 - Computing time-decayed aggregates under smooth decay functions: Aggregates are calculated from a data stream in which data is sent in a sequence of tuples, in which each tuple comprises an item identifier and a timestamp indicating when the tuple was transmitted. The tuples may arrive at a data receiver out-of-order, that is, the sequence in which the... Agent: At & T Legal Department - Ws Attn: Patent Docketing

20090172060 - Filter adaptive frequency resolution: In signal processing using digital filtering the representation of a filter is adapted depending on the filter characteristics. If e.g. a digital filter is represented by filter coefficients for transform bands Nos. 0, 1, . . . , K in the frequency domain, a reduced digital filter having coefficients for... Agent: Ericsson Inc.

20090172061 - Inverse hadamard transform converter and system: The present invention provides an Inverse Hadamard Transform (IHT) converter which comprises a first group of registers for receiving coefficients inputted to the IHT converter; a first adder for adding selected the coefficients stored in the first group of registers; a second group of registers for receiving results from the... Agent: Patterson & Sheridan, L.L.P.

20090172062 - Efficient fixed-point implementation of an fft: A fast Fourier transform (FFT) is performed on first-fourth input data points. Real and imaginary portions of the first input data point are stored in first and second registers. Real and imaginary portions of the second input data point are stored in third and fourth registers. Real and imaginary portions... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090172063 - Multi-threaded codeless user-defined functions: A multi-threaded codeless user-defined function (UDF) may be provided. First, at least one input value may be received from a calculation thread corresponding to a spreadsheet calling the codeless UDF. Then, the at least one input value may be saved in a thread storage area outside of a UDF storage... Agent: Merchant & Gould (microsoft)

20090172064 - Method for enhancing the computation of css and accuracy of computing hardware and to promote the computation speed: This invention proposed a new algorithm. By multiply the proposed weight coefficients of this invention, CSP and CSS can be computed without computing for the mean(s) of the data. After the proposed weight coefficients of this invention undergo factorization, it can promote a new recursive and real time updatable computation... Agent: Juei-chao Chen Tien-lung, Sun, Kuo-hung, Lo

20090172066 - Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away: Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating point numbers of precision P1 in base b, producing positive result... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Cpa Global

20090172065 - Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest even: Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest even are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating point numbers of precision P1 in base b, producing positive result... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Cpa Global

20090172067 - Methods and apparatus for implementing a saturating multiplier: Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating. The result of the multiplier can be stored in a result register in unsaturated form. The output of the result register can then be... Agent: Weaver Austin Villeneuve & Sampson LLP - Altera Attn: Altera

20090172068 - Method and apparatus for efficiently implementing the advanced encryption standard: Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are... Agent: Larry Mennemeier Intel Corporation

20090172069 - Method and apparatus for integer division: The invention provides a method, arithmetic divider unit, and system for dividing a dividend DZm . . . Z0 having a most significant bit and a plurality of less significant bits by a divisor having a most significant bit ZN and a plurality of less significant bits ZN−1 through Z0.... Agent: Ryan, Mason & Lewis, LLP

20090172070 - Single clock cycle first order limited accumulator for supplying weighted corrections: A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper... Agent: Law Office Of Gerald Maliszewski

20090172071 - Method and system for data decomposition via graphical multivariate analysis: A method for multivariate analysis using a mathematical model for generating model data and actual data for more than one variable includes for each variable, determining a difference between the model data and the actual data. The model data is substantially representative of more than one variable. The method also... Agent: John S. Beulick (12729) C/o Armstrong Teasdale LLP