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Electrical computers: arithmetic processing and calculating June invention type 06/09

20090164540 - Apparatus and method for updating check node of low density parity check code: Provided is an apparatus and method for updating a check node of a LDPC code at a high speed. The apparatus includes: a minimum value calculating unit for calculating a first minimum value of an input bit by sequentially calculating each bit of the first minimum value, and calculating a... Agent: Cantor Colburn, LLP

20090164541 - Procedure for deriving a three-dimensional digital mask starting from a series of two-dimensional masks, plus a device for doing this: A derivation procedure for a three-dimensional digital mask from a series of two-dimensional masks in a radiographic device containing a source (S) of X-rays, a means of recording and a volume of interest hat contains the object to be X-rayed located between the source (S) and the means of recording... Agent: General Electric Company Ge Global Patent Operation

20090164542 - Method for calculating coefficients of filter and method for filtering: A method for calculating coefficients of a filter and a method for filtering are provided. The invention directly factorizes a specific function in a cepstrum domain by spectral factorization and cepstrum technique to obtain coefficients of denominator function from the filter. In other words, the invention adopts a non-iterative algorithm... Agent: Jianq Chyun Intellectual Property Office

20090164543 - Apparatus and method to compute reciprocal approximations: A method and apparatus for reducing memory required to store reciprocal approximations as specified in Institute of Electrical and Electronic Engineers (IEEE) standards such as IEEE 754 is presented. Monotonic properties of the reciprocal function are used to bound groups of values. Efficient bit-vectors are used to represent information in... Agent: Caroline F. Fleming Intel Corporation

20090164544 - Dynamic range enhancement for arithmetic calculations in real-time control systems using fixed point hardware: A digital processing system and method are described that encodes a fixed point number into a mantissa by removing redundant sign bits by shifting the significant bits to the left. The number of bits shifted is recorded as the exponent. In one embodiment the mantissa and exponent are combined into... Agent: Marlin Knight

20090164545 - Electronic circuitry and method for determination of amplitudes of received signals: A method and a calculating circuit for generating an output signal representing an actual amplitude of a received digitized signal having a magnitude of the actual amplitude equal or greater than a value of a saturation level of a dynamic range of a receiver. For the determination of the actual... Agent: Houston Eliseeva

20090164546 - Method and apparatus for efficient programmable cyclic redundancy check (crc): A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic.... Agent: Intel Corporation C/o Cpa Global

20090157778 - Computer systems using quantum allegories as oracles: A computer system includes a deterministic computer that provides a non-recursive functional to a quantum system encoder. The quantum system encoder encodes the non-recursive functional into a first quantum system. The first quantum state is transformed to a second quantum state by an operator that includes a Topological Order Processing... Agent: Koestner Bertani LLP

20090157781 - Method and apparatus for generating content identifier and preventing alteration of the content identifier: A method and apparatus for generating a content identifier and preventing alteration of the content identifier are provided. The method includes generating at least one random number, generating location information for designating a plurality of locations within a content by using the at least one generated random number, extracting a... Agent: Sughrue Mion, PLLC

20090157779 - Method system and device for generation of a pseudo-random data sequence: A method and a generator for generating a pseudo-random data sequence (3), including combining means for combining data belonging to a plurality of initial data sequences (9a, 9b, 9c) using a procedure for searching for at least one search pattern.... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090157780 - Random number generating circuit, semiconductor integrated circuit, ic card and information terminal device: A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090157782 - Random number generator and random number generating method thereof: A random number generator and a random number generating method thereof are provided. The random number generator includes a signal generating unit and a sampling unit. The signal generating unit is adapted for memorizing a status of a noise generated during a transient of an output signal of an output... Agent: J C Patents, Inc.

20090157783 - Numerically-controlled oscillator capable of generating cosine signal and sine signal only using cosine look up table and operating method of the numerically-controlled oscillator: A numerically-controlled oscillator (NCO) and an operating method of the NCO are provided. According to the NCO and the operating method of the NCO, it is possible to reduce the size of a lookup table memory by using a lookup table, which stores a plurality of phase compensation values for... Agent: Cantor Colburn, LLP

20090157784 - Determining a message residue: A description of techniques of determining a modular remainder with respect to a polynomial of a message comprised of a series of segments. An implementation can include repeatedly accessing a strict subset of the segments and transforming the strict subset of segments to into a smaller set of segments that... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090157785 - Fast algorithms for computation of 5-point dct-ii, dct-iv, and dst-iv, and architectures: A more efficient encoder/decoder is provided in which an N-point MDCT transform is mapped into smaller sized N/2-point DCT-IV, DST-IV and/or DCT-II transforms. The MDCT may be systematically decimated by factor of 2 by utilizing a uniformly scaled 5-point DCT-II core function as opposed to the DCT-IV or FFT cores... Agent: Qualcomm Incorporated

20090157786 - Method and apparatus for a fail safe fourier transform matrix: A base station transmitter for maintaining data rate transmission between a set of Fourier Transform matrices, having a digital Fourier Transform Matrix (FTM), and analog FTM, and a plurality of transmit paths therebetween. During the occurrence of a power amplifier failure, the method includes detecting the failure of a power... Agent: Motorola, Inc.

20090157787 - Row-vector norm comparison method and row-vector norm comparison apparatus for inverse matrix: Disclosed are a row-vector norm comparison method and a row-vector norm comparison apparatus for an inverse matrix. A row-vector norm comparison apparatus includes: an input matrix processing module that receives and combines constituent elements of a matrix; a cofactor operation module that multiplexes the combination result of the constituent elements... Agent: JeffersonIPLaw, LLP

20090157788 - Modular squaring in binary field arithmetic: After squaring an element of a binary field, the squaring result may be reduced modulo the field-defining polynomial g bits at a time. To this end, a lookup table may be employed, where the lookup table stores entries corresponding to reducing g-bit-long polynomials modulo the field-defining polynomial. Such a reducing... Agent: Ridout & Maybee LLP

20090157790 - Method and apparatus for multiplying polynomials with a prime number of terms: An efficient method and apparatus to compute a product of polynomials of degree n−1 where n is an arbitrary prime is provided. The total number of multiply operations and Arithmetic Logical Unit (ALU) operations to compute the product is minimized through the judicious use of polynomial evaluations at few points... Agent: Caroline F. Fleming Intel Corporation

20090157789 - Multiplicative group counter: Systems and methods are provided for efficiently counting detected events via a multiplicative group counter. An equivalent class polynomial congruent with a first of a plurality of elements comprising a multiplicative group is represented as a series of binary values. The represented polynomial is subjected to a state transition function... Agent: Tarolli, Sundheim, Covell & Tummino L.L.P.

20090157791 - Flexible accumulator for rational division: A system and method are provided for rational division. The method accepts accepting a binary numerator and a binary denominator. A binary first sum is created of the numerator and a binary first count from a previous cycle. A binary first difference is created between the first sum and the... Agent: Gerald W. Maliszewski

20090150466 - Rate multiplication method: The present invention discloses a rate multiplication method for counting a sequence of original pulse signals and outputting a target pulse signal. In this method a comparison data and original pulse signal sequence is received. The original pulse signal sequence is counted in order to obtain a pulse count. Comparing... Agent: J C Patents, Inc.

20090150467 - Method of generating pseudo-random numbers: A method of generating a pseudo-random number by means of an iteration, comprising at least two iteration steps, applied to a one-way function, wherein the one-way function, based on a start value and a key, generates part of the pseudo-random number and wherein the iteration is initialized with a random... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090150468 - Digital filter: A FIR filter (20) has a delay line comprising four delay elements (21a, 21b, 21c, 21d) for delaying a signal received at a filter input (22) and four multipliers (24a, 24b, 24c, 24d) for multiplying the delayed signals by respective partial filter coefficients a, b, c, d. The delay elements... Agent: Seed Intellectual Property Law Group PLLC

20090150469 - Unified inverse discrete cosine transform (idct) microcode processor engine: The present invention provides a unified inverse discrete cosine transform (IDCT) microcode processor engine, which is able to process IDCT with different video standards and also achieves the processing speed requirement. The microcode processor engine comprises a read unit for reading input data; a shift left unit comprising: a first... Agent: Patterson & Sheridan, L.L.P.

20090150470 - Fast fourier transformation circuit: Provided is a fast Fourier transformation circuit capable of optimizing an operation resource while matching a plurality of communication systems. In this circuit, an FFT circuit (100) comprises a first FFT operation unit (110) for subjecting two-parallel 2<M−1> digital signals to FFT operations of (M−1) steps, a second FFT operation... Agent: Dickinson Wright PLLC James E. Ledbetter, Esq.

20090150471 - Reconfigurable arithmetic unit and high-efficiency processor having the same: Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for... Agent: Ladas & Parry LLP

20090144350 - Maximum simplex volume criterion-based endmember extraction algorithms: Provided herein are algorithms and processes to extract endmembers from hyperspectral image data in real time. A Simplex Growing Algorithm is effective to estimate a p number of endmembers to be generated, to select one or more initial endmembers as a simplex of k members and to add a k+1... Agent: Benjamin Aaron Adler Adler & Associates

20090144351 - Control of a pseudo random number generator and a consumer circuit coupled thereto: A system comprising a pseudo random number generator, a control circuit being configured to increase a quality of a pseudo random number output signal of the pseudo random number generator by coupling the pseudo random number generator with a true random number output signal of a true random number generator... Agent: Dickstein Shapiro LLP

20090144352 - Automatic maintenance of a computing system in a steady state using correlation: An autonomic computing system is automatically maintained in a steady state. The system has a number of parameters, each of which has one or more threshold. The system may further have a number of influencers, adjustment of which affects values of the parameters. One or more of the parameters are... Agent: Law Offices Of Michael Dryja

20090144353 - Method and apparatus for efficient modulo multiplication: A method of a hardware based Montgomery reduction contemplates preparing a table comprising a plurality of sets of values of 2K+i (mod n), 2K+i+1 (mod n) and (2K+i+2K+i+1)(mod n), where i=to M−2, n is a modulo number, K is an integer, and M is a number of significant bits in... Agent: Docket Clerk

20090144354 - Imaging device: An imaging device that improves properties for multiplying signal charges. The imaging device includes an accumulation section which accumulates signal charges. A transfer section transfers the signal charges accumulated in the accumulation section. A multiplier section increases the signal charges accumulated in the accumulation section. The transfer section includes a... Agent: Ditthavong Mori & Steiner, P.C.