Electrical computers: arithmetic processing and calculating inventions 05/09

20090138534 - Microprocessor shifter circuits utilizing butterfly and inverse butterfly routing circuits, and control circuits therefor: Microprocessor shifter circuits utilizing butterfly and inverse butterfly circuits, and control circuits therefor, are provided. The same shifter circuits can also perform complex bit manipulations at high speeds, including butterfly and inverse butterfly operations, parallel extract and deposit operations, group operations, mix operations, permutation operations, as well as instructions executed... Agent: Mccarter & English, LLP Newark

20090138535 - Novel binary and n-state linear feedback shift registers (lfsrs): N-state with n equal or greater than 2 modified Linear Feedback Shift Registers (mLFSRs) having a non-reversible n-state switching function have been disclosed. An mLFSR can also contain a device that implements an n-state logic function of which one input is provided with a signal external to the mLFSR. The... Agent: Diehl Servilla LLC

20090138536 - Precision-sensing linear interpolation algorithm: The present invention discloses a precision-sensing linear interpolation algorithm, which is distinct from the conventional technology in that precision detection is performed before iterative division calculations. The iteration number of iterative division calculations is determined according to the required precision. After the iterative division calculations, the bits in the decimal... Agent: Joe Mckinney Muncy

20090138537 - Address generating circuit and semiconductor memory device: An address generating circuit includes a first carry look-ahead circuit for performing an operation using an inputted first carry and a first address and outputting a first output address and a first output carry respectively as a first operation result, a second carry look-ahead circuit for performing an operation using... Agent: Mcginn Intellectual Property Law Group, PLLC

20090132624 - Integrated circuit with a true random number generator: An integrated circuit (1 . . . 1′″, 1a . . . I c) with a true random number generator (2 . . . 2′″), which true random number generator (2 . . . 2″) comprises at least one instable physically uncloneable function (3 . . . 3′″, 3a, 3a′)... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090132625 - Method for combining binary numbers in environments having limited bit widths and apparatus therefor: The present disclosure provides a method and system for combining multiple coefficient words using only the magnitude bits of each of the coefficient words and using the sign bits of each of the coefficient words to modify the output of the combined magnitude bits. Using this method and/or system, it... Agent: Duane Morris LLP (harris Corp.)IPDepartment

20090132626 - Method and system for detecting difference between plural observed results: A method and system for analyzing time series data. In an embodiment, a loop is executed and terminated upon a specified maximum number of iterations of the loop being performed or upon a difference between scores in successive iterations of the loop not being greater than a specified tolerance, wherein... Agent: Ibm - End Shimokaji & Associates, P.C.

20090132627 - Method for performing decimal floating point addition: A method for performing a decimal floating point operation including receiving a first operand having a first coefficient and a first exponent into a first register. A second operand having a second coefficient and a second exponent are received into a second register. An operation, either addition or subtraction, associated... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090132628 - Method for performing decimal division: A method for performing decimal division including receiving a scaled divisor and a scaled dividend into input registers. A subset of multiples of the scaled divisor is stored in a plurality of multiples registers. Quotient digits are calculated in response to the scaled divisor and the scaled dividend. Each quotient... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090132629 - Method for providing a decimal multiply algorithm using a double adder: A method for performing decimal multiplication including storing a multiplier and a multiplicand in operand registers, the multiplier including one or more digits. A running sum is stored in a shifter and initialized to zero. The method includes performing for each of the digits in the multiplier in order from... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090132630 - Method and apparatus for multiplying binary operands: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from... Agent: Texas Instruments Incorporated

20090132631 - Method of forcing 1's and inverting sum in an adder without incurring timing delay: A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation.... Agent: Ibm Corporation (jvm)

20090125575 - Noise canceling device, weighing device, method of canceling a noise, and method of designing a digital filter: It is an object of the present invention to provide techniques which allow for easier change in filter characteristics of a digital filter. Then, in order to attain this object, in a weighing device according to the present invention, a filter coefficient calculator (6) calculates a filter coefficient using a... Agent: Staas & Halsey LLP

20090125576 - Pade approximation convert circuit of direct digital frequency synthesizer: This invention relates to Pade approximation convert circuit of the direct digital frequency synthesizer in which a multiplier receives and multiplies a first input signal and a variable signal so as to produce a multiplication signal; a divider receives and divides a second input signal and a variable signal so... Agent: Rosenberg, Klein & Lee

20090119355 - Arithmetic logical unit, computation method and computer system: This arithmetic logical unit outputs data to be used in checking the final result of an AES unit that encrypts a plain text block into an encrypted text block based on AES operation, and includes an arithmetic unit for computing parity data created based on XOR operation from an encryption... Agent: Sughrue Mion, PLLC

20090119356 - Method for reducing digital filter coefficient word size and apparatus therefor: Electronic component resource utilization for certain digital filters may be significantly reduced by using a method for determining a set of coefficient words using a smaller word size. The disclosed method and/or apparatus may be used to determine an initial set of coefficient words for a digital filter for a... Agent: Duane Morris LLP (harris Corp.)IPDepartment

20090119357 - Advanced correlation and process window evaluation application: A method only has the user input (or select) a data type, a report key, a dependent variable table, and/or filtering restrictions. Using this information, the method automatically locates independent variable data based on the data type and the report key. This independent variable data can be in the form... Agent: International Business Machines Corporation Dept. 18g

20090119358 - Computational method, system, and apparatus: An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational... Agent: Fortkort & Houston P.C.