|Electrical computers: arithmetic processing and calculating patents - Monitor Patents|
USPTO Class 708 | Browse by Industry: Previous - Next | All
04/2009 | Recent | 13: May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers: arithmetic processing and calculating April category listing, related patent applications 04/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 04/30/2009 > patent applications in patent subcategories. category listing, related patent applications
20090112954 - A robust spectral analyzer for one-dimensional and multi-dimensional data analysis: A method of analyzing a spectrum of one-dimensional or multi-dimensional signal X(t) requires a number of steps including deriving coefficients [AN(ω), BN(ω)] of an Lp-norm harmonic regression of tie signal with 0<p≦∞ and pγ2, squaring the coefficients, summing the squared coefficients, and scaling the summed, squared coefficients with a constant... Agent: Scully, Scott, Murphy & Presser, P.C.
20090112955 - Apparatus and method for performing magnitude detection of arthimetic operations: An apparatus and method is provided comprising processing circuitry, one or more registers and control circuitry. The control circuitry is configured such that it is responsive to a combined magnitude-detecting arithmetic instruction to control the processing circuitry to perform an arithmetic operation on at least one data element and further... Agent: Nixon & Vanderhye P.C.
20090112956 - Fast batch verification method and apparatus there-of: A fast batch verification method and apparatus are provided. In the method of batch-verifying a plurality of exponentiations, (a) a predetermined bit value t is set to an integer equal to or greater than 1; (b) a maximum Hamming weight k is set to an integer equal to or greater... Agent: Cantor Colburn, LLP
20090112957 - System and methods for data sample decimation and display of scanning probe microscope images: Methods, systems and components for producing a scanning probe microscope (SPM) image. One method embodiment includes receiving sample data from a scanning probe microscope wherein said sample data comprises data sample many times per pixel of the SPM image to be displayed; selecting at least one decimation scheme from a... Agent: Agilent Technologies Inc.
20090112958 - Processes and apparatus for deriving order-16 integer transforms: Apparatus, systems and techniques based on an integer transform for encoding and decoding video or image signals, including apparatus, systems and techniques for deriving an order-16 integer transform from an order-8 integer transform in image and video coding. In some implementations, eight additions and eight subtractions are used to assign... Agent: Fish & Richardson, PC
20090112959 - Single-cycle fft butterfly calculator: In accordance with exemplary embodiments, a Fast Fourier Transform (FFT) architecture includes elements that perform a radix-2 FFT butterfly in one processor clock cycle at steady state. Some exemplary implementations of the FFT architecture incorporate register and data path elements that relieve memory bandwidth limitations by pairing operands consumed by... Agent: Ip Legal Services LLC
20090112960 - System and method for providing a double adder for decimal floating point operations: A method for implementing an adder including receiving a first and second operand. A sum of one or more corresponding digits from the first operand and the second operand is calculated. The calculating is performed by a plurality of adder blocks. Output from the calculating includes the sum of the... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090112961 - Error-correcting method used in data transmission and decoding: An error-correcting method used in decoding data transmission is disclosed. The error-correcting method is used for analyzing an error receiving data received from a receiving terminal and comprises: providing a first calculating formula for manipulation of the receiving data to generate the first sum; providing a second calculating formula for... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20090112962 - Modular squaring in binary field arithmetic: After squaring an element of a binary field, the squaring result may be reduced modulo the field-defining polynomial g bits at a time. To this end, a lookup table may be employed, where the lookup table stores entries corresponding to reducing g-bit-long polynomials modulo the field-defining polynomial. Such a reducing... Agent: Ridout & Maybee LLP
20090112963 - Method to perform a subtraction of two operands in a binary arithmetic unit plus arithmetic unit to perform such a method: A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular... Agent: International Business Machines Corporation Dept. 18g04/23/2009 > patent applications in patent subcategories. category listing, related patent applications
20090106335 - Speed-level calculator and calculating method for dynamic voltage scaling: Disclosed is directed to a speed-level calculator and calculating method for dynamic voltage scaling. The speed-level calculator comprises a deadline counter, a shifter, and a fixed-point multiplier. The deadline counter calculates the residual time D from current time through to each task deadline for completing an episode. The shifter generates... Agent: Lin & Associates Intellectual Property, Inc.
20090106336 - Digital signal processing apparatus: Register includes flip-flop circuits each constructed to retain data of n bit in synchronism with a clock pulse, the register retaining a multiplication result of a multiplier dividedly by the flip-flop circuits, n bit per flip-flop circuit. For each of a first and second numeric value data to be multiplied... Agent: Morrison & Foerster, LLP
20090106337 - Serial adder based on \"no-carry\" addition: The invention, based on an original addition algorithm for adding two binary numbers, a and b, and disclosed in the body of this application, is a schematic diagram of a serial, synchronous, digital adder, with circuitry which exemplifies an unusual procedure for calculating the carry at any bit pair, ai... Agent: Rada Higgins
20090106338 - Pseudorandom number generation: A system and method of for obtaining a pseudorandom number generator are disclosed. A set of state modules, each with a limit value, may be provided. In an embodiment, each of the limit values may be relatively prime to the other limit values. In response to one or more events,... Agent: Schneider Electric / Square D Company Legal Dept. - I.p. Group (b&w)
20090106339 - Random number generator: Provided is a random number generator including: a clock generator outputting first and second control signals; a ring oscillator (RO) block receiving a meta stable voltage and performing an oscillation operation using the meta stable voltage in response to the first control signal; and a sampling unit sampling an output... Agent: Harness, Dickey & Pierce, P.L.C
20090106340 - Generation of schedule by which physical items to be manufactured are assigned into production slots via reducing non-zero factors within coefficient matrix clusters: A schedule is generated by which physical items to be manufactured are assigned into production slots. The physical items have constraints governing manufacture of the physical items. The method generates coefficient matrix clusters from a mathematical programming problem based on an actual scheduling problem. Each coefficient matrix cluster defines a... Agent: Law Offices Of Michael Dryja
20090106341 - Dynamically reconfigurable shared baseband engine: A reconfigurable processing block for use in a communications system capable of supporting multiple communication formats. The reconfigurable processing block comprises a plurality of modular processing elements. The processing elements comprise a pn-code generating means, a twiddle factor generating means, coefficient memory means, input data memory means, output data memory... Agent: Ratnerprestia
20090106342 - Circuit and method for performing multiple modulo mathematic operations: A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathematic argument to obtain one or more final partial modulo products. The final partial modulo... Agent: Davidson Berquist Jackson & Gowdey LLP
20090106343 - Method and structure for producing high performance linear algebra routines using composite blocking based on l1 cache size: A method (and structure) for performing a matrix subroutine, includes storing data for a matrix subroutine call in a computer memory in an increment block size that is based on a cache size.... Agent: Mcginn Intellectual Property Law Group, PLLC04/16/2009 > patent applications in patent subcategories. category listing, related patent applications
20090100117 - Semiconductor integrated circuit: The invention reduces unnecessary electromagnetic radiation noise due to an operation clock signal generated by an oscillator circuit. Random number data outputted by a random number generation circuit is stored in a frequency variable data register. The data stored in the frequency variable data register is replaced by random number... Agent: Morrison & Foerster LLP
20090100118 - Algorithm for creating unique bingo faces: A method and apparatus for generating a plurality of unique configurations of indicia is provided. A first set of indicia is provided, including a plurality of first groups of indicia. Then a second set of indicia is provided that has a plurality of second groups of indicia. The first set... Agent: Fay Sharpe LLP
20090100119 - Semiconductor integrated circuit: The invention reduces unnecessary electromagnetic radiation noise associated with a step pulse of an output signal. A random number control register is a register for controlling start, standby, stop, timing or the like of output of random number data from a random number generation circuit. Random number data outputted by... Agent: Morrison & Foerster LLP
20090100120 - Modular multiplication method, modular multiplier and cryptosystem having the same: Provided are a modular multiplication method with an improved arithmetic operation, a modular multiplier and a cryptograph calculating system having the modular multiplier. The modular multiplication method comprises performing a first arithmetic operation including a first multiplication on a first bit string of a multiplicand and a first bit string... Agent: Harness, Dickey & Pierce, P.L.C
20090100121 - Apparatus and method for low complexity combinatorial coding of signals: During operation of an encoder, a signal vector (x) is received. A first multi-precision operand (Ψ′k) will be generated based on the signal vector to be encoded. A mantissa operand and an exponent operand are generated. Both the mantissa operand and the exponent operand are representative of a second multi-precision... Agent: Motorola, Inc.
20090100122 - Saturation and rounding in multiply-accumulate blocks: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation... Agent: Ropes & Gray LLP04/09/2009 > patent applications in patent subcategories. category listing, related patent applications
20090094302 - Incorporating noise and/or jitter into waveform generation: One or more embodiments are disclosed that involve computer implementable techniques for generating simulate-able waveforms without the need for repeatedly including and simulating a full channel model or testing the waveforms on a physical channel. Techniques according to such embodiments the invention comprise simulating the sending of a waveform across... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.
20090094303 - Filter operation unit and motion-compensating device: A filter operation unit that performs a multiply-accumulate operation on input data and a filter coefficient group including a plurality of coefficients using Booth's algorithm. The filter operation unit includes: at least two filter multiplier units that multiply the input data and a difference between adjacent filter coefficients in a... Agent: Sughrue Mion, PLLC
20090094304 - System and method for adaptive nonlinear filtering: An adaptive nonlinear filtering system includes an adaptive filter module that is configured to generate relative location information pertaining to a relative location of an input signal within an input range; determine an input dependent filter parameter based at least in part on the relative location information; generate an output... Agent: Van Pelt, Yi & James LLP
20090094305 - System for displaying spectral trends in complex signals: A method for displaying changes in spectral content of data signals over periods of time using a computer system. The method includes the steps of transforming time segments of digitized data signals into a frequency based spectral representation of the digitized data. The resulting spectral data are then grouped into... Agent: Jeanne E. Longmuir
20090094306 - Cordic rotation angle calculation: A computer-implemented method for performing a calculation using a coordinate rotation digital computer (CORDIC) algorithm. A step of the coordinate rotation digital computer algorithm is performed. As a result of performing the step, a value of the coordinate rotation digital computer algorithm is reduced. The value is shifted using a... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090094307 - Accuracy improvement in cordic through precomputation of the error bias: Performing a calculation using a coordinate rotation digital computer (CORDIC) algorithm. Execution of the CORDIC algorithm is begun. An error introduced by a truncated vector as a result of executing the CORDIC algorithm is pre-computed. The error is incorporated into a subsequent iteration of the CORDIC algorithm. Execution of the... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090094308 - Relaxed remainder constraints with comparison rounding: A system and method for efficient floating-point rounding in computer systems. A computer system may include at least one floating-point unit for floating-point arithmetic operations such as addition, subtraction, multiplication, division and square root. For the division operation, the constraints for the remainder may be relaxed in order to reduce... Agent: Rory D. Rankin Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20090094309 - System and method to implement a matrix multiply unit of a broadband processor: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier... Agent: Mcdermott Will & Emery LLP04/02/2009 > patent applications in patent subcategories. category listing, related patent applications
20090089346 - Method for performing a division operation in a system: A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on the initial error; d) determining whether to apply the... Agent: Lexmark International, Inc. Intellectual Property Law Department
20090089347 - Method and device for generating a random number in a usb (universal serial bus) peripheral: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of... Agent: Seed Intellectual Property Law Group PLLC
20090089348 - Adaptive precision arithmetic unit for error tolerant applications: Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090089349 - Angle computation method and related circuit: Computing an angle between a real part and an imaginary part of a complex number includes receiving complex number data; generating a first value, a second value and a determination result according to the complex number data; choosing a dividend and a divisor of a division operation from the first... Agent: North America Intellectual Property Corporation
20090089350 - Modular reduction operator: This invention concerns an improved modular reduction device. The modular reduction device includes a multiplier using an alternative of the Montgomery multiplication process using a high numeration base r with r being equal to or greater than 4. It applies more particularly to the calculation components used for asymmetrical cryptography.... Agent: Lowe Hauptman & Berner, LLPPrevious industry: Data processing: database and file management or data structures
Next industry: Electrical computers and digital processing systems: multicomputer data transferring or plural processor synchronization
RSS FEED for 20130509:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers: arithmetic processing and calculating patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers: arithmetic processing and calculating patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers: arithmetic processing and calculating patents we recommend signing up for free keyword monitoring by email.
FreshPatents.com Support - Terms & Conditions
Results in 0.60036 seconds