Electrical computers: arithmetic processing and calculating inventions 03/09

20090083350 - Shift-add based random number generation: A system for pseudorandom number generation. A processor is provided that has a first memory to hold a first value and a second memory to hold a second value. Then a logic performs a +* operation while a looping condition is true.... Agent: Henneman & Associates, PLC

20090083351 - Exponentiation calculation apparatus and exponentiation calculation method: A exponentiation calculation apparatus includes a dividing unit which divides an input value as an element of a torus T2(Fq̂r) (r is an odd prime, q is a power of a prime) into first and second elements (of Fq̂r), a first calculating unit which calculates some multiplications on a base... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20090083352 - Methods and apparatus for performing reduced complexity discrete fourier transforms using interpolation: Methods and apparatus arc provided for performing reduced complexity discrete Fourier transforms using interpolation An input sequence of length N is transformed by extending the input sequence to an extended input sequence of length M, where M is greater than N (a power of two greater than N); performing a... Agent: Ryan, Mason & Lewis, LLP

20090083353 - Transitioning a filter function of a two-port lattice-form planar waveguide optical delay line circuit filter from a start filter function to a target filter function: Optically coherent, two-port, serially cascaded-form optical delay line circuits can realize arbitrary signal processing functions identical to those of FIR digital filters with complex filter coefficients whilst maintaining a maximum optical transmission characteristic of 100%. The invention provides an iterative process for transitioning in a step-wise manner a filter function... Agent: Louis Paul Herzberg

20090083354 - Methods and systems for compression, storage, and generation of digital filter coefficients: A method and system for compressing coefficients of a digital filter is provided. In one approach, the method comprises providing a digital filter having a plurality of consecutive filter coefficients including a first filter coefficient, determining consecutive difference values between each of the consecutive filter coefficients, and storing the first... Agent: Fogg & Powers LLC

20090083355 - Convolution integral calculation apparatus: A convolution integrator that can be used favorably to prepare, at high speed, a computer generated hologram that can reproduce a reproduction image formed by reproduction points at various distances and differing in initial phase is provided. A plurality of element processors PE are practically cascade-connected. Each element processor PE... Agent: Drinker Biddle & Reath (dc)

20090083356 - Finite differences methods: The application of finite differences methods to solve boundary value problems typically involves a discretization of such a problem across an orthogonal array of discrete grid points. This leads to an array of difference equations which is solved numerically within the constraints of the boundary conditions to yield solutions at... Agent: Levisohn Berger LLP

20090083357 - Method and apparatus implementing a floating point weighted average function: A method, computer-readable medium, and an apparatus for implementing a floating point weighted average function. The method includes receiving an input containing 2N input values, 2N weights, and an opcode, where N is a positive integer number and each of the input values corresponds to one of the weights. Furthermore,... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090083358 - Emulation of a fixed point operation using a corresponding floating point operation: A computer emulates a fixed-point operation that is normally performed on fixed-point operands, by use of a floating-point operation that is normally performed on floating-point operands. Several embodiments emulate a fixed-point operation by: expanding at least one fixed-point operand into a floating-point representation (also called “floating-point equivalent”), performing, on the... Agent: Silicon Valley Patent Group LLP

20090083359 - Apparatus for calculating square root: Provided is a square root calculation apparatus. The apparatus includes a section judgment unit, a coefficient storing unit, and an adder. The section judgment unit stores information regarding a plurality of sections obtained by dividing an entire range of an input value into predetermined intervals, and judges one of the... Agent: Lowe Hauptman Ham & Berner, LLP

20090083360 - Shift-add based parallel multiplication: A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a... Agent: Henneman & Associates, PLC

20090083361 - Shift-add based multiplication: A system for multiplication of multi-bit first and second values. A processor is provided that has first and second memories with bit-positions that can all be zero or one and where the first memory has a low bit (LB). The first value is arranged in the first memory so its... Agent: Henneman & Associates, PLC

20090077143 - Nonlinear filtering and deblocking applications utilizing simd sign and absolute value operations: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality... Agent: Intel Corporation C/o Intellevate, LLC

20090077144 - Method and apparatus for performing finite field calculations: In general terms, the invention provides a finite field engine and methods for operating on elements in a finite field. The finite field engine provides finite field sub-engines suitable for any finite field size requiring a fixed number of machine words. The engine reuses these engines, along with some general... Agent: Blake, Cassels & Graydon LLP

20090077145 - Reconfigurable arithmetic unit: A reconfigurable arithmetic circuit including a matrix having a plurality of partial product mask cells arranged in rows and columns, where rows and columns have incrementing arithmetic weights assigned, each partial product mask cell including a gate implementing a logical AND function of its inputs to provide an output, and... Agent: Peter Su

20090077147 - Multi-bit sampling of oscillator jitter for random number generation: An apparatus includes an oscillator, a counter for counting pulses, and a latch for latching a count from the counter in response to changes in a logic level of an output of the oscillator. The apparatus can further include an edge detector for producing a latching signal in response to... Agent: Pietragallo Gordon Alfano Bosick & Raspanti, LLP

20090077146 - On-line randomness test for restart random number generators: An apparatus includes a first counter for counting successive bits representative of a logic 1, and a second counter for counting successive bits representative of a logic 0, wherein a first predetermined count on the first counter or a second predetermined count on the second counter indicates a randomness failure.... Agent: Pietragallo Gordon Alfano Bosick & Raspanti, LLP

20090077148 - Methods and apparatus for perturbing an evolving data stream for time series compressibility and privacy: Techniques for perturbing an evolving data stream are provided. The evolving data stream is received. An online linear transformation is applied to received values of the evolving data stream generating a plurality of transform coefficients. A plurality of significant transform coefficients are selected from the plurality of transform coefficients. Noise... Agent: Ryan, Mason & Lewis, LLP

20090077149 - Asynchronous sampling rate conversion: Asynchronous sampling rate converter using multistage oversampling with final stage polyphase filter coefficients approximated by polynomials of the filter index. The approximation polynomial coefficients occupy smaller memory than the polyphase filter coefficients being approximated.... Agent: Texas Instruments Incorporated

20090077150 - Method and system for controlling a voltage waveform: A method of automating a process for controlling a voltage waveform applied to an object is provided. A first waveform for applying to the object is received. A first FFT of the first waveform is calculated. A second waveform for input to the waveform generator is determined based on the... Agent: Wisconsin Alumni Research Foundation (warf)

20090077151 - Multi-input, multi-state switching functions and multiplications: Methods to create an implementation for a multi-input n-state logic function with at least one inverter at an input by modifying the truth table according to the inverter into a reduced truth table are provided. Implementations of the reduced truth table by gates and inverters are also disclosed. Applying reduced... Agent: Diehl Servilla LLC

20090077152 - Handling denormal floating point operands when result must be normalized: A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090077153 - Reconfigurable arithmetic unit: A reconfigurable arithmetic circuit including a plurality of logical AND gates arranged in logical columns and rows, a plurality of conductors each connected to furnish input to the AND gates of a row, an array of memory cells each connected to furnish input to one of the AND gates, and... Agent: Peter Su

20090077154 - Microprocessor: Provided is a microprocessor including a complex-MAC unit that operates in response to a complex-MAC instruction. The complex-MAC unit receives first and second complex data (each having 2m-bit length) from a first register having a register length of at least 2m+1 bits, and also receives third and fourth complex data... Agent: Mcginn Intellectual Property Law Group, PLLC

20090077155 - High speed adder design for a multiply-add based floating point unit: A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent... Agent: Ibm Corporation (cs) C/o Carr LLP

20090070394 - Canonical signed digit multiplier: A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090070395 - Interpolation function generation circuit: An interpolation function generation circuit is formed by cascade connecting a first FIR filter (10) having a numerical value string composed of a ratio “−α, α, β, β, α, −α” (α is an emphasis coefficient and β is a fixed value) as a filter coefficient and a second FIR filter... Agent: Connolly Bove Lodge & Hutz LLP

20090070396 - Waveform equalizing device: Tap coefficients for a filter for removing a ghost signal are converged to optimum values in a short time. The waveform equalizing device includes: an initial tap coefficient generation section for determining and outputting the initial values of tap coefficients for a FIR filter and an IIR filter based on... Agent: Mcdermott Will & Emery LLP

20090070397 - Method for active noise reduction and an apparatus for carrying out the method: In active noise reduction, at least one input signal (25) is fed to a computing unit (18), which passes on the at least one input signal (25) to at least one additional computing unit (19), wherein the at least one input signal (25) is processed for the generation of at... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090070398 - Method and apparatus for an area efficient transcendental estimate algorithm: A method, computer-readable medium, and an apparatus for generating a transcendental value. The method includes receiving an input containing an input value and an opcode and determining whether the opcode corresponds to a trigonometric operation or a power-of-two operation. The method also includes calculating a fractional value and an integer... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090070399 - Arithmetic processing system and method thereof: An arithmetic processing system processes a sensing signal and a first approximate offset signal to obtain a second approximate offset signal. The system includes a first arithmetic processor and a second arithmetic processor. The first arithmetic processor receives and processes the sensing signal and the first approximate offset signal to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090070400 - Carry-select adder: A carry select adder to add two binary addends to produce a binary sum. In a first section a first addition block adds 6-bit addend slices having 3-bit lower-half and higher-half slices. A first adder block receives and adds the lower-half slices and outputs an adder-carry-out and a 3-bit lower-half... Agent: Henneman & Associates, PLC

20090063597 - Numerical analysis device and numerical analysis program: A second derivative of a second-order differential equation is calculated at a reference variable value. The second derivative is multiplied by an analytical small variable value, the first derivative at the reference variable value is added, and a result is output as a first derivative after an increment of the... Agent: Wenderoth, Lind & Ponack, L.L.P.

20090063598 - Apparatus and method for calculating and visualizing targets: A computer-readable medium includes executable instructions to define a target value, define an achievement boundary range, define specific values for the achievement boundary range, and combine the target value, achievement boundary range, and specific values associated with the achievement boundary range to form an absolute target metric object.... Agent: Sap Global C/o Cooley Godward Kronish LLP William S. Galliani

20090063599 - Fast computation of products by dyadic fractions with sign-symmetric rounding errors: A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate... Agent: Qualcomm Incorporated

20090063600 - Computing device and method for converting between julian calendar days and chinese calendar dates: A method and computing device is provided for converting between Chinese calendar dates and Julian day numbers in any specified date range using tables stored in the memory of the computing device containing the lengths of the months and which (if any) months are leap months, together with one or... Agent: Saul Ewing LLP (philadelphia)

20090063601 - Method of generating unique pseudorandom numbers: A method of generating a set of unique pseudorandom N-digit base-B integers includes the steps of selecting an integer A, wherein A is equal to or greater than 0 and equal to or less than BN−1, and adding to integer A an integer P, modulus BN, wherein P is equal... Agent: Dillon & Yudell, LLP

20090063602 - Device and method for preventing wiretapping on power line: Provided are a device and method for detecting a wiretapping device using a power line and nullifying the wiretapping device. More particularly, a device and method for preventing wiretapping, which sense a wiretapping signal from a power line and transmit a noise signal to the power line, are provided. The... Agent: Ladas & Parry LLP

20090063603 - Apparatus and method for time-series storage with compression accuracy as a function of time: The present invention provides a system and method for time-series with compression accuracy as a function of time. Briefly described, in architecture, one embodiment of the system, among others, can be implemented as follows. The system includes a computer with a processor. The system performs a method receiving a data... Agent: Cantor Colburn LLP-ibm Yorktown

20090063604 - Vdsl2 transmitter/receiver architecture: The invention suggests a novel pipeline FFT/IFFT architecture that not only produces time-domain samples (after IFFT) but also pushes time-domain samples into FFT in a time-based sequential order. This reduces external memory requirement for buffering the time-domain samples. Also the design is based on a mixed radix-2 and radix-22 algorithm... Agent: Law Offices Of Barry N. Young

20090063605 - Signal processing device: A device capable of improving the convergence rate and estimation accuracy in estimating a correlation value. According to a signal processing device, since a window length is adjusted in such a manner to reduce an estimated error of a correlation matrix, the convergence rate and estimation accuracy in estimating the... Agent: Rankin, Hill & Clark LLP

20090063606 - Methods and apparatus for single stage galois field operations: Techniques for single function stage Galois field (GF) computations are described. The new single function stage GF multiplication requires only m-bits per internal logic stage, a savings of m−1 bits per logic stage that do not have to be accounted for as compared with a previous two function stage approach.... Agent: Peter H. Priest

20090063608 - Full vector width cross product using recirculation for area optimization: Embodiments of the invention are generally related to the field of image processing, and more specifically to vector units for supporting image processing. A vector unit may comprise a plurality of operand multiplexers associated with each vector processing lane of the vector unit. The operand multiplexers may select vector operands... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090063607 - Method and structure for fast in-place transformation of standard full and packed matrix data formats: A method and structure for an in-place transformation of matrix data. For a matrix A stored in one of a standard full format or a packed format and a transformation T having a compact representation, blocking parameters MB and NB are chosen, based on a cache size. A sub-matrix A1... Agent: Mcginn Intellectual Property Law Group, PLLC

20090063609 - Static 4:2 compressor with fast sum and carryout: In one embodiment, a compressor circuit has a carry-in input and input bits a, b, c, and d. The compressor circuit comprises a first multiplexor (mux) coupled to receive a value of input bit a and a complement of the value of input bit a as inputs and a value... Agent: Mhkkg, PC/apple, Inc.