Electrical computers: arithmetic processing and calculating inventions 02/09

20090055453 - Data entry method and apparatus: On a portable electronic device, multiple-position toggle button data entry keys are provided within the data entry keypad. A controller detects activation of each multiple-position toggle button data entry key on the keypad by a user, and also detects the number of times the data entry key is activated. The... Agent: Mayer & Williams PC

20090055454 - Half width counting leading zero circuit: A circuit and method are provided for storing a data word in a latch and determining the number of consecutive equal value bits within the data word. The data word consists of bits stored in unique bit positions and having a least significant bit position and a most significant bit... Agent: Ibm Corporation

20090055455 - Microprocessor: A microprocessor has an instruction decode portion, a register file, a complex operation unit, and a data storage position determining mechanism. The complex operation unit performs complex operation, including complex multiplication, using first and second complex number data supplied from the register file based on an instruction decoded by the... Agent: Young & Thompson

20090055456 - Data correction circuit: A circuit and method are provided for correcting binary values in a data word having N bit positions where the circuit includes several assemblies, each for a unique data word bit position, where each assembly includes a first logic circuit connected to its unique data word bid and an adjacent... Agent: Ibm Corporation

20090055457 - Field device with capability of calculating digital filter coefficients: A digital filter design algorithm is implemented directly within a process control field device or other process related equipment. Filter design parameters are exposed so that filter design parameter values may be provided to the digital filter design algorithm so that the digital filter design algorithm may calculate digital filter... Agent: Marshall, Gerstein & Borun LLP (fisher)

20090055458 - Substitution boxes: A multiple-input multiple-output s-box receives a contiguously numbered input bits (101, 102, 103, 104, 105) I1, I2 to Ia, where a is at least 4, and outputs b contiguously numbered output bits (131, 132, 133, 134, 135) O1, O2, to Ob. The s-box comprises c primitive s-boxes (121, 122, 123)... Agent: Hoffman Wasson & Gitler, P.c Crystal Center 2, Suite 522

20090055459 - Frequency-domain equalizer: A digital signal processing structure includes a processing unit configured to perform a fast Fourier transformation of length N on signal samples of word length WL, wherein the processing unit is configured to vary during operation the values of N and WL_in in a reverse fashion with respect to one... Agent: Eschweiler & Associates LLC

20090049111 - Method, apparatus and system for resistance to side channel attacks on random number generators: A random number generator (RNG) resistant to side channel attacks includes an activation pseudo random number generator (APRNG) having an activation output connected to an activation seed input to provide a next seed to the activation seed input. A second random number generator includes a second seed input, which receives... Agent: Keusey, Tutunjian & Bitetto, P.C.

20090049112 - Interleaved method for parallel implementation of the fast fourier transform: The present invention generally relates to a method for computing a Fast Fourier Transform (FFT). In one embodiment, the present invention relates to an interleaved method for computing a Fast Fourier Transform (FFT).... Agent: Roetzel And Andress

20090049113 - Method and apparatus for implementing a multiple operand vector floating point summation to scalar function: Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises computing an arithmetic result of a pair of operands in each processing lane of a vector unit. The arithmetic results generated in each processing lane of the vector unit may... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090043834 - Dvi link with parallel test data: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of... Agent: Schwegman, Lundberg & Woessner/micron

20090043835 - Method for efficient and reliable computation of results for mathematical functions: A method is provided for efficient computation of reliable results for mathematical functions. The method may include an interface, a control module, and an error module. The interface receives a mathematical function call. The call includes a plurality of arguments for which a range of computable results for the mathematical... Agent: Kunzler & Mckenzie

20090043836 - Method and system for large number multiplication: Methods, apparatus and systems for large number multiplication. A multiplication circuit is provided to compute the product of two operands (A and B), at least one of which is wider than a width associated with the multiplication circuit. Each of the operands includes contiguous ordered word-wide operand segments (Aj and... Agent: Fish & Richardson P.C.