Electrical computers: arithmetic processing and calculating inventions 11/08

20080294706 - Novel adder structure with midcycle latch for power reduction: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage... Agent: International Business Machines Corporation

20080294707 - Random number generation device and vehicle control device: A random number generation device including a first random number generation part which generates a new random number based on a random number which was previously generated and which outputs the random number generated by the first random number generation part, the random number generation device includes: a second random... Agent: Arent Fox LLP

20080294708 - Methods, systems, and computer program products for parallel correlation and applications thereof: A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0-XM-1) with encoding coefficients (C0-CM-1), wherein each of (X0-XM-1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080294709 - Processing geometric data using spectral analysis: In one embodiment, the present invention includes a method for receiving vertex data corresponding to a surface of an image, performing a discrete Fourier transform (DFT) on the vertex data to obtain a frequency response, zero padding the frequency response to obtain zero padded frequency response data, and performing an... Agent: Trop Pruner & Hu, PC

20080294710 - Extending a repetition period of a random sequence: A method is provided for extending a sequence repetition period of a random number generator in systems based on the availability of random sequences. The method includes performing RNS arithmetic operations to express a random number in a sequence as RNS residue values. Each generated random number has a value... Agent: Harris Corporation C/o Darby & Darby PC

20080288565 - Method to compare and sort binary data: A binary data comparison method is performed as follows. First, bits of a plurality of binary data are provided, and bit x of the plurality of binary data are summed, where x=n, n−1, . . . , 1 or 0, and bit x is the most significant bit (MSB). If... Agent: Wpat, PC Intellectual Property Attorneys

20080288566 - Multimedia information providing system, server device, terminal equipment, multimedia information providing method, and computer-readable medium: In a multimedia information providing system, responding to a preview request from a terminal equipment, a server device generates a chaotic random number sequence from an initial value allocated to the terminal equipment, mixes this sequence into a set of multimedia information as a noise signal at a first mixing... Agent: Howard & Howard Attorneys, P.C.

20080288567 - Fir filter process and fir filter arrangement: The present invention relates to a FIR filter process (1′) and to a respective FIR filter arrangement (1) wherein at least one multiplex mode is given which is characterized in that in the respective summation stage (30′) or summation block (30) partial summations are carried out and controlled in conformity... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080288568 - Low power fast hadamard transform: Fast Hadamard transforms (FHT) are implemented using a pipelined architecture having an input stage, a processing stage, and an output stage, the FHT having a single internal loop back between the output stage and the input stage, the processing stage having at least one Hadamard processing unit. The FHT implementations... Agent: Carole A. Mulchinski , M1/040 The Aerospace Corporation,

20080288569 - Pipelined fft processor with memory address interleaving: An interleaver for use with transform processors provides an address generator allowing for implementation using a reduced memory foot print, and permitting interleaving of an input sequence while minimizing latency.... Agent: Procopio, Cory, Hargreaves & Savitch LLP

20080288570 - Correlation device: A correlation device is provided that includes an adder for adding an input signal sequence and an auxiliary signal sequence to obtain an addition signal sequence, and a delay element for delaying the addition signal sequence to obtain the auxiliary signal sequence, whereby the delay element has a plurality of... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080288571 - Arithmetic device for performing division or square root operation of floating point number and arithmetic method therefor: When division X/Y of floating point numbers is performed, bit string data of a mantissa x including a fraction xf of X or a mantissa y including a fraction yf of Y is shifted in accordance with magnitude relation between them to perform a fraction computation. Thereby, a fraction division... Agent: Staas & Halsey LLP

20080281889 - Pocket calculator for financial, mathematical calculation routines: The invention relates to a pocket calculator for financial, mathematical calculation routines, comprising a keypad (11) comprising several input keys and function keys for the input of data, a memory which is used to memorise permanent data and volatile data, a processor which is used to carry out the financial,... Agent: Michael L. Leetzow, Esq. Michael L. Leetzow, P.A.

20080281890 - Fast correctly-rounding floating-point conversion: A system and method for converting bases of floating point numbers using fixed-point computation includes tables having different related spacings of exponent indices. The tables are adapted to cross-reference conversion ratios between exponent bases. The tables are characterized by bi-uniform spacings of source and target exponents and including near-unity table... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080281891 - Parallel computation structures to enhance signal-quality, using arithmetic or statistical averaging: Parallel hardware computation structures for integrated-circuit arithmetic and statistical signal averaging are described herein as an invention that is applicable to broad systems applications where a variety of analog-to-digital and digital-to-analog data interfaces occur. Signal values are improved to accommodate signal reconstruction of high quality and at high frequencies. The... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080281892 - Method and apparatus for generating pseudo random numbers: The present invention proposes a methodology implementable in form of a hardware or software module for generating a pseudo random number. The pseudo random number corresponds to a pseudo random sequence of bits, which form the pseudo random number. A plurality of m polynomials is provided. The polynomials are derived... Agent: Alston & Bird LLP

20080281893 - Optimization of spectrum extrapolation for causal impulse response calculation using the hilbert transform: A causal impulse response function is calculated from a truncated spectrum by extending the real part of the spectrum beyond the truncation frequency and computing the imaginary part with the Hilbert transform to enforce causality. The out of band extrapolation is optimized to reduce the discrepancy between the computed and... Agent: Agilent Technologies Inc.

20080281894 - Digital architecture for dft/idft hardware: Embodiments of the present invention can provide circuits and systems for computing a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). An embodiment includes an input circuit, an intermediate circuit, an output circuit, and an accumulator circuit. The input circuit can receive a set of input values,... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080281895 - Method and device for calculating a similarity metric between a first feature vector and a second feature vector: The method of calculating a similarity metric between a first feature vector of a first audio and/or video signal and a second feature vector of a second audio and/or video signal of the invention comprises the step of calculating a distance between the first feature vector and the second feature... Agent: Philips Intellectual Property & Standards

20080281896 - Industrial controller: A first arithmetic operator (11) includes a first modular arithmetic coding encoder (11b) for encoding a numeric data transmitted by a command from a central controller (31) into a modular arithmetic code, a first arithmetic operation processor (11a) using the numeric data as modular arithmetic coded as an input operand,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080281897 - Universal execution unit: Methods and apparatus are described for an execution unit. A method includes receiving an instruction and one or more operands, determining a plurality of program bits and one or more sets of pluralities of select input bits, based on the instruction and the one or more operands, determining a plurality... Agent: Daaven S. Messinger

20080275929 - Use of line characterization to configure physical layered devices: A method of optimizing filter performance through monitoring channel characteristics is provided. A signal enters a channel and a receiver receives the signal. The receiver includes a FIR filter to remove near-end transmitted interference and recover a far-end desired signal. The filter has storage elements configured as a shift registers... Agent: Lumen Patent Firm, Inc.

20080275930 - Convolution operation circuit: There is provided a convolution operation circuit that performs a convolution operation on a provided digital signal. The convolution operation circuit includes a data dividing section that generates a plurality of divided data obtained by dividing respective amplitude data of the digital signal into a plurality of bit areas, an... Agent: Jianq Chyun Intellectual Property Office

20080275931 - Executing fixed point divide operations using a floating point multiply-add pipeline: A system and method for executing fixed point divide operations using a floating point multiply-add pipeline are provided. With the system and method, the floating point execution unit in a processor is modified to include elements that may be used to perform fixed point divide operations. These additional elements include... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080275932 - Integer division in a manner that counters a power analysis attack: In the course of performing an Elliptic Curve Scalar Multiplication operation by Additive Splitting Using Division, a main loop of an integer division operation may be performed. The integer division has a dividend and a divisor. By storing both the divisor and the negative value of the divisor, susceptibility to... Agent: Ridout & Maybee LLP