Electrical computers: arithmetic processing and calculating inventions 10/08

20080263115 - Very long arithmetic logic unit for security processor: An arithmetic and logic unit carries out arithmetic or logic operations on long operands. The unit comprises: an operation unit having a processing location, and configured for carrying out processing on bits at the processing location, the processing comprising any of a plurality of pre-defined arithmetic or logical operations, the... Agent: Martin D. Moynihan Prtsi, Inc.

20080263116 - Balanced pseudo-random binary sequence generator: Disclosed is a method for producing, in an electronic circuit, a varying digital output in response to edges of a received clock signal. The method includes generating, within circuitry of the electronic circuit, an unbalanced, pseudo-random binary output of the circuitry. The method also includes generating, within the electronic circuit... Agent: Eaton Peabody Patent Group, LLC

20080263117 - Initial seed management for pseudorandom number generator: A secure seeding and reseeding scheme is provided for pseudorandom number generators by using a pre-stored initialization seed. This scheme initializes a pseudorandom number generator into an unknown state even when entropy collection is unavailable. A primary seed file and a shadow seed file are maintained with initialization seed information... Agent: Qualcomm Incorporated

20080263118 - System for convolution calculation with multiple computer processors: A process for loading a signal data values and convolution filter coefficient values into a target processor (ct) in a set of processors (cutil) utilized to calculate a convolution. The coefficient values are mapped to cutil. An interleave of the data values and of the coefficient values determined for ct.... Agent: Henneman & Associates, PLC

20080263119 - Digital generation of a chaotic numerical sequence: A method is provided for generating a chaotic sequence. The method includes selecting a plurality of polynomial equations. The method also includes using residue number system (RNS) arithmetic operations to respectively determine solutions for the polynomial equations. The solutions are iteratively computed and expressed as RNS residue values. The method... Agent: Harris Corporation C/o Darby & Darby PC

20080263120 - Method and system for optimizing floating point conversion between different bases: A method of streamlining floating-point conversions includes determining a source coefficient and a source exponent of an input value represented by a floating-point number in a source base; estimating an approximated target exponent (ATE) using the source coefficient and the source exponent, in the event the source coefficient has a... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080263121 - Method and system for optimizing floating point conversion between different bases: A method of performing floating-point conversions in a digital computing system includes determining a source coefficient, c1, and a source exponent, n, of an input value represented by a floating-point number in a source base, b1; converting the source coefficient to a common base, b2, and storing the converted coefficient... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080263122 - Multi-function floating point arithmetic pipeline: A scalable engine having multiple datapaths, each of which is a unique multi-function floating point pipeline capable of performing a four component dot product on data in a single pass through the datapath, which allows matrix transformations to be computed in an efficient manner, with a high data throughput and... Agent: Dickstein Shapiro LLP

20080263123 - Method and system for determining a minimum number and a penultimate minimum number in a set of numbers: There is provided a system for determining a minimum number and a penultimate minimum number in a set of numbers. According to one embodiment, the system includes a first comparator module configured to receive a first subset of the set of numbers and to compare the first subset to determine... Agent: Farjami & Farjami LLP

20080263115 - Very long arithmetic logic unit for security processor: An arithmetic and logic unit carries out arithmetic or logic operations on long operands. The unit comprises: an operation unit having a processing location, and configured for carrying out processing on bits at the processing location, the processing comprising any of a plurality of pre-defined arithmetic or logical operations, the... Agent: Martin D. Moynihan Prtsi, Inc.

20080263116 - Balanced pseudo-random binary sequence generator: Disclosed is a method for producing, in an electronic circuit, a varying digital output in response to edges of a received clock signal. The method includes generating, within circuitry of the electronic circuit, an unbalanced, pseudo-random binary output of the circuitry. The method also includes generating, within the electronic circuit... Agent: Eaton Peabody Patent Group, LLC

20080263117 - Initial seed management for pseudorandom number generator: A secure seeding and reseeding scheme is provided for pseudorandom number generators by using a pre-stored initialization seed. This scheme initializes a pseudorandom number generator into an unknown state even when entropy collection is unavailable. A primary seed file and a shadow seed file are maintained with initialization seed information... Agent: Qualcomm Incorporated

20080263118 - System for convolution calculation with multiple computer processors: A process for loading a signal data values and convolution filter coefficient values into a target processor (ct) in a set of processors (cutil) utilized to calculate a convolution. The coefficient values are mapped to cutil. An interleave of the data values and of the coefficient values determined for ct.... Agent: Henneman & Associates, PLC

20080263119 - Digital generation of a chaotic numerical sequence: A method is provided for generating a chaotic sequence. The method includes selecting a plurality of polynomial equations. The method also includes using residue number system (RNS) arithmetic operations to respectively determine solutions for the polynomial equations. The solutions are iteratively computed and expressed as RNS residue values. The method... Agent: Harris Corporation C/o Darby & Darby PC

20080263120 - Method and system for optimizing floating point conversion between different bases: A method of streamlining floating-point conversions includes determining a source coefficient and a source exponent of an input value represented by a floating-point number in a source base; estimating an approximated target exponent (ATE) using the source coefficient and the source exponent, in the event the source coefficient has a... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080263121 - Method and system for optimizing floating point conversion between different bases: A method of performing floating-point conversions in a digital computing system includes determining a source coefficient, c1, and a source exponent, n, of an input value represented by a floating-point number in a source base, b1; converting the source coefficient to a common base, b2, and storing the converted coefficient... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080263122 - Multi-function floating point arithmetic pipeline: A scalable engine having multiple datapaths, each of which is a unique multi-function floating point pipeline capable of performing a four component dot product on data in a single pass through the datapath, which allows matrix transformations to be computed in an efficient manner, with a high data throughput and... Agent: Dickstein Shapiro LLP

20080263123 - Method and system for determining a minimum number and a penultimate minimum number in a set of numbers: There is provided a system for determining a minimum number and a penultimate minimum number in a set of numbers. According to one embodiment, the system includes a first comparator module configured to receive a first subset of the set of numbers and to compare the first subset to determine... Agent: Farjami & Farjami LLP

20080256150 - Three-path fused multiply-adder circuit: A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a... Agent: Eric Quinnell

20080256152 - Random number generating device: The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080256151 - Weighted entropy pool service: A weighted entropy pool service system and methods. Weights are associated with entropy sources and are used to estimate a quantity of entropy contained in data from the entropy sources. An interface is optionally provided to facilitate connecting user entropy sources to the entropy pool service. The quantity of entropy... Agent: Woodcock Washburn LLP (microsoft Corporation)

20080256153 - Random number signal generator using pulse oscillator: A random number signal generator using pulse oscillators, the generator including: a first pulse oscillator oscillating a first pulse at high speed; a second pulse oscillator oscillating a second pulse; a sampler receiving an output pulse of the first oscillator as data, receiving an output pulse of the second pulse... Agent: Ladas & Parry LLP

20080256154 - Method and apparatus for synthesizing a user defined pre-emphasized arbitrary waveform for high speed serial data technologies: The embodiments herein provide a device and method to generate Pre-emphasized signal. In one embodiment herein an input file containing digital data representing a digital data pattern waveform is received and up-sampled by an Fs/Fd rate. The up-sampled digital data is used for generating step response. The generated step response... Agent: William K. Bucher Tektronix, Inc.

20080256155 - System and method to compute narrow bounds on a modal interval polynomial function: A computer executable method of processing a representation of a modal interval polynomial is provided. A representation of a modal interval polynomial is generally provided as input, more particularly, a representation comprising a modal interval function variable and an array of modal interval coefficients. Each modal interval linear interpolation of... Agent: Nawrocki, Rooney & Sivertson Suite 401, Broadway Place East

20080256156 - Reliable and efficient computation of modal interval arithmetic operations: A computer executable method of performing a modal interval operation, and system for performing same is provided. The method includes providing representations of first and second modal interval operands. Each modal interval operand of the operands is delimited by first and second marks of a digital scale, each mark of... Agent: Nawrocki, Rooney & Sivertson Suite 401, Broadway Place East

20080256157 - Information processing device and information processing method: An information processing device for processing reception signals converted into digital signals, includes: a first conversion unit for executing sampling rate conversion of each of the digital signals to be computed with each tap coefficient of a K'th-order FIR filter; a filter computing unit for executing computation processing of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080256158 - Matching movement behavior in motion graphics: Computer-implemented methods and media bearing instructions for matching movements of objects are described. In one example, the method can include determining a position of a first point in a first coordinate system, converting the position of the first point from the first coordinate system to a second coordinate system, performing... Agent: Fish & Richardson P.C.

20080256159 - Multi-stream fft for mimo-ofdm systems: The present invention proposes a signal processor for Fast Fourier Transformation, FFT, of MR, MR>1, input data streams of 2k samples each, supplied in parallel. After multiplexing the input data streams in an interlaced manner, the resulting stream is subjected to FFT. The FFT device has a pipeline architecture composed... Agent: Squire, Sanders & Dempsey L.L.P.

20080256160 - Reduction of digital filter delay: An apparatus for reducing a digital filter delay includes means for determining the magnitude response of a desired filter. Means form the real cepstrum of this magnitude response. Means transform the real cepstrum into a complex cepstrum of a corresponding minimum-phase filter having the same magnitude response as the desired... Agent: Ericsson Inc.

20080256161 - Bridge fused multiply-adder circuit: A bridge fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The bridge fused multiply-add unit adds this functionality to existing floating-point co-processor units by including a fused multiply-add hardware “bridge” between an existing floating-point adder and a floating-point multiplier unit. This fused multiply-add... Agent: Dillon & Yudell LLP

20080256162 - X87 fused multiply-add instruction: An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the third addend operand as a third x87 FPU register... Agent: Huffman Law Group, P.C.

20080256163 - Apparatus and method of generating codebook for multiple input multiple output communication system: An apparatus and method of generating a codebook. The codebook generation apparatus includes a matrix extender to generate a candidate matrix set by multiplying a base matrix and at least one diagonal matrix, wherein the at least one diagonal matrix includes elements of a constrained set as diagonal elements; and... Agent: Stein, Mcewen & Bui, LLP

20080256164 - Methods and apparatus for carry generation in a binary look ahead system: Methods and apparatus provide for a carry generation tree for a carry look-ahead binary adder, which includes N stages of operators, reducers, and/or repeaters, wherein: a first of the stages receives binary outputs from a series of binary adders; a last of the stages produces a carry out signal representing... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20080256165 - Full-adder modules and multiplier devices using the same: A full-adder module (30) comprises a full-adder comprising a plurality of input and output terminals, a sum generation unit and a carry generation unit. The carry generation unit comprises a programmable inverter arranged to selectively invert a carry-in bit to the carry generating unit in response to a control signal... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080250090 - Adaptive filter device and method for determining filter coefficients: An adaptive filter device, including a finite impulse response (FIR) filter which is based on filter coefficients, which are determined based on a predetermined iterative adaptation algorithm for determining filter coefficients of an adaptive filter, wherein, in at least one iteration step of said predetermined iterative adaptation algorithm a sum... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080250091 - Custom character-coding compression for encoding and watermarking media content: An apparatus for compressing media content is disclosed. The apparatus divides the media content into at least three predetermined portions, compresses each of the at least three portions using one of at least three different compression algorithms and makes the at least three compressed predetermined portions publicly available. Making the... Agent: At&t Corp.

20080250092 - System for convolution calculation with multiple computer processors: A system for calculating a convolution of a data function with a filter function utilizing an array of processors including first and last processors. A coefficient value based on a derivation of the filter function and a data value representative of the data function are multiplied to produce a current... Agent: Henneman & Associates, PLC

20080250093 - Method and apparatus for filtering multiple channels of signals: To reduce chip size and lower cost by using a method of multiplexing a device to filter a plurality of signals, the present invention provides an apparatus for filtering the plurality of signals, comprising: a group of storage units, for storing the plurality of signals, wherein the group of storage... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080250094 - Efficient implementations of kernel computations: A method and apparatus for efficiently performing digital signal processing is provided. In one embodiment, kernel matrix computations are simplified by grouping similar kernel coefficients together. Each coefficient group contains only coefficients having the same value. At least one of the coefficient groups has at least two coefficients. Techniques are... Agent: Hickman Palermo Truong & Becker / Tessera Inc.

20080243971 - Method and apparatus for calculating an ssd and encoding a video signal: The present invention relates to a method and apparatus for calculating the Sum of Squared Differences (SSD) between a source block and a reconstructed block of image or video data encoding according to an encoding scheme such as H.264/AVC. In a preferred embodiment, the method computes the SSD by finding... Agent: Stites & Harbison PLLC

20080243972 - High density planar magnetic domain wall memory apparatus and method of forming the same: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location;... Agent: Cantor Colburn LLP-ibm Yorktown

20080243973 - Locking of an integrated circuit: A method for protecting an integrated circuit. According to the method, the start-up of all, or part, of the circuit is determined in the presence of a key which is recorded in a non-volatile manner in the circuit, following the production thereof, and depends on at least one first parameter... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080243974 - Electronic data shift device, in particular for coding/decoding with an ldpc code: The electronic shift device includes N inputs and N outputs, a configurable barrel shifter connected between the N inputs and the N outputs. A second shifter is arranged and connected between some of the outputs of the barrel shifter and some of the N outputs according to different predetermined organizations... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080243975 - Sensor driving circuit: A sensor driving circuit includes a shift circuit that outputs clock signals the high level period of each of which is limited to a predetermined period in one pulse period and whose high level periods are shifted by one pulse period from each other, to respective capacitance elements each of... Agent: Oliff & Berridge, PLC

20080243976 - Multiply and multiply and accumulate unit: The present invention relates to a multiply apparatus and a method for multiplying a first operand consisting of na bits and a second operand consisting of nx bits. In one embodiment the multiply apparatus comprising a CSA (CSA) unit with nx rows each comprising na AND gates for calculating a... Agent: Texas Instruments Incorporated

20080243977 - Pseudorandom number generator and encrytion device using the same: A pseudorandom number generator reduced in size while maintaining high security is disclosed. The generator has a state storage unit of 2 blocks (n bits per block) and a buffer of plurality of blocks, and mixes their contents to obtain a random number sequence. The mixing is done by a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080243978 - Random number generator: A random number generator includes an amplifier to amplify a difference between a noise signal and a reference signal to generate an amplified signal, a plurality of binarization circuits configured to binarize the amplified signal by using different inherent threshold values to obtain a plurality of binarized signals, and an... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20080243979 - Data stream filters and plug-ins for storage managers: A storage manager and related method and computer program product manages client data on a data storage resource and includes the ability to utilize many different types of data stream filters that are neither built into the storage manager nor require a custom programming effort. A storage manager user may... Agent: Walter W. Duft

20080243980 - Coupling simulations with filtering: Systems, techniques, and machine-readable instructions for coupling simulations with filtering. In one aspect, a method is for coupling simulations with filtering of data. The method includes generating a first visual rendition of a first collection of display data and a second visual rendition of a second collection of display data,... Agent: Fish & Richardson, P.C.

20080243981 - Method and apparatus for accelerating processing of adaptive finite impulse response filtering: Finite impulse response filtering is achieved by broadcasting to at least one compute unit an instruction having a plurality of data samples, a conditional field associated with each compute unit, and a set of operator values for operating on each data sample; providing a function of each the data sample... Agent: Iandiorio & Teska

20080243982 - Hardware matrix computation for wireless receivers: In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different... Agent: Mendelsohn & Associates, P.C.

20080243983 - Residual fourier-padding interpolation for instrumentation and measurement: A technique for interpolating a series of samples includes constructing a mathematical model of the series that describes its large signal behavior. The model is subtracted from the original series to yield a residue. A discrete Fourier transform (DFT) is taken of the residue, and the DFT is zero-padded. An... Agent: Law Office Of Bruce D. Rubenstein

20080243984 - Coordinate transformation for presentation in display systems: A system and method for displaying data provided by a sensor in Polar coordinates on a raster scan device operating in Cartesian coordinates. Cartesian coordinates for display points on said raster scan device are converted to corresponding Polar coordinates, and sensor data values for said Polar coordinates are fetched for... Agent: Ericsson Inc.

20080243985 - Method and apparatus for performing multiplicative functions: A new function for calculating the reciprocal residual of a floating-point number X is defined as recip_residual(X)=1−X*recip(X), where recip(X) represents the reciprocal of X. The function may be implemented using a fused multiply-add unit in a processor. The reciprocal value of X, recip(X), may be obtained from a lookup table.... Agent: Intel Corporation C/o Intellevate, LLC