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USPTO Class 708 | Browse by Industry: Previous - Next | All 09/2008 | Recent | 09: Oct | Sept | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 08: Dec | Nov | Oct | Sp | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 07: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 06: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Electrical computers: arithmetic processing and calculating inventions 09/08Recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.Listing format for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 09/25/2008 > patent applications in patent subcategories. 20080235310 - Difference degree evaluation device, difference degree evaluation method and program product: A difference degree evaluation device includes a signal acquisition unit which acquires at least two signals which are objects of matching, a memory unit which stores one of the two signals, which are acquired by the signal acquisition unit, as a reference signal, and stores the other of the two... Agent: Frishauf, Holtz, Goodman & Chick, PC 20080235311 - Simplified equalization for correlated channels in ofdma: Systems and methodologies are described that facilitate equalization of received signals in a wireless communication environment. Multiple transmit and/or receive antennas and utilize MIMO technology to enhance performance. A single tile of transmitted data, including a set of modulation symbols, can be received at multiple receive antennas, resulting in multiple... Agent: Qualcomm Incorporated 20080235312 - Method and arrangement for suppressing noise in digital signal sequences and a corresponding computer program and a corresponding computer-readable storage medium: The present invention relates to a method and an arrangement for suppressing noise in digital signal sequences, and to a corresponding computer program and a corresponding computer-readable storage medium, which can be used in particular to smooth and/or improve the signal-to-noise ratio in digital signal processing and in digital image... Agent: Nxp, B.v. Nxp Intellectual Property Department 20080235313 - Signal processing method and signal processing circuit: A signal processing method includes a first step of calculating a value indicating a value obtained by multiplying a ratio of the number of times of inputting the input signal having any one of values from p to m, where m is a maximum value of values of input signal... Agent: Fitzpatrick Cella Harper & Scinto 20080235314 - Method of generating random access preambles in wireless communication system: A method of generating random access preambles includes receiving information on a source logical index and generating random access preambles in the order of increasing cyclic shift from root ZC sequences with the consecutive logical indexes from the beginning of the source logical index until a predetermined number of the... Agent: Lee, Hong, Degerman, Kang & Schmadeka 20080235315 - Technique for solving np-hard problems using polynomial sequential time and polylogarithmic parallel time: A system and technique, called Solution Enumeration technique, for finding efficient algorithms for NP-hard combinatorial problems is presented. The solution space of these problems grows exponentially with the problem size. Some examples in this class are: Hamiltonian Circuit, SAT, Graph Isomorphism, and Perfect Matching problems. The core of this technique... Agent: Javaid Aslam 20080235316 - Processor with adaptive multi-shader: The disclosure describes an adaptive multi-shader within a processor that uses one or more high-precision arithmetic logic units (ALUs) and low-precision ALUs to process data based on the type of the data. Upon receiving a stream of data, the adaptive multi-shader first determines the type of the data. For example,... Agent: Qualcomm Incorporated 09/18/2008 > patent applications in patent subcategories.20080228844 - Method of enhancing spectral data: A method of enhancing spectral data such as a frequency, wavelength or mass spectrum comprises applying an inverse Fourier Transform to the data in the frequency, wavelength or mass spectrum, zero-filling and, optionally, apodizing that inverse transform data, and then applying a Fourier Transform to convert the inverse data back... Agent: Haynes And Boone, LLP 20080228845 - Apparatus for calculating an n-point discrete fourier transform by utilizing cooley-tukey algorithm: An apparatus for calculating an N-point Discrete Fourier Transforms (DFTs) and/or Inverse DFTs (IDFTs) using the Cooley-Tukey algorithm is provided. The N-point DFT/IDFT is achieved by calculating a plurality of N1-point and N2-point DFTs. The apparatus comprises a storing unit, a calculating unit, and a controlling unit. The storing unit... Agent: Holland & Knight LLP 20080228846 - Processing apparatus and control method thereof: A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series... Agent: Staas & Halsey LLP 20080228847 - N bit adder and corresponding adding method: An n bit adder includes first computing circuit with 2n inputs for receiving n values of bits of first and second binary numbers and an additional input for receiving an input carry digit. The first computing circuit elaborates from each of the n pairs of bit values of the same... Agent: Westman Champlin & Kelly, P.A. 09/11/2008 > patent applications in patent subcategories.20080222226 - Bandwidth efficient instruction-driven multiplication engine: Multiplication engines and multiplication methods are provided for a digital processor. A multiplication engine includes multipliers, each receiving a first operand and a second operand; a local operand register having locations to hold the first operands for respective multipliers; a first operand bus coupled to the local operand register to... Agent: Wolf Greenfield & Sacks, P.c. 20080222227 - Design structure for a booth decoder: A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit is used to... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.c. 20080222228 - Bank of cascadable digital filters, and reception circuit including such a bank of cascaded filters: The present invention relates to a bank of digital filters that can be cascade connected. It also relates to a reception circuit comprising such a bank of cascaded filters. With the digital filter being sampled at a given sampling frequency Fs, the bank of cascadable digital filters has: at the... Agent: Lowe Hauptman & Berner, LLP 20080222229 - Determination of incremental value in server processed data: The accumulated change in values representative of actions taken by a processor, such as the number of email messages processed by an email server, in a given time period is determined. Actions are represented as data points on a plot. Look-ahead intervals are defined for each point. Candidate pairs of... Agent: Woodcock Washburn LLP (microsoft Corporation) 20080222230 - Multiplier-divider having error offset function: A multiplier-divider capable of offsetting errors includes a plurality of multiplication and division units to perform processes and arrangements so that errors generated by signals passing through the multiplier-divider are offset. As a result impact of the errors is reduced. More than one processing signal can be obtained from the... Agent: Joe Mckinney Muncy 09/04/2008 > patent applications in patent subcategories.20080215650 - Efficient multiple input multiple output signal processing method and apparatus: A method and apparatus are disclosed for use with multiple input, multiple output (MIMO) signal processing techniques, which reduce the amount of memory and memory bandwidth used to store and access filter coefficients by compressing a filter coefficient based at least in part on one or more neighboring filter coefficients... Agent: Weide & Miller, Ltd. 20080215651 - Signal separation device, signal separation method, signal separation program and recording medium: A frequency domain transforming section 2 transforms mixed signals observed by multiple sensors into mixed signals in the frequency domain, a complex vector generating section 3 generates a complex vector by using the frequency-domain mixed signals, a normalizing section 4 generates a normalized vector excluding frequency dependence of the complex... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C. 20080215652 - Constellation-multiplexed transmitter and receiver: A device of dynamic communication of information allows, on the average, non-integer bits per symbol transmission, using a compact code set or a partial response decoding receiver. A stream of selectable predetermined integer bits, e.g., k or k+1 data bits, is grouped into a selectable integer number of bit vectors... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c. 20080215653 - Data processing device with multi-endian support: A data processing device includes at least one first and one second component which are coupled to one another. The first component is operable in a first endian mode, while the second component is operable in a second endian mode, which is different from the first endian mode.... Agent: Slater & Matsil LLP 20080215654 - Video decoding with reduced idct calculations: Reduced complexity inverse discrete cosine transform (IDCT) masks and a method for reducing the number of IDCT calculations in video decoding are provided. The method comprises: accepting an n×m matrix of DCT coefficients; performing (n−y) horizontal IDCT operations, where y is greater than 0; performing y scaling operations; and, generating... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski 20080215655 - Multi-carrier transmission process and system in a difficult environment with optimisation of emission power: characterised in that at least two distinct scramblings (20, 21) of the data are completed, such that there is a first and a second set of scrambled data. After passage in a single complex inverse Fourier transform, that intended for emission is selected (26), whereof the dynamic in amplitude is... Agent: Blakely Sokoloff Taylor & Zafman LLP 20080215656 - Fast fourier transform circuit and fast fourier transform method: A fast Fourier transform circuit includes a computation component, an extraction component and a setting component. The extraction component, at each step of the computation, extracts, from computation result data points calculated by the computation component, data in a pre-specified range with a number of bits the same as a... Agent: Volentine & Whitt PLLC 20080215657 - Messaging method: This invention relates to a short message format that captures useful information embedded in a data vector of a sequence of symbols or numbers. The data vector may represent many different forms of information generated by various electronic and information systems. This short message format is particularly useful when bandwidth... Agent: Knobbe Martens Olson & Bear LLP 20080215658 - Generic implementations of elliptic curve cryptography using partial reduction: A reduction operation is utilized in an arithmetic operation on two binary polynomials X(t) and Y(t) over GF(2), where an irreducible polynomial Mm(t)=tm+am−1tm−1+am−2tm−2+ . . . +a1t+a0, where the coefficients ai are equal to either 1 or 0, and m is a field degree. The reduction operation includes partially reducing... Agent: Mhkkg/sun 20080215659 - Round for reround mode in a decimal floating point instruction: a round-far-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are... Agent: International Business Machines Corporation 20080215660 - Three-term input floating-point adder-subtractor: The three-term input floating-point adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent... Agent: Antonelli, Terry, Stout & Kraus, LLP 20080215661 - Waveform correction apparatus and waveform correction method: This disclosure concerns a waveform corrector comprising a first portion calculating an offset value of an intermediate value between a maximum value and a minimum value of a signal with respect to a reference value; a second portion calculating an actual amplitude of the signal by subtracting the offset value... Agent: Dla Piper US LLP Previous industry: Data processing: database and file management or data structuresNext industry: Electrical computers and digital processing systems: multicomputer data transferring or plural processor synchronization ###### RSS FEED for 20091112: Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates. For more info, read this article. ###### Thank you for viewing Electrical computers: arithmetic processing and calculating patents on the FreshPatents.com website. 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