Electrical computers: arithmetic processing and calculating inventions 08/08

20080208939 - Decoder device and decoding method: A decoder having an element decoding unit generating external information for input data, including an exponent position determining unit, when the external information output from the element decoding unit is input, of information excluding a sign bit from the external information, specifying an exponent that is a bit position where... Agent: Hanify & King Professional Corporation

20080208940 - Reconfigurable circuit: A reconfigurable circuit including a multiplier for multiplying a value, an accumulator for cumulatively adding said multiplied value and a round-off processing unit for rounding off said cumulatively added value; wherein said multiplier, said accumulator and said round-off processing unit are disposed within a single processing element and said accumulator... Agent: Arent Fox LLP

20080208941 - Interpolation process circuit: There are included a three-tap FIR calculating part (2) that multiples data outputted from three taps on a tapped delay line by respective filter factors comprising a ratio value sequence of “−1, m, −1”; and an n-tap FIR calculating part (3) that multiples data outputted from n taps on a... Agent: Connolly Bove Lodge & Hutz LLP

20080208943 - Data transform method and apparatus, data processing method and apparatus, and program: When sample data is played back, audio guide data G1 and G2 and subsequent frame data are played back based on usage license information L1 contained in the sample data. When high-quality data is generated, the audio guide data G1 and G2 and the usage license information L1 are overwritten... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080208942 - Parallel architecture for matrix transposition: An extension to current multiple memory bank video processing architecture is presented. A more powerful memory controller is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths making possible new combinations of reads and writes at the input and output ports. Matrix transposition... Agent: Texas Instruments Incorporated

20080208944 - Digital signal processor structure for performing length-scalable fast fourier transformation: A digital signal processor structure by performing length-scalable Fast Fourier Transformation (FFT) discloses a single processor element (single PE), and a simple and effective address generator are used to achieve length-scalable, high performance, and low power consumption in split-radix-2/4 FFT or IFFT module. In order to meet different communication standards,... Agent: Birch Stewart Kolasch & Birch

20080208945 - Method to compute an approximation to the reciprocal of the square root of a floating point number in ieee format: Approximations of reciprocal square roots are provided in IEEE floating point binary format by obtaining an index from an input value, accessing a pair of table values and performing a limited number of simple and rapidly performed manipulations. The maximum relative error in the approximation thus provided is less than... Agent: Whitham, Curtis, & Christofferson, P.c.

20080208946 - Method of data analysis: A method of analysis of incomplete data sets to detect fraudulent data is disclosed. The method comprises computing constant values for various leading digit sequence lengths, computing artificial Benford frequencies for the digit sequence lengths, computing a standard deviation for each of the sequence lengths, and flagging any digit sequences... Agent: Hodgson Russ LLP The Guaranty Building

20080208947 - Method and appratus for evaluating visitors to a web server: Different web pages on a web server are associated with different qualification profiles, each of which is assigned a value by the web-site proprietor. Traffic data hits at the web-site are analyzed to determine which web pages the visitor viewed on the web server. Each qualifying visitor is thereafter associated... Agent: Marger Johnson & Mccollom, P.c.

20080208948 - Methods and apparatus for using boolean derivatives to process data: Method and apparatus for generating an Nth order Boolean derivative from r bit-array Qth order partial derivatives combined using fusion. Exemplary applications include multimedia, e.g., signal, image and video, processing systems; security systems; edge detection, compression, filtering, multimedia data, e.g., signal, image, video, interpolation and resizing systems; biometrics and recognition... Agent: Daly, Crowley, Mofford & Durkee, LLP

20080201394 - Computer technical solution of the digital engineering method of hybrid numeral carry system and carry line: The present invention relates to the digital engineering method and the field of computer, and it puts forward a new digital engineering method which can remarkably increase the computation speed and greatly reduce the error rate of written calculation. The present invention uses the “method of hybrid numeral carry system... Agent: Toler Law Group

20080201395 - Method and apparatus for distributing random elements: Apparatus for distributing valid random elements, including at least a first module and a second module. The first module is connected to a provider of valid random elements and to the second module. The first module includes a controller that passes valid random elements from the first module to the... Agent: Dickstein Shapiro LLP

20080201396 - Signal processing apparatus and the correcting method: A signal processing apparatus, comprising: a first filter on an in-phase signal channel; a second filter on a quadrature signal channel; a plurality of filter stages having each of more than one signal paths crossing each other which connects the first filter and the second filter; and at least more... Agent: Hanify & King Professional Corporation

20080201397 - Semi-automatic system with an iterative learning method for uncovering the leading indicators in business processes: Embodiments herein select performance indicators from raw data and measure the indicators over at least one time period to extract a time series of data for each of the indicators. The methods filter out redundant indicators to produce a reduced indicator set of time series of data. The embodiments detect... Agent: Frederick W. Gibb, Iii Gibb I.p. Law Firm, LLC

20080201398 - Determination of a modular inverse: In side-channel attack-resistant encoding methods, a return value (r) is determined as the modular inverse of an input value (a), by a module (M). A resistance to side-channel attack can be achieved with minimal restrictions on implementation on determination of the modular inverse with minimal technical complexity. To this end,... Agent: Baker Botts L.L.P. Patent Department

20080195684 - Apparatus for reducing the latency of sum-addressed shifters: The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.c.

20080195683 - Method for processing sensor data: A method for processing sensor data which are transmitted by at least one asynchronous sensor at a transfer rate, the sensor data being read at a predefined sampling rate, a mean value being computed from a predefined number of read sensor data, wherein the sampling ratio between the sampling rate... Agent: Kenyon & Kenyon LLP

20080195685 - Multi-format multiplier unit: Multiplication engines and multiplication methods are provided. A multiplication engine for a digital processor includes a first multiplier to generate unequally weighted partial products from input operands in a first multiplier mode; a second multiplier to generate equally weighted partial products from input operands in a second multiplier mode; a... Agent: Wolf Greenfield & Sacks, P.c.

20080189344 - Electronic abacus and operation method of the electronic abacus: The invention discloses an electronic abacus and operation method of the electronic abacus. The electronic abacus comprises a calculating apparatus, an input apparatus and a display apparatus. The input apparatus and the display apparatus are connected to the calculating apparatus respectively. The calculating apparatus receives the input information from the... Agent: Fish & Richardson PC

20080189345 - Efficient symbolic differentiation using derivative graph factorization: An efficient symbolic differentiation method and system that automatically computes one or more derivatives of a function using a computing device. A derivative graph is used to graphically represent the derivative of a function. Repeated factorization of the derivative graph yields a factored derivative graph. The derivative is computed by... Agent: Microsoft Corporation C/o Lyon & Harr, LLP

20080189346 - Method for realizing finite field divider architecture: A method for realizing a finite field divider architecture is proposed, in which all standard basis of a divider are transformed into the composite field basis, and the circuit is realized using subfield multiplier, squarer, adder and lookup table over this composite field. The user can finish a division operation... Agent: Sinorica, LLC

20080189347 - Dual multiply-accumulator operation optimized for even and odd multisample calculations: According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed.... Agent: Marvell/finnegan Henderson LLP C/o Finnegan, Henderson, Farabow, Garnett Et. Al.