Electrical computers: arithmetic processing and calculating inventions 06/08

20080154996 - Datapipe synchronization device: A programmable element for data processing comprises a crosspoint switch (318), a mathematical operation module (320), and a plurality of data hold modules (604,606). Each of the data hold modules (604,606) receives data from the crosspoint switch (318) and communicates the data to an input of the mathematical operation module... Agent: Hovey Williams LLP

20080154997 - Systems and methods for function control in a calculation device: Various systems and methods for controlling the functionality of calculation devices are disclosed. For example, some embodiments of the present invention provide function controlled calculation devices that include a functionality environment detector that is operable to receive an environment indication from a functionality environment. The calculation devices further include a... Agent: Texas Instruments Incorporated

20080154998 - Method and apparatus for dividing information bit string: A method of dividing an information bit string by a generator polynomial includes dividing the information bit string into a plurality of sub-bit strings A1 through AN, multiplying a remainder value by each bit of a sub-bit string Ai (1≦i≦N) successively with a most significant bit first so as to... Agent: Bingham Mccutchen LLP

20080154999 - Compressed floating point representation of points on monotonic curves which can be specified by high order equations: Using different number of data bits to represent points in corresponding different sections of a high order monotonic curve in a floating point format. More number of data bits are used to represent one section of the curve, while correspondingly fewer data bits are used to represent another section of... Agent: Texas Instruments Incorporated

20080155000 - Efficient kernel calculation for interpolation: A method of determining interpolation coefficients (607, 609, 610, 611) of a symmetric interpolation kernel (608) is disclosed. The method comprises determining a first interpolation coefficient (611) from the symmetric interpolation kernel (608) and storing the first interpolation coefficient in a memory (506). The method then determines the value of... Agent: Fitzpatrick Cella Harper & Scinto

20080155001 - Method for efficient and zero latency filtering in a long impulse response system: A method for long impulse response digital filtering of an input data stream, by use of a digital filtering system. Where the input data stream is divided into zero-input signals and zero-state signals. One of the zero-input signals and a corresponding impulse response of the digital filtering system is converted... Agent: Seed Intellectual Property Law Group Pllc

20080155002 - Combined fast fourier transforms and matrix operations: Embodiments of a hardware accelerator having a circuit configurable to perform a plurality of matrix operations and Fast Fourier Transforms (FFT) are presented herein.... Agent: Lee & Hayes, Pllc C/o Intellevate, Llc

20080155003 - Pipeline-based reconfigurable mixed-radix fft processor: The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to... Agent: Troxell Law Office Pllc

20080155004 - Arithmetic circuit, arithmetic method, and information processing device: To provide a floating point arithmetic circuit for efficiently defecting an error, which has a large numerical error, with a less circuit amount, the floating point arithmetic circuit comprises a first arithmetic unit for outputting a first arithmetic result, a second arithmetic unit for outputting a second arithmetic result, and... Agent: Staas & Halsey LLP

20080155005 - Dtmf lockout utility using epoch time stamp: A method for converting a first time and a first date in a first format to a second time in a second format includes determining a number of seconds that have elapsed between a predetermined date and a beginning of a current year of the first date. The method further... Agent: Greenblum & Bernstein, P.L.C

20080147758 - Variational error correction system and method of grid generation: A system and method for automatically generating a computation mesh for use with an analytical tool, the computation mesh having a plurality of ξ-grid lines and η-grid lines intersecting at grid points positioned with respect to an inner boundary and an outer boundary. The system and method include one or... Agent: Downs Rachlin Martin Pllc

20080147759 - Self-authenticating quantum random bit generators: Various embodiments of the present invention are directed to self-authenticating, quantum random bit generators that can be integrated into an optoelectronic circuit. In one embodiment, a quantum random bit generator comprises a transmission layer that includes an electromagnetic radiation source coupled to a waveguide branching into a first, second, and... Agent: Hewlett Packard Company

20080147760 - System and method for performing accelerated finite impulse response filtering operations in a microprocessor: A system and method for accelerating the performance of finite impulse response (FIR) filtering operations in a processor system. The system and method accelerates FIR filtering operations by using a holding register to provide additional input samples to an instruction beyond those normally accommodated by source registers, and by using... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080147762 - Digital audio processing system and method: A digital audio processing system and method is disclosed. In an embodiment, the digital audio processing system can include a phase detector to sample an input signal and provide an output to adjust a decimation rate of an input signal. In another embodiment, the digital audio processing system can include... Agent: Toler Law Group

20080147761 - Signal processing system with a digital sample rate converter: A signal processing system includes a digital sample rate converter to convert a signal sampled at a first sampling frequency into a corresponding signal sampled at a second sampling frequency. In at least one embodiment, the sample rate converter includes a digital sample rate conversion filter. The digital sample rate... Agent: Hamilton & Terrile, LLP

20080147763 - Method and apparatus for using state space differential geometry to perform nonlinear blind source separation: Given a time series of possibly multicomponent input data, the method and apparatus includes a device that finds a time series of “source” components, which are possibly nonlinear combinations of the input data components and which can be partitioned into groups that are statistically independent of one another. These groups... Agent: Brinks Hofer Gilson & Lione

20080147765 - Encoding and decoding data arrays using separate pre-multiplication stages: Some embodiments of the invention provide a method of performing a Discrete Cosine Transform (“DCT”) encoding or decoding coefficients of a data array by (1) multiplying the coefficients by a scalar value before the encoding or decoding, and then (2) dividing the encoded or decoded coefficients by the scalar value.... Agent: Adeli & Tollen, LLP

20080147764 - Motion estimation in image processing systems: A motion estimator 50 for image processing finds a motion vector from a search area in a reference picture to a source macroblock in a source picture by finding a maximum of a 2-dimensional normalised cross-correlation surface between the source macroblock and a portion of the reference search area using... Agent: Seyfarth Shaw LLP

20080147766 - Circuit arrangement and method for receiving specially designed coded signals: In order to attain an optimally compressed, narrow pulse peak at the filter output of a correlation filter for the purpose of reception, the interfering secondary maxima of the autocorrelation function of binary codes must be as small as possible. The invention uses specially designed signal codes which are used... Agent: Fish & Richardson P.c.

20080147767 - Binomial options pricing model computations using a parallel processor: Binomial options pricing model computations are performed on node values of a lattice using a parallel processor such as a single-instruction, multiple-data processor. The parallel processor stores computational data in on-chip memory. Data to be processed by a group of threads executing the binomial options pricing model computations is read... Agent: Townsend And Townsend And Crew LLP

20080147768 - Configurable exponent fifo: The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second... Agent: Grossman, Tucker, Perreault & Pfleger, Pllc C/o Intellevate, Llc

20080147769 - Device and method for enabling multi-value digital computation and control: Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as... Agent: William J. Kolegraff

20080147770 - Input device: An input device includes a power unit, a power switch unit, a processing unit, and an input unit. The power switch unit includes a first switch for supplying power to the processing unit when actuated; the input unit is connected with the processing unit and the power switch unit and... Agent: North America Intellectual Property Corporation

20080140739 - Cryptographic device employing parallel processing: A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to each of the plurality of calculating subunits. A cryptographic operation is distributed among the individual calculating subunits in the form... Agent: Lerner Greenberg Stemer LLP

20080140740 - Systems and methods for processing data sets in parallel: Various parallel processing devices, methods for designing such and using such are disclosed herein. For example, a parallel linear processing device is disclosed that includes two multipliers. One of the multipliers is operable to multiply a feedback signal by a first value and to provide a first multiplier output. The... Agent: Hamilton And Desanctis

20080140741 - method for using the fundamental homotopy group in assessing the similarity of sets of data: A method for finding sequences of similar data (SDDs), which are similar to a target sequence of digital data, is invented. The method leverages a new category of signatures, called equivalence signatures, to characterize the SDDs. These signatures have the salient feature that, at worst, they change in a bounded... Agent: Roger K. Brooks

20080140742 - Method for finding minimal signed digit with variable multi-bit coding based on booth's algorithm: Provided is a method for finding a minimal signed digit with variable multi-bit coding. The method includes the steps of: scanning and grouping given multi-bit and checking the type of each group; deciding whether each group is to be performed by any one of a coding for positive number and... Agent: Ladas & Parry LLP

20080140743 - Acs unit and method thereof: An add-compare-select (ACS) unit generates first path metrics having a first bit-pair and a most significant bit-pair (MSB), where each bit-pair is in represented in redundant numbers comprising a high bit and a low bit, and comprises a first ACS circuit and an MSB ACS circuit. The first ACS circuit... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080140745 - Arithmetic method and device of reconfigurable processor: Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing... Agent: Blakely Sokoloff Taylor & Zafman

20080140744 - Dividers: The present invention relates to a divider for dividing a dividend by a divisor. The divider includes a subtractor for subtracting the divisor from the dividend to produce a result, storage space with a preliminary answer, and a processor for revising the dividend and preliminary answer based on the result.... Agent: Dann, Dorfman, Herrell & Skillman

20080140746 - Fast quantum mechanical initial state approximation: A system and method efficiently prepare the initial state of q quantum computer required by the eigenvalue approximation method of Abrams and Lloyd. The system and method can be applied when solving continuous Hermitian eigenproblems, e.g. the Schrodinger equation, on a discrete gird, and allows for efficient calculation of their... Agent: Wilmerhale/columbia University

20080140747 - Complex multiplier and twiddle factor generator: The present invention relates to a complex multiplier and a twiddle factor generator. The complex multiplier according to an embodiment of the invention includes: a first adder/subtracter that adds the real part of the complex number and a first twiddle factor or subtracts the first twiddle factor from the real... Agent: Jefferson Ip Law, LLP

20080140748 - Computer-implemented systems and methods for determining steady-state confidence intervals: Computer-implemented systems and methods for estimating confidence intervals for output generated from a computer simulation program that simulates a physical stochastic process. A plurality of statistical tests is performed upon the physical stochastic simulated output so that a confidence interval can be determined.... Agent: Patent Group 2n Jones Day

20080140750 - Apparatus and method for performing rearrangement and arithmetic operations on data: An apparatus and method are provided for performing rearrangement operations and arithmetic operations on data. The data processing apparatus has processing circuitry for performing SIMD processing operations and scalar processing operations, a register bank for storing data and control circuitry responsive to program instructions to control the processing circuitry to... Agent: Nixon & Vanderhye, Pc

20080140749 - Method and device for performing a quantum algorithm to simulate a genetic algorithm: A method and device for performing a quantum algorithm where the superposition, entanglement with interference operators determined for performing selection, crossover, and mutation operations based upon a genetic algorithm. Moreover, entanglement vectors generated by the entanglement operator of the quantum algorithm may be processed by a wise controller implementing a... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.a.

20080140752 - Method and apparatus for efficient matrix multiplication in a direct sequence cdma system: System and method for processing symbols in a communication system are disclosed and may include in a processor that receives symbols to be coded for transmission over a wireless medium, grouping elements of an input matrix across a second dimension of the input matrix to form groups of matrix elements... Agent: Mcandrews Held & Malloy, Ltd

20080140751 - Technique for detecting anomaly in observation target: A system, method, and computer program product allowing an information processing apparatus to function as a system for detecting an anomaly in an observation target on the basis of time series data. The system includes a first generation unit, a second generation unit, a singular vector computation unit, a matrix... Agent: Shimokaji & Associates, P.c.

20080140753 - Multiplier: An electronically implemented method includes multiplying a number A, and a number B, where A is composed of segments ai and B is composed of segments bj where i and j are integers greater than 1. The multiplying includes determining partial product values for at least some of aibj and... Agent: Intel/blakely

20080140754 - Device for checking numbers and method for checking numbers: A device for checking numbers consists of a multiplexer (101) with a controller module (106) linked to it. An output of the multiplexer is connected to a first input of a register (102), which is an element of memory, while a first output of the controller module (106) is connected... Agent: Matthias Scholl

20080140755 - Mixed-signal system for performing taylor series function approximations: A mixed-signal system for performing Taylor series function approximations is disclosed. The mixed-signal system includes a digital-to-analog converter (DAC), multiple resistor-to-resistor (R2R) ladders, various digital registers, a digital processor and an analog integrator. The digital processor calculates coefficients F, Fx, Fy, Fxx, Fxy, Fyy of a Taylor series equation and... Agent: Dillon & Yudell LLP

20080133625 - Method and apparatus for implementing finite impulse response filters without the use of mutipliers: A finite impulse response filter is implemented as a sum of individual component, running-sum filters. The sum of all of the component filters required for a desired filter response is calculated in an accumulator and only the component filters' update terms, which are the difference between a new and an... Agent: Bachman & Lapointe, P.c.

20080133626 - Calculator device having a usb connection: A method for transferring a signal between a calculator device having a USB connector and a remote device is described. The method includes: connecting the calculator device with the remote device using the USB connector; transmitting a signal from the remote device to the calculator device using the USB connector;... Agent: Hewlett Packard Company

20080133627 - Large multiplier for programmable logic device: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but... Agent: Ropes & Gray LLP

20080133628 - System and method for an efficient comparision operation of multi-bit vectors in a digital logic circuit: An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector... Agent: Global Ip Services, Pllc

20080133629 - Random cache line refill: A microprocessor including random cache line refill ordering to lessen side channel leakage in a cache line and thus thwart cryptanalysis attacks such as timing attacks, power analysis attacks, and probe attacks. A random sequence generator is used to randomize the order in which memory locations are read when filling... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080133630 - Interpolation fir filter having multiple data rates in mobile communication system and method of filtering data using the same: The present invention relates to an interpolation FIR (finite impulse response) filter having multiple data rates in a mobile communication system, and a method of filtering data using the same. In the method of filtering data using the interpolation FIR filter, a first filter uses an FIR low pass filter... Agent: Jefferson Ip Law, LLP

20080133631 - Equalizer using infinitive impulse response filtering and associated method: An equalizer for equalizing an input signal includes an infinitive impulse response (IIR) filtering portion for filtering the input signal to produce N filtered outputs; a gain-adjusting portion coupled to the IIR filtering portion with N gains for adjusting the N filtered outputs to produce N gained outputs, respectively; and... Agent: Kirton And Mcconkie

20080133632 - Apparatus and method for comparing protein structures using principal components analysis and autocorrelation: Provided is an apparatus and method for comparing structures of proteins by extracting main axes of the proteins using principal components analysis (PCA), dividing regions using grids into voxels for precise structure alignment, and placing the proteins respectively in the regions to calculate a similarity between the proteins by autocorrelation.... Agent: Ladas & Parry LLP

20080133633 - Efficient implementation of multidimensional fast fourier transform on a distributed-memory parallel multi-node computer: The present in invention is directed to a method, system and program storage device for efficiently implementing a multidimensional Fast Fourier Transform (FFT) of a multidimensional array comprising a plurality of elements initially distributed in a multi-node computer system comprising a plurality of nodes in communication over a network, comprising:... Agent: Scully, Scott, Murphy & Presser, P.c.

20080133634 - 0.75-power computing apparatus and method: A 0.75-power computation apparatus and method are provided in which the range of an input value X is divided into a predetermined number areas, a 0.75 power of the input value X is represented as a predetermined approximation polynomial, coefficients for the approximation polynomial representing the input value X are... Agent: Cha & Reiter, Llc

20080133635 - Nanoelectronics: A circuit element includes a plurality of computation blocks connected at least partially in series for processing multi-bit numbers. Each of the computation blocks includes a plurality of transistors having characteristic threshold voltages. The circuit element is configured so that the transistors will each operate at a voltage below its... Agent: Hayes, Soloway P.c.

20080133636 - High pass filter: A high pass filter adapted for use in a signal processing device comprising a sampler adapted to sample a signal and transmit the samples to the high pass filter, the high pass filter comprising a differentiator and an integrator; a counter which, in use, counts the number of samples received... Agent: Freescale Semiconductor, Inc. Law Department