Electrical computers: arithmetic processing and calculating inventions 05/08

20080126454 - Selectively attachable calculator: A calculator that is selectively attachable to an article attached to a user of the calculator is disclosed. The calculator has an oblong carabiner extending from its bottom end for attaching the calculator to the article. The attachment mechanism includes an oblong loop and an arm that is part of... Agent: The Soni Law Firm

20080126455 - Methods of protecting management frames exchanged between two wireless equipments, and of receiving and transmitting such frames, computer programs, and data media containing said computer programs: a step of the second equipment comparing an image of the numerical value Xk−1 as obtained by the function f as received in the kth management frame (7, 8, 9, 10) with the parameter f(Xk−1) received in the k−1th management frame (3, 4, 5, 6).... Agent: Oliff & Berridge, PLC

20080126457 - Computer system for storing infinite, infinitesimal, and finite quantities and executing arithmetical operations with them: In this invention we describe a new type of computer—infinity computer—that is able to operate with infinite, infinitesimal, and finite numbers in such a way that it becomes possible to execute the usual arithmetical operations with all of them. For the new computer it is shown how the memory for... Agent: Smith Hopen, Pa

20080126456 - Standard cell for arithmetic logic unit and chip card controller: A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The... Agent: Davidson, Davidson & Kappel, LLC

20080126458 - Apparatus and methods for generating random signals: A random signal generator circuit includes a thermal noise generator circuit and a self-biased inverter having an input coupled to the thermal noise generator circuit and to a feedback resistor coupled to an output of the self-biased inverter, the self-biased inverter configured to produce a sensed noise signal at the... Agent: Myers Bigel Sibley & Sajovec

20080126459 - Method and device for generating a filter coefficient in real time: The present invention provides a method and device for generating a filter coefficient in real time. The method includes: looking up a converted window function value in a converted window function table based on a current coefficient index; generating a current cut-off angular frequency; generating a look-up table address based... Agent: Mindray C/o Stoel Rives LLP

20080126460 - Real-time digital quadrature demodulation method and device for ultrasonic imaging system: A real-time digital quadrature demodulation method and device for the ultrasonic imaging system are disclosed in this invention. In addition to a multiplying step and a filtering step, the method further comprises a sine and cosine table generating step for generating the sine and cosine table in real time, and... Agent: Mindray C/o Stoel Rives LLP

20080126461 - Signal processing system employing time and frequency domain partitioning: The present invention relates to a method for processing a digital input signal by a Finite Impulse Response, FIR, filtering means, comprising partitioning the digital input signal at least partly in the time domain to obtain at least two partitions of the digital input signal; partitioning the FIR filtering means... Agent: Brinks Hofer Gilson & Lione

20080126462 - Optimized multi-mode dft implementation: The present invention relates to a method and apparatus for implementing a discrete Fourier transformation (DFT) of a predetermined vector size, wherein at least one enhanced DFT module is provided by using at least one type of DFT module including multiplication by first and second types of twiddle factors in... Agent: Squire, Sanders & Dempsey L.L.P.

20080126463 - Apparatus and method for optimal implementation of the cordic algorithm for wireless rfic digital down-conversion: A CORDIC circuit capable of performing precise vector rotation, including a pre-rotation stage configured to selectively rotate an input vector by 90 degrees and to produce a pre-rotated vector. A first stage is configured to perform a first set of iterative CORDIC calculations on the pre-rotated vector and to produce... Agent: Docket Clerk

20080126464 - Least square clustering and folded dimension visualization: A two dimensional rendition of a multi-dimensional data set is presented wherein the multi-dimensional data set is graphed on a coordinate system having axes that are a predetermined angle away from each other axes in the coordinate system. Each subsequent predetermined angle may be half the previous predetermined angle for... Agent: Quarles & Brady LLP

20080126465 - Calendar-based financial calculator: A computer operated, calendar-based financial calculator comprises a computer display, calendar calculating software, and a calculation engine, so as to provide a visual presentation of any calendar month. Each day of each month of each year has a unique numerical value which can be understood and acted upon by the... Agent: Gowan Intellectual Property

20080126466 - Method and apparatus for accumulating floating point values: A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for directing initial inputs and intermediate result values.... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080126467 - Technique for transposing nonsymmetric sparse matrices: A technique includes receiving a compressed representation of a sparse matrix. The compressed representation is processed in parallel with multiple processors to generate a compressed representation of the sparse matrix transposed.... Agent: Trop Pruner & Hu, PC

20080126468 - Decoding apparatus for vector booth multiplication: A decoding apparatus for Booth multiplication includes a NAND gate, a first and a second OR gate coupled to the NAND gate, a first and a second exclusive NOR gate coupled respectively to the OR gates, a clean-to-zero device coupled to the first and the second OR gates, and a... Agent: Birch Stewart Kolasch & Birch

20080120355 - System and method for generating mathematical equations and symbolic scientific expressions in html and css: A comprehensive method for generating mathematical equations and symbolic scientific expressions using pure HTML and CSS is disclosed. This method renders the equations portable and editable and contrasts with previous procedures that represent equations using a whole built-up graphic objects. An application of the method using HTML and JavaScript is... Agent: Kehinde Alabi

20080120356 - Digital low-pass filter: A digital low-pass filter includes: a first subtracter that subtracts a first feedback term from an input; a first multiplier that multiplies an first subtracter output by a constant k1; a first delay unit that delays an input by a predetermined sampling time; a first adder that supplies, to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080120357 - Software method for solving systems of linear equations having integer variables: This invention describes a software method for computers for solving integer programming problems containing systems of linear equations where part of or all of the variables may take only integer values. Said software method consists of 4 main steps. First, all of or part of said system is transformed into... Agent: Jean-paul Theis

20080114820 - Apparatus and method for high-speed modulo multiplication and division: The method for high-speed modulo multiplication is a method for multiplying integers A and B modulus N that is optimized for high speed implementation in an electronic device, which may be implemented in software, but is preferably implemented in hardware. The multiplication is performed on devices requiring no more than... Agent: Litman Law Offices, Ltd.

20080114821 - Decimation filter: A decimation filter has: a plurality of calculating devices each having a multiplier and an accumulator; a plurality of coefficient memories (a ring memory and shift registers) which store filter coefficients, and which correspond to the calculating devices, respectively; and a selector which sequentially selectively outputs the outputs of the... Agent: Sughrue-265550

20080114822 - Enhancement of extraction of film thickness from x-ray data: A method embodiment of the present method and apparatus may comprise: transforming raw data into flattened data; taking a first derivative of the flattened data to produce derivate data; and applying a Fourier transform to the derivate data to produce transformed data. A system embodiment of the present method and... Agent: Patti, Hewitt & Arezina Llc

20080114823 - Method of transferring data from a first device to a second device: A method of transferring data from a first device to a second device, the method including receiving information at the second device; and converting first data, from the first device, from the time domain to the frequency domain using butterfly computations to produce second data, wherein the butterfly computations used... Agent: Harrington & Smith, Pc

20080114824 - Single precision vector permute immediate with \"word\" vector write mask: The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve performing a plurality of permute operations to arrange vector operands in desired locations of a register prior to performing vector operation, for example, a... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080114825 - Digital signal processing apparatus and digital signal processing method: A digital signal processing apparatus including: an arithmetic circuit that performs first digital signal processing on an input signal SA sampled at a first sampling frequency f1 and second digital signal processing on a result of the first digital signal processing; a timing control circuit that controls and causes the... Agent: Amin, Turocy & Calvin, LLP

20080114826 - Single precision vector dot product with \"word\" vector write mask: The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve performing a plurality of dot product operations to generate operands for generating operands for a new vector. The dot product operations may require the... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080109500 - Systems, devices, and methods for solving computational problems: Systems, devices, and methods for using an analog processor to solve computational problems. A digital processor is configured to track computational problem processing requests received from a plurality of different users, and to track at least one of a status and a processing cost for each of the computational problem... Agent: Seed Intellectual Property Law Group Pllc

20080109502 - Method and apparatus for partitioning of a bitstream: Apparatus for encoding and deciphering inter-chip signals has a single pseudo-random number generator (PRNG) (31, 41, 42) which generates a single pseudo-random number stream. A decision making module (32, 43) creates two pseudo-random number streams from the output of the PRNG (31, 41, 42). Buffers (33, 35, 37, 44, 45)... Agent: Christopher J. Mcdonald Hoffman, Wasson & Gitler

20080109501 - Modular multiplication method with precomputation using one known operand: A modular multiplication method implemented in an electronic digital processing system takes advantage of the case where one of the operands W is known in advance or used multiple times with different second operands V to speed calculation. The operands V and W and the modulus M may be integers... Agent: Schneck & Schneck

20080109504 - Low cost, high purity sign wave generator: An automatic test system that includes low cost and accurate circuitry for generating sinusoidal signals. Each sinusoidal signal generator produces a series of digital values approximating a sine wave. These values are computed, avoiding the need for large memories to store tables representing sine waves. Inaccuracies in the representation of... Agent: Teradyne, Inc. C/o Wolf, Greenfield & Sacks, P.c.

20080109503 - Sine wave generator with dual port look-up table: An automatic test system that includes low cost and accurate circuitry for generating sinusoidal signals. Each sinusoidal signal generator includes a look-up table that can, for each phase on sine wave, output two digital values representing an in-phase and a quadrature-phase value of the sine wave. Simple circuitry can be... Agent: Teradyne, Inc. C/o Wolf, Greenfield & Sacks, P.c.

20080109505 - Fir decimation filter and arrangement comprising the same: A finite impulse response (FIR) decimation filter includes an input to receive an oversampled signal, and an output to provide an output signal having a sampling rate that is reduced by a decimation factor relative to the oversampled signal. The decimation factor corresponds to a sum of one and an... Agent: Fish & Richardson Pc

20080109506 - Data transformation method and data transformation circuit capable of saving numeral operations: A data transformation method capable of saving numeral operations, the data transformation method includes encoding a plurality of digital data to generate a plurality of sets of byte data according to an encoding mode, determining a plurality of repetition patterns of the plurality of sets of byte data, processing shift... Agent: North America Intellectual Property Corporation

20080109507 - System and method for performing an optimized discrete walsh transform: A circuit (26) performs a discrete Walsh transform using a reduced set of arithmetic operators. The circuit (26) comprises a first memory component (32), an adder (36), a subtractor (38), a second memory component (40), and a controller (52). In each of a plurality of stages, the controller (52) enables... Agent: Hovey Williams LLP

20080109508 - System having a carry look-ahead (cla) adder: In a system having stored operands in various locations, addition is performed without having to store the operands in preparation for an add operation. Bitwise propagate and generate terms are efficiently created to speed up additions in the system. Combinational logic circuitry has a plurality of inputs and provides a... Agent: Freescale Semiconductor, Inc. Law Department

20080104153 - Multimode mathematical user interface: Aspects of the present disclosure include a quick and easy user interface system for allowing a user to format mathematical expression on a math program as they would be formatted in longhand. The user interface is configured to switch between a linear math expression entry scheme and a structured math... Agent: Knobbe Martens Olson & Bear LLP

20080104155 - Digital electronic binary rotator and reverser: A binary rotator which comprises an array of n cascaded 2-input multiplexer banks (104) and receives at an input (102) 2n-bit binary data words can be used not only for rotation but also for selective reversal, without the necessity of the addition of a further multiplexer bank dedicated to the... Agent: Flynn Thiel Boutell & Tanis, P.C.

20080104154 - Normalization processing apparatus: A normalization processing apparatus according to an embodiment of the present invention can calculate all of normalization processing output values, that is, the output value of the size of a region, the output value of the lowest value in the region, the output value of the number of non-output bits,... Agent: Canon U.s.a. Inc. Intellectual Property Division

20080104156 - Random number generators and systems and methods relating to the same: A random number generator comprising a sigma-delta modulator, the sigma-delta modulator having a modulation unit and a feedback loop arranged to receive a digital output signal from the modulator and form an adjustment signal in dependence on the digital output signal such that at any given time the absolute difference... Agent: Greenberg Traurig LLP (la)

20080104157 - Efficient implementation of filters for mimo fading: A single finite impulse response filter designed to operate on a single signal is used in conjunction with an input multiplexer that interleaves samples from multiple signals and an output decimator. The output of the decimator contains interleaved samples of the multiple signals with independent filtering applied to each.... Agent: Agilent Technologies Inc.

20080104158 - Implementation of adaptive filters of reduced complexity: Herein described is at least a method for implementing an adaptive digital filter of reduced implementation complexity. The method comprises computing at least one complex discrete Fourier transform of a complex data sequence using approximately one-half the number of points used in computing said discrete Fourier transform of a real... Agent: Mcandrews Held & Malloy, Ltd

20080104159 - Harware arithmetic engine for lambda rule computations: A recursive lambda rule engine (114, 302) includes a first multiplier (204) that sequentially multiplies each of series of inputs by a nonlinearity determining parameter and supplies results to a second multiplier (214) that multiplies the output of the first multiplier (204) by a previous output of the engine (114,... Agent: Motorola, Inc.

20080104160 - Operation method and apparatus: Precision of arithmetic operations on floating-point numbers is improved while also preventing an increase in the amount of processing. A second converter converts an exponent included in an exponent field according to an exponent conversion rule defined in accordance with a function. A storage stores in a table a value... Agent: Katten Muchin Rosenman LLP

20080104161 - Integrated conversion method and apparatus: An integrated transformation apparatus is provided. The apparatus includes a first multiplexer, a second multiplexer, and a transformation unit. The first multiplexer retrieves point data from columns or rows of a multi-dimensional matrix and input data. The second multiplexer retrieves transformation coefficients corresponding to the point data. The transformation unit... Agent: Quintero Law Office, PC

20080104162 - Data processing apparatus and data processing method: An apparatus determines a communication protocol for transmitting data, adds a calculation result of checksum calculation to the data and transmits the result with the data, and stores the calculation result in a memory according to a communication protocol determination.... Agent: Canon U.s.a. Inc. Intellectual Property Division

20080104163 - Non-uniform sampling to avoid aliasing: A method for sampling includes selecting and sampling at uniform time steps over a collection time that is more than one period. Reordering the collected samples into “one period” and transforming the period from the time domain to the frequency domain.... Agent: Agilent Technologies Inc.

20080104164 - Reconfigurable simd vector processing system: A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products... Agent: Buckley, Maschoff & Talwalkar LLC