Electrical computers: arithmetic processing and calculating inventions 03/08

20080077643 - Bit field operation circuit: A bit field operation circuit has a first shift unit, a mask shift amount control circuit, a second shift unit, a logic operation unit, and a selection unit. The first shift unit outputs a first intermediate data based on a first control signal. The mask shift amount control circuit outputs... Agent: Nixon Peabody, LLP

20080077644 - Systems and methods for wavefront analysis over circular and noncircular pupils: Systems, methods, and software for determining a set of analytical or numerical polynomials that is orthonormal over circular or noncircular pupils are described. Closed-form orthonormal polynomials for circular, annular, hexagonal, elliptical, rectangular, and square pupils are derived. Such techniques can be applied to ray tracing as in the optical design... Agent: Townsend And Townsend And Crew, LLP

20080077645 - System and method for efficient basis conversion: This invention describes a method for evaluating a polynomial in an extension field FqM, wherein the method comprises the steps of partitioning the polynomial into a plurality of parts, each part is comprised of smaller polynomials using a q−th power operation in a field of characteristic q; and computing for... Agent: Blake, Cassels & Graydon LLP

20080077646 - Method for designing distributing frame: A method for designing a distributing frame and a computer readable medium having computer instructions thereon for causing a computer to perform the method. The distributing frame may include a first distribution portion having a first series of verticals, and a first series of horizontal shelves; a second distribution portion... Agent: David Aker

20080077647 - Parameterized vlsi architecture and method for binary multipliers: Systems and methods of multiplying binary numbers are disclosed. In one such system there is a Sigma unit and an Omega unit. The Sigma unit may generate partial sums of the multiplier and shifted forms of the multiplier. The Omega unit may have a plurality of control units, a plurality... Agent: Hodgson Russ LLP The Guaranty Building

20080071846 - Processor architecture for programmable digital filters in a multi-standard integrated circuit: An architecture for a cascaded digital filters comprises independently programmable controlling registers and independent interpolating factors; a digital to analog converter for converting the digital signals into analog signals with a constant sampling rate which matches with the interpolating factors of the cascaded digital filters. Each filter property (filters order,... Agent: Texas Instruments Incorporated

20080071848 - In-place radix-2 butterfly processor and method: A butterfly processor architecture including a single high speed multiplier unit and two adder/subtracter units structured to efficiently perform radix-2 decimation-in-time (DIT) butterfly operations is disclosed. The computations for windowing operations, FFT operations, and IFFT operations may be realized in terms of butterfly operations. Therefore, the butterfly processor architecture may... Agent: Texas Instruments Incorporated

20080071847 - Method for transforming data by look-up table: Provided is a method for transforming data using a look-up table. The method includes the steps of: (a) mapping preprocessed input binary data to a constellation diagram divided into four quadrants to output a first complex number; (b) performing addition/subtraction operations between real numbers and between imaginary numbers with respect... Agent: Ladas & Parry LLP

20080071849 - Polynomial method for detecting a hamiltonian circuit: An NP-complete problem can be transformed in polynomial time into any known NP problem. The Hamiltonian circuit problem may be transformed into any other known NP problem (such as the Traveling Salesman problem) and has applications in any context that can be represented by a graph, map, or network structure.... Agent: Mckenna Long & Aldridge LLP

20080071850 - Methods and apparatus for extracting integer remainders: Methods and apparatus to determine a remainder value are disclosed. A disclosed example method involves, during a compilation phase, causing a processor to multiply a dividend value by a first value to generate a second value associated with a product. The first value is associated with a scaled approximate reciprocal... Agent: Hanley, Flight & Zimmerman, LLC

20080071851 - Instruction and logic for performing a dot-product operation: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.... Agent: Trop, Pruner & Hu, P.C.

20080071852 - Method to perform a subtraction of two operands in a binary arithmetic unit plus arithmetic unit to perform such a method: A method and apparatus is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the... Agent: International Business Machines Corporation Dept. 18g

20080065709 - Fast correctly-rounding floating-point conversion: A system and method for converting bases of floating point numbers with improved rounding over an entire exponent range includes identifying exceptional conversions for a given source precision to target precision. A representation of the exceptions is stored in a bit vector for use during conversion execution.... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080065710 - Optical-based, self-authenticating quantum random number generators: Various embodiments of the present invention are directed to methods and systems for generating random numbers. In one embodiment, a quantum random number generator comprises: a state generator configured to generate a quantum system in a coherent state; a polarization states analyzer configured to project the quantum system onto one... Agent: Hewlett Packard Company

20080065711 - System and method for fast walsh transform processing in a multi-coded signal environment: A flexible Fast Walsh Transform circuit provides configurable FWT sizes, and is suitable for use in radio receivers where the received signal may be generated using varying spreading codes and/or varying numbers of multi-codes. Such signal types are commonly encountered in wireless communication systems like those based on the Wideband... Agent: Coats & Bennett, PLLC

20080065712 - Automated data alignment based upon indirect device relationships: A noisy data alignment algorithm for determining cycle count offsets for noisy pairs of n monitoring devices. A direct cycle count offset matrix is determined based upon the highest correlation coefficients produced by correlating frequency variation data from each device pair Dij. For each direct cycle count offset Mij, indirect... Agent: Schneider Electric / Square D Company Legal Dept. - I.p. Group (np)

20080065713 - Signal processing apparatus and method for performing modular multiplication in an electronic device, and smart card using the same: Provided is an apparatus for encryption/decryption and electronic signature in a mobile communication environment. A signal processing apparatus, performing modular multiplication in an electronic device, includes a first logic for outputting a signed multiplicand by selectively performing a one's complementary operation on a multiplicand according to a Booth conversion result... Agent: The Farrell Law Firm, P.C.

20080065714 - Device and method for calculating a result of a modular multiplication with a calculating unit smaller than the operands: For calculating a result of a modular multiplication with long operands, at least the multiplicand is divided into at least three shorter portions. Using the three shorter portions of the multiplicand, the multiplier and the modulus, a modular multiplication is performed within a cryptographic calculation, wherein the portions of the... Agent: Dickstein Shapiro LLP

20080059546 - Methods and apparatus for providing a scalable motion estimation/compensation assist function within an array processor: An apparatus is described for attaching a motion search hardware assist unit to a processing element and its local memory. A current macro block storage unit is attached to a local memory interface unit for storage of a copy of a current macro block from the local memory. A search... Agent: Gerald G. Pechanek

20080059547 - Method and computer system for extrapolating changes in a self-consistent solution driven by an external parameter: The invention relates to a method an computer system for using extrapolation analysis to express an approximate self-consistent solution or a change in a self-consistent solution based on a change in the value of one or more external parameters, said self-consistent solution being used in a model of a system... Agent: Gifford, Krass, Sprinkle,anderson & Citkowski, P.c

20080059548 - Image processing apparatus, image processing method, and image processing program: An image processing apparatus is disclosed that includes an input unit that inputs data subject to image processing, an input filter that controls data input operations of the input unit, an output unit that outputs processed data resulting from the image processing, an output filter that controls data output operations... Agent: Cooper & Dunham, LLP

20080059549 - Molecular orbital computing device for elongation method: where YCMORLMO is a transformation matrix for transforming into a regional localized molecular orbital by a canonical molecular orbital basis, CROCMO+ is a transpose matrix of a matrix representing a canonical molecular orbital by a regional atomic orbital basis, U is a transformation matrix for erasing elements in an off-diagonal... Agent: Osha Liang L.L.P.

20080059550 - Sampled data averaging circuit: A sampled data averaging circuit which comprises sampling means for sampling input data at predetermined timing by a number of sampling times set, division means for dividing the sampled data by the number of sampling times for each time the input data is sampled, and accumulation means for sequentially accumulating... Agent: Nixon Peabody, LLP

20080059551 - Device and method for composing codes: Configurable vector processors can be equipped with code generators, so that they are capable of handling different standards and codes. Furthermore, they can be arranged to provide support for related functions such as cyclic redundancy check (CRC). A configurable vector processor would then be equipped with a plurality of generators... Agent: Nxp, B.v. Nxp Intellectual Property Department