Electrical computers: arithmetic processing and calculating inventions 11/07

20070276889 - Method for creating a representation of a calculation result linearly dependent upon a square of a value: In the transition into the logarithmic range, not the entire bit width of the result linearly dependent upon the square of the value must be considered. Rather, it is possible to scale the result of a value with x bits such that a representation with less than x bits of... Agent: Glenn Patent Group

20070276890 - Tamper proof generation of true random numbers: A method and a device generate a truly random number. The novel method obtains the true random number on the basis of a stochastically distributed duration of an electric charge exchange or charge reversal process. The processes for charge exchange in memory cells, for example the EEPROM or FLASH memory... Agent: Lerner Greenberg Stemer LLP

20070276891 - Pulse output direct digital synthesis circuit: A clock signal generator responsive to a frequency control word and a reference clock signal having a reference clock frequency fref. The clock signal generator generates an output clock signal having a frequency fgen, wherein fgen is less than fref. A modulo-N counter accepts the reference clock signal as input.... Agent: Dr. Mark M. Friedman C/o Bill Polkinghorn - Discovery Dispatch

20070276892 - Finite impulse response filter and digital signal receiving apparatus: An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions,... Agent: Greenblum & Bernstein, P.L.C

20070276893 - Method for performing a domain transformation of a digital signal from the time domaiain into the frequency domain and vice versa: A method for performing a domain transformation of a digital signal from the time domain into the frequency domain and vice versa, the method including performing the transformation by a transforming element, the transformation element comprising a plurality of lifting stages, wherein the transformation corresponds to a transformation matrix and... Agent: Paul J. Backofen Crockett & Crockett

20070276894 - Process and device for determining a transforming element for a given transformation function, method and device for transforming a digital signal from the time domain into the frequency domain and vice versa and computer readable medium: According to the process for determining a transform element for a given transformation function, which transformation function comprises a transformation matrix and corresponds to a transformation of a digital signal from the time domain into the frequency domain or vice versa, the transformation matrix is decomposed into a rotation matrix... Agent: Crockett & Crockett

20070276895 - Low-voltage cmos circuits for analog decoders: Low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits, suitable for analog decoders, for example, are provided. The circuits include multiplier modules that receive first input signals and respective ones of a plurality of second input signals. Each multiplier module generates as output signals products of the first input signals and its... Agent: Ralph A. Dowell Of Dowell & Dowell P.C.

20070276896 - Affinity-based clustering of vectors for partitioning the columns of a matrix: A method for partitioning the columns of a matrix A. The method includes providing the matrix A in a memory device of a computer system. The matrix A has n columns and m rows, wherein n is an integer of at least 3, and wherein m is an integer of... Agent: Schmeiser, Olsen & Watts

20070271319 - Apparatus for an method of signal processing: A set of related methods of demodulating amplitude and frequency modulated signals. The emphasis is on using an iterative approach to separate an envelope signal and a frequency modulated signal from which a physically meaningful, non-negative instantaneous frequency can be derived. Three schemes are presented. The first scheme represents signals... Agent: Manelli Denison & Selter Attn: William H. Bollman

20070271320 - Random pulse generation source, and semiconductor device, method and program for generating random number and/or probability using the source: The present invention provides a semiconductor device such as an IC capable of generating completely random signals and generating an authentication signal, random number, and probability by integrally setting a random pulse generation source for spontaneously generating at the inside, and also provides a method/program for generating a random number... Agent: Kubovcik & Kubovcik

20070271321 - Transforms with reduce complexity and/or improve precision by means of common factors: Techniques for efficiently performing transforms on data are described. In one design, an apparatus performs multiplication of a group of data values with a group of rational dyadic constants that approximates at least one irrational constant scaled by a common factor. Each rational dyadic constant is a rational number with... Agent: Qualcomm Incorporated

20070271322 - Computer graphics systems and methods using stratification by rank-1 lattices: A computer program product for a computer graphics system comprises computer executable instructions recorded on a computer-readable medium: instructions executable to enable the computer to generate a selected number of sample points over an integration domain, such that there is at least one sample point in each of a plurality... Agent: Jacobs & Kim LLP

20070271323 - Compound galois field engine and galois field divider and square root engine and method: A Galois field divider engine and method inputs a 1 and a first Galois field element to a Galois field reciprocal generator to obtain an output, multiplies in a Galois field reciprocal generator a first Galois field element by a first element of the Galois field reciprocal generator for predicting... Agent: Iandiorio & Teska

20070271324 - Computational method for sizing three-phase separators: A method and software for sizing three-phase separators utilizing an iterative approach is provided. The proposed computational method for sizing three-phase separators uses an iterative technique that calculates the optimum vessel dimensions for each service over a range of length to diameter ratios. The method starts with the smallest vessel... Agent: Bracewell & Giuliani LLP

20070271325 - Matrix multiply with reduced bandwidth requirements: Systems and methods for reducing the bandwidth needed to read the inputs to a matrix multiply operation may improve system performance. Rather than reading a row of a first input matrix and a column of a second input matrix to produce a column of a product matrix, a column of... Agent: Patterson & Sheridan, L.L.P.

20070271326 - Technical solution to written calculations engineering of the digital engineering method for hybrid numeral carry system and carry line: The present invention relates to the digital engineering method and the field of written calculation engineering, and it puts forward a new digital engineering method which could remarkably increase the computation speed and greatly reduce the error rate of written calculation. The present invention uses the “method of hybrid numeral... Agent: Bachman & Lapointe, P.C.

20070266067 - Pseudo random number generator: A pseudo-random number generator 100 generates a pseudo-random number by the following operation. At C.2, S1[B41] is determined from B41 set in a second internal memory, and S2[B40] is determined from B40. Then, R[J] is generated from S1[I], S1[B41], and S2[B40]. At C.3, S1[I] is newly generated based on S1[B41]... Agent: Birch Stewart Kolasch & Birch

20070266068 - Method and apparatus for integer transformation using a discrete logarithm and modular factorization: Transforming an integer comprises receiving the integer, where the integer can be expressed as a modular factorization. The modular factorization comprises one or more factors, where each factor has an exponent. The integer is expressed as a product of residues. A discrete logarithm of the integer is established from a... Agent: Baker Botts L.L.P.

20070266069 - Multi-dimensional hybrid and transpose form finite impulse response filters: Multi-dimensional finite impulse response filters ale disclosed in hybrid and transpose forms. Multi-dimensional signals can be expressed in a vector (ox matrix) form to allow multi-dimensional signals to be processed collectively. Known hybrid and transpose FIR filters are extended to the multi-dimensional case to allow multi-dimensional signals to be processed... Agent: Ryan, Mason & Lewis, LLP

20070266070 - Split-radix fft/ifft processor: This invention presents a CORDIC-based split-radix FFT/IFFT (Fast Fourier Transform/Inverse Fast Fourier Transform) processor dedicated to the computation of 2048/4096/8192-point DFT (Discrete Fourier Transform). The arithmetic unit of butterfly processor and twiddle factor generator are based on CORDIC (Coordinate Rotation Digital Computer) algorithm. An efficient implementation of CORDIC-based split-radix FFT... Agent: Bacon & Thomas, PLLC

20070266071 - Mode-based multiply-add recoding for denormal operands: In a denormal support mode, the normalization circuit of a floating-point adder is used to normalize or denormalized the output of a floating-point multiplier. Each floating-point multiply instruction is speculatively converted to a multiply-add instruction, with the addend forced to zero. This preserves the value of the product, while normalizing... Agent: Qualcomm Incorporated

20070266072 - Method and apparatus for decimal number multiplication using hardware for binary number operations: According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are... Agent: Intel Corporation C/o Intellevate, LLC

20070266073 - Method and apparatus for decimal number addition using hardware for binary number operations: According to embodiments of the subject matter disclosed in this application, decimal floating-point additions and/or decimal fixed-point additions may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are... Agent: Intel Corporation C/o Intellevate, LLC

20070260656 - Method and apparatus for diagnosing a mechanism: P

20070260657 - Information processing apparatus, information processing method, and program: A method of processing information of an apparatus including first storage means for storing an encrypted application program and data, second storage means for loading a decrypted application program and data and execution means for executing the application program loaded in the second storage section, and controlling a reader/writer reading... Agent: Rader Fishman & Grauer PLLC

20070260658 - Optical-based, self-authenticating quantum random number generators: Various embodiments of the present invention are directed optical-based quantum random number generators. In one embodiment, a quantum random number generator includes an input state generator that generates a first optical quantum system and a second optical quantum system in an entangled state, a detector that measures the state of... Agent: Hewlett-packard Company Intellectual Property Administration

20070260659 - Computing filter coefficients for an equalizer in a communication receiver: The present invention provides an equalizer (200) and a method for computing equalizer filter coefficients in a communication receiver. The equalizer filter coefficients are computed on the basis of a real matrix T which is generated from channel estimation vector f, which is derived from the channel estimation inputs.... Agent: Mcginn Intellectual Property Law Group, PLLC

20070260660 - Efficient mapping of fft to a reconfigurable parallel and pipeline data flow machine: A system comprises first and second local memory banks; and a reconfigurable ALU array having multiple configurations including: a first for performing an inverse butterfly operation, a second for performing a multiplication operation, a third for performing parallel subtraction and addition, and a fourth for performing an inverse N-point shuffle.... Agent: Thelen Reid Brown Raysman & Steiner LLP

20070260661 - Apparatus, methods, and computer program products for determining the coefficients of a function with decreased latency: The present invention provides apparatus, methods, and computer program products that can decrease the latency with which the coefficients of a function representative of signal are determined. Specifically, the apparatus, methods, and computer program products of the present invention, taking advantage of the independence of samples, updates each of the... Agent: Alston & Bird LLP

20070260664 - Computation of a multiplication operation with an electronic circuit and method: A computing method and circuit for computing a modular operation with at least one operand having a binary representation. Iteratively for each bit of this operand, doubling the value of an intermediate result stored in a first memory element by shifting the bits of the intermediate result towards the most... Agent: Graybeal, Jackson, Haley LLP

20070260662 - Controlled-precision iterative arithmetic logic unit: A controlled-precision Iterative Arithmetic Logic Unit (IALU) included in a processor produces sub-precision results, i.e. results having a bit precision less than full precision. In one embodiment, the controlled-precision IALU comprises an arithmetic logic circuit and a precision control circuit. The arithmetic logic circuit is configured to iteratively process operands... Agent: Qualcomm Incorporated

20070260663 - Cyclic segmented prefix circuits for mesh networks: Parallel prefix circuits for computing a cyclic segmented prefix operation with a mesh topology are disclosed. In one embodiment of the present invention, the elements (prefix nodes) of the mesh are arranged in row-major order. Values are accumulated toward the center of the mesh and partial results are propagated outward... Agent: Ibm Corp. (mrn) C/o Law Office Of Michael R. Nichols

20070260665 - Method of specifying and tracking precision in floating-point calculation: A new floating-point representation and arithmetic called precise representation and arithmetic enables efficient precision storage and tracking during arithmetic operations by (1) discarding the normalization process of conventional arithmetic; (2) reinterpreting the floating-point representation of a signed significand on an exponent as a value based on a precision; (3) providing... Agent: Wang, Chengpu

20070260666 - Efficient encoding and access of mathematically precise variable precision numeric types: A method of encoding variable-precision numeric types that includes determining a fixed numeric storage size used by a computer system, encoding numeric values that do not fit into the fixed size in a variable-precision numeric value allocated on a program heap and generating a reference to point to the variable-precision... Agent: Hunton & Williams LLP Intellectual Property Department

20070260667 - Multi-thread spreadsheet processing with dependency levels: This disclosure relates to a method and system of processing chain calculations in spreadsheet applications utilizing multiple processors, each having a separate recalculation engine. A single calculation chain may be reordered into a unified chain where supporting and dependent formulas are organized into a tree hierarchy of child chains. The... Agent: Merchant & Gould (microsoft)

20070255776 - Processor system including processor and coprocessor: A processor includes a first register, a control section and an arithmetical section. The processor has a first operation mode which allows the first area of a first register to be accessed and a second operation mode which allows a second area of the first register to be accessed. The... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070255777 - Method for generating random number and random number generator: It is an object of the present invention to provide, with simple and not expensive devices, a new method for generating random number with more perfectly disorder and a random number generator which is utilized in the generating method of random number. In this point of view, a noise or... Agent: Oliff & Berridge, PLC

20070255778 - Software method for solving systems of linear equations having integer variables: This invention describes a software method for computers for solving integer programming problems containing systems of linear equations where part of or all of the variables may take only integer values. Said software method consists of 3 main steps. First, all of or part of said system is regularized such... Agent: Jean-paul Theis

20070255779 - Method for solving implicit reservoir simulation matrix: A method for solving a matrix equation AX=B, wherein A represents a block sparse matrix, B represents a right hand side block vector and X represents a solution block vector. In one embodiment, the method includes receiving the block sparse matrix and the right hand side block vector, constructing a... Agent: Brent R. Knight Exxonmobil Upstream Research Company

20070255780 - Method and system for creating a multiplication and division puzzle: A multiplication and division puzzle and method of making thereof include a main table having a plurality of cells in rows and columns, the cells being filled with products and multipliers. A template having a plurality of cells that correspond to the plurality of cells in the main table has... Agent: Rhonda Barton