Electrical computers: arithmetic processing and calculating inventions 10/07

20070250554 - Output buffer receiving first and second input signals and outputting an output signal, and corresponding electronic circuit: An output buffer is provided, to which first and second input signals are applied and that delivers an output signal. The output buffer includes a second offset switching stage installed in cascade downstream from a first switching stage. The second offset switching stage generates control points shifted in time with... Agent: Westman Champlin & Kelly, P.A.

20070250555 - Apparatus and method of equalisation: To reduce the number of components needed when compared with an exact-calculation analog equaliser, an analog equaliser is characterised by iterative means arranged in operation to generate an estimate of marginal posterior expectations for received bit values.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070250556 - Read channel operable to calibrate a coefficient of a filter, such as an fir filter, disposed before an interpolated-timing-recovery circuit, and related integrated circuit, system, and method: An embodiment of a read channel includes a filter, an interpolator, a recovery circuit, an error detector, a reverse interpolator, and a filter calibrator. The filter is operable to receive a raw sample of a signal and a coefficient-correction value, generate a filtered sample from the raw sample and a... Agent: Graybeal Jackson Haley LLP Bryan A. Santarelli

20070250557 - Method and circuit for performing cordic based loeffler discrete cosine transformation (dct) for signal processing: A low-power and high-quality DCT transformation based on the Cordic method is presented. The proposed Cordic based Loeffler DCT architecture only requires 38 add and 16 shift operations to carry out the DCT transformation. The complexity is almost the same as the complexity of the binDCT-C5. The simulation results show... Agent: Jianq Chyun Intellectual Property Office

20070250558 - Method and device for performing spectrum analysis of a wanted signal or noise signal: A method and device for performing spectrum analysis of a signal in a plurality of frequency bands with respective different frequency resolutions. Said method comprises a data acquisition step and a subsequent data evaluation step for every frequency band. The data acquisition step and the subsequent data evaluation step proceeds... Agent: Marshall, Gerstein & Borun LLP

20070250559 - Broadband transfer function synthesis using orthonormal rational bases: In order to generate a broadband transfer function of complex characteristics of a linear time-invariant (LTI) system, data characterising properties of the system are acquired. A set of poles in the complex plane are defined to characterise the system, and then an iterative process is performed to: define a set... Agent: Perman & Green

20070244943 - Methods and apparatus for providing a reduction array: Methods and apparatus provide for accumulating bit streams from four partial products and producing a carry-save output pair, including: producing the save, S, portion of the carry-save output pair, in accordance with the following Boolean expression: S=d3 XOR ((d0 XOR d1) XOR (d2 XOR Cin)), wherein d0, d1, d2, d3... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20070244944 - Method of processing information to be confidentially transmitted: A method of processing information to be confidentially transmitted from a first module to a second module provides that a first scalar multiplication may be carried out in order to obtain a first result [r]P). This first scalar multiplication comprises a plurality of generation steps of ordered factors from which... Agent: Seed Intellectual Property Law Group PLLC

20070244945 - Analog circuit arrangement for creating elliptic functions: An analog circuit system for generating output signals whose curve shape, at least sectionally, corresponds or is approximate to an elliptic function. Standard analog components such as adders, integrators, multipliers and differential amplifiers can be interconnected in order to simulate elliptic time functions from the standpoint of circuit engineering.... Agent: Kenyon & Kenyon LLP

20070244946 - Communication device and method to derive context information: A communication device comprises processing means, storage means for storing a database of language components, display means and user interface means. The processing means is arranged to determine at least one qualifier, to access the database, and to select at least one language component according to the at least one... Agent: Ibm Corporation Intellectual Property Law

20070244947 - Memory based computation systems and methods for high performance and/or fast operations: In the preferred embodiments, a high performance logic circuit is disclosed that includes: a logic circuit divided into smaller blocks, which smaller blocks being implemented with Read Only Memory in which outputs corresponding to input combinations are pre-stored; and inputs to each of said smaller blocks being used as an... Agent: Watchstone P+d, PLC

20070244948 - Memory transfer with early access to critical portion: In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second... Agent: Marger Johnson & Mccollom, P.C.

20070244949 - Method for generating the multiplicative inverse in a finite field gf(p): The essence of the invention is an effective method for generating the multiplicative inverse in a finite field GF(p) where p is prime, i.e. for generating the modular inverse. This method is derived from the Extended Euclidean Algorithm (EEA). The method is for binary execution of operations during the process... Agent: Egbert Law Offices

20070244950 - Method and apparatus for generating random data: An apparatus for generating random data includes a raw random sequence source adapted to generate a raw random sequence and a digital post processor adapted to process the raw random sequence to generate the random data, wherein the digital post-processor includes a synchronous finite state machine having at least one... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070244951 - Accelerated throughtput synchronized word stream cipher, message authenticator and zero-knowledge output random number generator: Systems and methods are disclosed, especially designed for very compact hardware implementations, to generate random number strings with a high level of entropy at maximum speed. For immediate deployment of software implementations, certain permutations have been introduced to maintain the same level of unpredictability which is more amenable to hi-level... Agent: Kinney & Lange, P.A.

20070244952 - Signal analysis methods: The invention relates to a method of comparing two or more series of signal analysis data samples, to produce a measure of their similarity. Corresponding data samples of each series are compared, and measures of the magnitude of the signal and the variation between corresponding data samples are calculated. The... Agent: Greenblum & Bernstein, P.L.C

20070244953 - Method and apparatus to perform multiply-and-accumulate operations: A method and corresponding circuit for determining a final result for a desired series of multiply-and-accumulate (MAC) operations are based on counting the occurrence of products in the desired series of MAC operations, multiplying the counts by their corresponding products to obtain partial sums, and adding the partial sums to... Agent: Coats & Bennett, PLLC

20070244955 - Method for locating a servo motor controller: The method of locating a servo motor controller's position of the present invention utilizes accrual calculation method to ensure the positions of motor controller at each station of the production line is correctly obtained, wherein the last digit of the gear ratio is utilized to obtain a critical value so... Agent: Dykema Gossett, PLLC

20070244954 - Fused booth encoder multiplexer: A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer... Agent: Ibm Corporation (jvm)

20070244956 - Digital computation method involving euclidean division: A computational method for implementation in an electronic digital processing system performs integer division upon very large (multi-word) operands. An approximated reciprocal of the divisor is obtained by extracting the two most significant words of the divisor, adding one to the extracted value and dividing from a power of two... Agent: Schneck & Schneck

20070244961 - Configurable ic with configurable routing resources that have asymmetric input and/or outputs: Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. Each configurable interior tile includes a set of configurable logic... Agent: Adeli Law Group, A Professional Law Corporation

20070244958 - Configurable ic's with carry bypass circuitry: Some embodiments provide a configurable IC that includes several configurable logic circuits. The logic circuits include several sets of associated configurable logic circuits, each set for performing an add or subtract operation. For each set of associated configurable logic circuits, the configurable IC includes a carry circuit for performing a... Agent: Adeli Law Group, A Professional Law Corporation

20070244957 - Configurable ic's with configurable logic circuits that perform adder and/or subtractor operations: Some embodiments provide a configurable IC that includes a set of configurable logic circuits each for configurably performing a set of functions. A particular configurable logic circuit receives a configuration data set that defines the function that the particular logic circuit is to perform in the particular configurable logic circuit's... Agent: Adeli Law Group, A Professional Law Corporation

20070244959 - Configurable ic's with dual carry chains: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each of several sets of associated configurable logic circuits, the configurable IC includes first and second circuitry for establishing carry signal flow in two directions... Agent: Adeli Law Group, A Professional Law Corporation

20070244960 - Configurable ic's with large carry chains: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein... Agent: Adeli Law Group, A Professional Law Corporation

20070239808 - Systems and methods for multiple equation graphing: Various systems and methods for equation graphing are disclosed herein. For example, some embodiments of the present invention provide methods for graphing equations in a substantially real time environment. Such methods include receiving a first equation and a second equation, and parsing the equations such that they are each formatted... Agent: Texas Instruments Incorporated

20070239809 - Method for calculating a local extremum, preferably a local minimum, of a multidimensional function e(x1, x2, ..., xn): In case of P≧0: Analysing whether the number of conducted iteration steps since the last detected case of P<0 exceeds a given minimum number Nmin, in case of “no” returning to step b) and in case of “yes” increasing δti, decreasing α and return to step b).... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070239810 - Method and apparatus for providing packed shift operations in a processor: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon... Agent: Intel Corporation C/o Intellevate, LLC

20070239811 - Multiplication by one from a set of constants using simple circuitry: A cascaded multiplier is configured for multiplying an input value by one of a predetermined set of coefficients. Each multiplier stage performs a set of elementary operations, including shifting, signal selection, addition, and subtraction. Each multiplier stage is responsive to at least one input control signal to control at least... Agent: Tensorcomm, Inc.

20070239812 - Binary and n-valued lfsr and lfcsr based scramblers, descramblers, sequence generators and detectors in galois configuration: N-valued scramblers, descramblers, sequence generators and sequence detectors with Linear Feedback Shift Registers (LFSRs) in Galois configuration are disclosed. Methods for creating detectors and descramblers in Fibonacci configuration corresponding to generators and scramblers with LFSRs in Galois configuration are also disclosed. Methods to calculate the content of a shift register... Agent: Diehl Servilla LLC

20070239813 - Method and system of utilizing a context vector and method and system of utilizing a context vector and database for location applications: A system (100) and method (300) of using a context vector and database (202) for location applications can include a transceiver (104), a plurality of environmental sensors (114, 116, 118, 120, 121) including at least two location technology devices (110, 112), and a processor (102) coupled to the transceiver and... Agent: Motorola, Inc Intellectual Property Section

20070239814 - Statistical control of adaptive ocular filter stability: An electroencephalograph system and method for controlling the stability of an adaptive filter during high noise spikes in ocular sensor channels. The method comprises receiving a signal from at least one sensor and determining when an adaptive filter algorithm is subject to becoming unstable based on a signal from the... Agent: Honeywell International Inc.

20070239815 - Pipeline fft architecture and method: Techniques for performing Fast Fourier Transforms (FFT) are described. In some aspects, calculating the Fast Fourier Transform is achieved with an apparatus having a memory (610), a Fast Fourier Transform engine (FFTe) having one or more registers (650) and a delayless pipeline (630), the FFTe configured to receive a multi-point... Agent: Qualcomm Incorporated

20070239817 - Rounding computing method and computing device therefor: A computing device has a rounding processor that inputs therein a set of plural (K) input data IN1 through INK comprising z bits. The rounding processor selects an ensured bit field depending upon the state of usage of each of specific areas A of upper z/2 bits of the 32-bit... Agent: Nixon Peabody, LLP

20070239816 - Formation process for logical and control functions in information processing and control systems: The invention concerns generally radio electronics in particular it relates to computer facilities and can be used in information processing and control systems. The process includes an operation of input of two data to be compared; the first operation of addition of instantaneous values of input data quantities; the first... Agent: I. Zborovsky

20070233758 - Method of high-speed video motion detection: An algorithm for the high-speed detection of temporal motion in a video signal by means of a digital high-pass filter which is applied to corresponding digital picture elements in sequential video frames. The resulting array of filtered values represents areas which are in motion within the video sequence, typically in... Agent: Daniel D. Moss

20070233759 - Platform for seamless multi-device interactive digital content: A multimedia information system includes multiple devices and provides automatic transfer of content between devices when any two of the devices are collocated, i.e., brought within a physical proximity and relative orientation of each other that allows each to detect the other, for example, using infrared data devices. The multimedia,... Agent: Shimokaji & Associates, P.C.

20070233760 - 3:2 bit compressor circuit and method: A circuit to convert three input bits (A, B and C) to a redundant format may include a first block with at least one transmission gate, and a second block with at least one static mirror. The first block may receive the three bits and output a sum bit, and... Agent: Buckley, Maschoff & Talwalkar LLC

20070233761 - Crossbar arithmetic processor: An arithmetic processing system is taught to be formed by combining a crossbar array with programming circuitry, input circuitry, and post-processing circuitry. The programming circuitry is configured to set crosspoints of the crossbar array to either a relatively high conductivity or a relatively low conductivity state corresponding to a logic... Agent: Blaise Mouttet

20070233762 - Techniques for random bit generation: Techniques are presented for randomly generating bits. A seed is inverted and a non repeating portion of the resulting digits from the inversion are retained. The inverted seed is then raised to a power to acquire another non repeating portion or additional digits. This process is repeated for a desired... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070233763 - Method and computer program for group delay and magnitude equalization with relaxed phase slope constraint: The present invention is a method and computer program for equalizing group delay and magnitude of a system for which a system response is known. The method and computer program are implemented via a finite impulse response (“FIR”) filter for the system, and the method broadly comprises the steps of:... Agent: Hovey Williams LLP

20070233764 - Transform design with scaled and non-scaled interfaces: Techniques for efficiently performing full and scaled transforms on data received via full and scaled interfaces, respectively, are described. A full transform is a transform that implements the complete mathematical description of the transform. A full transform operates on or provides full transform coefficients. A scaled transform is a transform... Agent: Qualcomm Incorporated

20070233765 - System and method for test generation for system level verification using parallel algorithms: A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070233768 - Method and circuit arrangement for computing a value of a complex signal: The invention relates to continuous computing of an averaged value of a complex signal, in which values are produced by iterative processing, such as CORDIC processing, from digital complex input values of in-phase and quadrature components (si, sq) of the complex signal. The smoothed value is provided by processing the... Agent: O'shea, Getz & Kosakowski, P.C. Suite 912

20070233767 - Rotator/shifter arrangement: Embodiments related to rotator/shifter arrangements are presented herein.... Agent: Lee & Hayes, PLLC C/o Intellevate

20070233766 - System and method for compiling scalar code for a single instruction multiple data (simd) execution engine: A system, method, and computer program product are provided for performing scalar operations using a SIMD data parallel execution unit. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using vector operations in a SIMD data parallel execution unit. The scalar... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070233769 - A scalable, faster method and apparatus for montgomery multiplication: Montgomery multiplication can be computed quickly by using carry save adders and parallel multipliers. We present an enhanced technique for very fast Montgomery multiplication that can be used for RSA calculations. This invention utilizes a scalable bit word implementation, suitable for very large bit encryptions. Such designs can be deployed... Agent: Michael Moshier

20070233770 - Method of validating a number in an electronic device and associated electronic device: The present invention relates to a method of validating a number comprising a plurality of digits, the number having a maximum value, each digit being successively entered by a user during several stages. The method includes a test stage activated when the number of digits entered is equal to that... Agent: Joseph J. Laks, Vice President Thomson Licensing LLC

20070233771 - Calculation apparatus and storage medium in which calculation program is stored: In a graphing calculator, a decimal calculation unit obtains a calculation result of an arithmetic expression input by an input device to an n-th digit and an (n+m)-th digit. When the values from the most significant digit to an (n+1)-th digit in the (n+m)-digit calculation result are zero, with respect... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070233772 - Modular multiplication acceleration circuit and method for data encryption/decryption: A system to process multiplier X and multiplicand Y may include multiplication of a least-significant bit of X and a least-significant w bits of Y to generate a least-significant w bits of product Z. The system may further include determination of whether a least-significant bit of product Z is 1,... Agent: Buckley, Maschoff & Talwalkar LLC Attorneys For Intel Corporation

20070233773 - Modular binary multiplier for signed and unsigned operands of variable widths: A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070233774 - Rounding of binary integers: Methods and apparatus to provide rounding of a binary integer are described. In one embodiment, a value that indicates whether a divisor divides a binary integer is extracted from a product of the binary integer and a scaled approximate reciprocal of the divisor.... Agent: Caven & Aghevli LLC Portfolioip