Electrical computers: arithmetic processing and calculating inventions 09/07

20070226283 - Easily graspable numerical expression display apparatus: When a numerical expression (FIG. 6(a)) is inputted to a mathematical calculator (1) and then a rough display key (27) is depressed, calculation units composing the numerical expression are converted to display blocks, whereby the numerical expression is displayed in a natural expression form on a display (3) and a... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070226284 - Electronic device: A storing unit stores therein a plurality of different display language data that is switchable according to a use environment of a user. A selecting unit selects a display language data from the storing unit in response to display language specification information supplied from a main unit at a time... Agent: Harness, Dickey & Pierce, P.L.C

20070226285 - A high speed fft hardware architecture for an ofdm processor: A novel technique for providing high speed FFT architecture for OFDM processors that reduces silicon area while maintaining the high speed requirement. In one example embodiment, this is accomplished by pipelined and/or sequential implementation of two or more FFT stages so that each stage performs a small portion of the... Agent: GlobalIPServices, PLLC

20070226286 - Fast fourier transform apparatus: A data transform system performs FFT and IFFT computations with respect to N data points. The data transform system performs radix-R (R is an integer) butterfly computation in parallel by use of M arithmetic elements. Serial and parallel computation structures a recombined to provide a system that provides for optimal... Agent: Mills & Onello LLP

20070226287 - Mimo receiver and method for beamforming using cordic operations: Embodiments of a MIMO receiver and method for beamforming using CORDIC operations are generally described herein. Other embodiments may be described and claimed. In some embodiments, complex singular value decomposition (SVD) operations are performed on a channel matrix using CORDIC operations to generate vector elements of a beamforming matrix. An... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070226288 - Processing method and computer system for summation of floating point data: A computer system execute summation processing even if the computing sequence is not adhered to in a system for computing a sum of floating point data of a plurality of nodes. Each node sends floating point data to a reduction mechanism, and the reduction mechanism computes the sums only for... Agent: Staas & Halsey LLP

20070226289 - Wireless receiver and its demodulating method: A wireless receiver which is used for a digital signal transmission system to wirelessly transmit a digital signal by packetizing and modifying it, selectively sets the shortest arithmetical bit length satisfying a required communication quality when performs demodulation arithmetical processing to demodulate a digital signal to be packet-transmitted, inputs a... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20070220073 - Digital filter and method for designing digital filters: A digital filter comprises a plurality of filter units each realizing mutually independent filter functions with a predetermined recursive filter order on a signal path between the input and the output of the filter and operating at a first clock rate, a plurality of sampling devices operating at the first... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070220075 - Race track betting calculator: A portable electronic device, e.g., a calculator, with the basic functions of addition, subtraction, multiplication and division with a dedicated program for a racing sport is disclosed herein. The calculator incorporates a progressive method of wagering in conjunction with the statistics of the sport to allow the user to calculate... Agent: Mccarter & English, LLP

20070220074 - Sharing of a logic operator having a work register: A circuit for calculating a discriminating function with successive iterations and with a work register on data divided into blocks, including: a single operator in wired logic for executing the function; a plurality of work registers sharing the operator; and an element for selecting one of the work registers to... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070220076 - Data processing apparatus and method for converting a number between fixed-point and floating-point presentations: The present invention provides a data processing apparatus and method for converting a number between fixed-point and floating-point representations. More particularly, the data processing apparatus comprises a data processing unit operable to execute instructions, with the data processing unit being responsive to a format conversion instruction to apply a format... Agent: Nixon & Vanderhye, PC

20070220077 - Frequency float method and system for realizing a signal filter: A method for realizing a digital filter in an electronic system. The method comprises first determining the specific number of coefficients to be calculated for a design filter and calculating the value of some of the coefficients for the design filter, typically all but one. Next, a reference filter is... Agent: Jablonski And Reid, PLLC

20070220078 - Data processing apparatus incorporating a numeric processing mechanism: A data processing apparatus uses numeric processing. A corrective mechanism enables a method for performing accurate integer divisions to be derived from an approximate division method which does not, of itself, always produce an accurate result but for which the range of errors is known. By applying the corrective mechanism... Agent: Ibm Corp,IPLaw Dept T81/503

20070214200 - Gain calibration in emccd cameras: A CCD device of the type which provides gain by impact ionisation in a multiplication register includes an arrangement for production of a first output signal derived from a known input with multiplication applied and a second output signal derived from a different input with unit gain applied. Using the... Agent: Venable LLP

20070214201 - Units conversion using flexible, parseable syntax: The present invention relates to tools for converting dimensional, numerical values from one set of units to another quickly and efficiently. More particularly, it relates to improved, computer-based systems, methods and software for changing between different units and for converting to and from a pre-specified standard set of units. The... Agent: Anthony A. Renshaw

20070214202 - Method and apparatus for efficient data acquisition and interpolation: A method and apparatus for performing efficient interpolation of data sequences or signals is disclosed. A preferred embodiment of the present invention determines a suitable Gaussian quadrature to match given bandwidth and accuracy requirements. This Gaussian quadrature is then used to construct a suitable family of interpolating functions to represent... Agent: Beck And Tysver P.l.l.c.

20070214203 - Dividing method and apparatus: A dividing apparatus and method using coordinate rotation is disclosed. To this end, a plurality of rotation stages are sequentially performed until a divisor reaches a criterion and a rotation direction used in each of the plurality of stages is output. A division result acquired by performing rotation with respect... Agent: The Farrell Law Firm, P.C.

20070214204 - Negative two's complement numbering system: d

20070214205 - Modular binary multiplier for signed and unsigned operands of variable widths: A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070208791 - Method and apparatus for the compression and decompression of audio files using a chaotic system: A system for the compression and decompression of sections of audio files is provided. A library of basic waveforms is produced by applying selected digital initialization codes to a chaotic system. Each basic waveform is in one-to-one correspondence with an initialization code. A weighted sum of the selected basic waveforms... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070208792 - Method for compressing and decompressing a sequence of numbers: A method for compressing and decompressing sequences of floating-point numbers includes determining a minimum value and a maximum value of the floating point numbers of the sequence, determining a quantization step value as a function of the minimum and maximum values, compressing each floating point number of the sequence by... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070208793 - Digital filter and its designing method, designing apparatus, and program for designing digital filter: An original filter is connected to an adjustment filter in the longitudinal way. The original filter has a first filter coefficient of a symmetric numeric string. The adjustment filter has a second filter coefficient which realizing an invert frequency amplitude characteristic B contacting with a frequency amplitude characteristic A of... Agent: Connolly Bove Lodge & Hutz LLP

20070208794 - Conflict-free memory for fast walsh and inverse fast walsh transforms: An address generation component performs in-place address assignments and memory-selection circuitry provides a specific pattern of data storage to avoid memory conflicts that may occur during a fast Walsh transform (FWT) operation.... Agent: Tensorcomm, Inc.

20070208795 - Three-dimensional fourier transform processing method for shared memory scalar parallel computer: When a three-dimensional Fourier transform is performed on the data x (i, j, k), the Fourier transform is performed on each two-dimensional plane formed by a first dimension and a second dimension (two-dimensional array defined by i and j). Since data is stored in a continuous area in the direction... Agent: Staas & Halsey LLP

20070208796 - Methods and apparatus in finite field polynomial implementations: Methods and apparatus reducing the number of multipliers in Galois Field arithmetic are disclosed. Methods and apparatus for implementing n-valued Linear Feedback Shift Register (LFSR) based applications with a reduced number of multipliers are also disclosed. N-valued LFSRs with reduced numbers of multipliers in Fibonacci and in Galois configuration are... Agent: Diehl Servilla LLC

20070208797 - Single-level parallel-gated carry/majority circuits and systems therefrom: A carry/majority circuit, comprising a plurality of differential transistor pairs coupled in parallel and forming a pair of output nodes, with a single parallel gated level. Current is steered through a leg of the transistor pair having a higher input voltage.... Agent: Bae Systems Information And Electronic Systems Integration Inc.